irqchip fixes for 5.6, take #2

- Add workaround for Cavium/Marvell ThunderX unimplemented GIC registers
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCgAtFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAl5sr4YPHG1hekBrZXJu
 ZWwub3JnAAoJECPQ0LrRPXpD3YsP/RU5Sm/dfdz/+MxcyKQVuupTZrmASoV38Ssw
 UI66lAWyIj2UVcHwPE7bCmgQusBARerEP/R/vge+7Qvh7J6WbTi6twkra//hZThg
 a/lf18+HgD2dCjmPKdbA01jqH7TLWbBl04OtXSqdNkRBFn6hQkpyTZ8Ha/hvGxez
 OfxUIbEEJ++HGnUAM1QhVTFynluTVZeWn17WbSFLqB5IPnpPhnc/oMzi83hG8pOF
 ToX578HrmrcrdiznVusYDJjdwDCfwnd3hKymFyOklBbFFLmocxs0ZKaPy/h+H4dD
 +c3DICWESmwTC7vjmbVdeVZSeAqzN7qXV9XDvEkrZltv07bz+fcE7rxz+qwhdw1v
 Y8A91QhMWDD1uSz++VnOMZ9R7sL0beLWcklS1TfhMEbRYYJRBssZF5OLFRrqRbu3
 gHHUCBCZ8QL5WCM1ci+ujuku07tuuNbvNdAqmxw0Pu1SuyCdmNGbsOolth5OGHsz
 GxpbjU9y5bxcFf6gQdImN3EhbeZ8ZUMk3RGOfW4zAHJhlGrT1KriBCS6LLRzVrcE
 sbEKovtbShmbG8NDEt/Q5/PKRkGVJR2ePONw9/EsZRVA2I1TgMmx4LHn43DDCfcL
 dKEWnloTf5kYrcWDb5ErdbQrUa5387i+8UPfe5jcc6gtw8sDBeG7pyZJdrYURyho
 NIqxpJ7e
 =vneR
 -----END PGP SIGNATURE-----

Merge tag 'irqchip-fixes-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

Pull irqchip fixes from Marc Zyngier:

- Add workaround for Cavium/Marvell ThunderX unimplemented GIC registers

Documentation/arm64/silicon-errata.rst

@@ -110,6 +110,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154        |
 +----------------+-----------------+-----------------+-----------------------------+
+| Cavium         | ThunderX GICv3  | #38539          | N/A                         |
++----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456        |
 +----------------+-----------------+-----------------+-----------------------------+
 | Cavium         | ThunderX Core   | #30115          | CAVIUM_ERRATUM_30115        |

drivers/irqchip/irq-gic-v3.c

@@ -34,6 +34,7 @@
 #define GICD_INT_NMI_PRI	(GICD_INT_DEF_PRI & ~0x80)
 
 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996	(1ULL << 0)
+#define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539	(1ULL << 1)
 
 struct redist_region {
 	void __iomem		*redist_base;
@@ -1464,6 +1465,15 @@ static bool gic_enable_quirk_msm8996(void *data)
 	return true;
 }
 
+static bool gic_enable_quirk_cavium_38539(void *data)
+{
+	struct gic_chip_data *d = data;
+
+	d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539;
+
+	return true;
+}
+
 static bool gic_enable_quirk_hip06_07(void *data)
 {
 	struct gic_chip_data *d = data;
@@ -1502,6 +1512,19 @@ static const struct gic_quirk gic_quirks[] = {
 		.mask	= 0xffffffff,
 		.init	= gic_enable_quirk_hip06_07,
 	},
+	{
+		/*
+		 * Reserved register accesses generate a Synchronous
+		 * External Abort. This erratum applies to:
+		 * - ThunderX: CN88xx
+		 * - OCTEON TX: CN83xx, CN81xx
+		 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
+		 */
+		.desc	= "GICv3: Cavium erratum 38539",
+		.iidr	= 0xa000034c,
+		.mask	= 0xe8f00fff,
+		.init	= gic_enable_quirk_cavium_38539,
+	},
 	{
 	}
 };
@@ -1577,7 +1600,12 @@ static int __init gic_init_bases(void __iomem *dist_base,
 	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
 	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
 
-	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
+	/*
+	 * ThunderX1 explodes on reading GICD_TYPER2, in violation of the
+	 * architecture spec (which says that reserved registers are RES0).
+	 */
+	if (!(gic_data.flags & FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539))
+		gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base + GICD_TYPER2);
 
 	gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops,
 						 &gic_data);