riscv: move sifive_l2_cache.c to drivers/soc

The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
This commit is contained in:
Christoph Hellwig 2019-11-07 10:20:39 +01:00 committed by Paul Walmsley
parent 01f52e16b8
commit 9209fb5189
8 changed files with 17 additions and 2 deletions

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@ -6027,6 +6027,7 @@ M: Yash Shah <yash.shah@sifive.com>
L: linux-edac@vger.kernel.org L: linux-edac@vger.kernel.org
S: Supported S: Supported
F: drivers/edac/sifive_edac.c F: drivers/edac/sifive_edac.c
F: drivers/soc/sifive_l2_cache.c
EDAC-SKYLAKE EDAC-SKYLAKE
M: Tony Luck <tony.luck@intel.com> M: Tony Luck <tony.luck@intel.com>

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@ -10,7 +10,6 @@ obj-y += extable.o
obj-$(CONFIG_MMU) += fault.o obj-$(CONFIG_MMU) += fault.o
obj-y += cacheflush.o obj-y += cacheflush.o
obj-y += context.o obj-y += context.o
obj-y += sifive_l2_cache.o
ifeq ($(CONFIG_MMU),y) ifeq ($(CONFIG_MMU),y)
obj-$(CONFIG_SMP) += tlbflush.o obj-$(CONFIG_SMP) += tlbflush.o

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@ -462,7 +462,7 @@ config EDAC_ALTERA_SDMMC
config EDAC_SIFIVE config EDAC_SIFIVE
bool "Sifive platform EDAC driver" bool "Sifive platform EDAC driver"
depends on EDAC=y && RISCV depends on EDAC=y && SIFIVE_L2
help help
Support for error detection and correction on the SiFive SoCs. Support for error detection and correction on the SiFive SoCs.

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@ -14,6 +14,7 @@ source "drivers/soc/qcom/Kconfig"
source "drivers/soc/renesas/Kconfig" source "drivers/soc/renesas/Kconfig"
source "drivers/soc/rockchip/Kconfig" source "drivers/soc/rockchip/Kconfig"
source "drivers/soc/samsung/Kconfig" source "drivers/soc/samsung/Kconfig"
source "drivers/soc/sifive/Kconfig"
source "drivers/soc/sunxi/Kconfig" source "drivers/soc/sunxi/Kconfig"
source "drivers/soc/tegra/Kconfig" source "drivers/soc/tegra/Kconfig"
source "drivers/soc/ti/Kconfig" source "drivers/soc/ti/Kconfig"

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@ -20,6 +20,7 @@ obj-y += qcom/
obj-y += renesas/ obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/
obj-$(CONFIG_SOC_SIFIVE) += sifive/
obj-y += sunxi/ obj-y += sunxi/
obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-y += ti/ obj-y += ti/

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@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
if SOC_SIFIVE
config SIFIVE_L2
bool "Sifive L2 Cache controller"
help
Support for the L2 cache controller on SiFive platforms.
endif

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@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_SIFIVE_L2) += sifive_l2_cache.o