x86: cpu_debug add write support for MSRs
Supported write flag for registers. currently write is enabled only for PMC MSR. [root@ht]# cat /sys/kernel/debug/x86/cpu/cpu1/pmc/0x300/value 0x0 [root@ht]# echo 1234 > /sys/kernel/debug/x86/cpu/cpu1/pmc/0x300/value [root@ht]# cat /sys/kernel/debug/x86/cpu/cpu1/pmc/0x300/value 0x4d2 [root@ht]# echo 0x1234 > /sys/kernel/debug/x86/cpu/cpu1/pmc/0x300/value [root@ht]# cat /sys/kernel/debug/x86/cpu/cpu1/pmc/0x300/value 0x1234 Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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02dde8b45c
commit
91219bcbdc
arch/x86
@ -171,6 +171,17 @@ struct cpu_private {
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struct cpu_debug_base {
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struct cpu_debug_base {
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char *name; /* Register name */
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char *name; /* Register name */
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unsigned flag; /* Register flag */
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unsigned flag; /* Register flag */
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unsigned write; /* Register write flag */
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};
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/*
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* Currently it looks similar to cpu_debug_base but once we add more files
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* cpu_file_base will go in different direction
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*/
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struct cpu_file_base {
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char *name; /* Register file name */
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unsigned flag; /* Register file flag */
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unsigned write; /* Register write flag */
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};
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};
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struct cpu_cpuX_base {
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struct cpu_cpuX_base {
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@ -178,11 +189,6 @@ struct cpu_cpuX_base {
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int init; /* Register index file */
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int init; /* Register index file */
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};
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};
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struct cpu_file_base {
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char *name; /* Register file name */
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unsigned flag; /* Register file flag */
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};
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struct cpu_debug_range {
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struct cpu_debug_range {
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unsigned min; /* Register range min */
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unsigned min; /* Register range min */
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unsigned max; /* Register range max */
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unsigned max; /* Register range max */
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@ -11,6 +11,7 @@
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#include <linux/seq_file.h>
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#include <linux/seq_file.h>
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#include <linux/debugfs.h>
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#include <linux/debugfs.h>
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#include <linux/kprobes.h>
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#include <linux/kprobes.h>
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#include <linux/uaccess.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/percpu.h>
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@ -40,41 +41,41 @@ static DEFINE_MUTEX(cpu_debug_lock);
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static struct dentry *cpu_debugfs_dir;
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static struct dentry *cpu_debugfs_dir;
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static struct cpu_debug_base cpu_base[] = {
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static struct cpu_debug_base cpu_base[] = {
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{ "mc", CPU_MC }, /* Machine Check */
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{ "mc", CPU_MC, 0 },
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{ "monitor", CPU_MONITOR }, /* Monitor */
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{ "monitor", CPU_MONITOR, 0 },
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{ "time", CPU_TIME }, /* Time */
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{ "time", CPU_TIME, 0 },
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{ "pmc", CPU_PMC }, /* Performance Monitor */
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{ "pmc", CPU_PMC, 1 },
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{ "platform", CPU_PLATFORM }, /* Platform */
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{ "platform", CPU_PLATFORM, 0 },
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{ "apic", CPU_APIC }, /* APIC */
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{ "apic", CPU_APIC, 0 },
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{ "poweron", CPU_POWERON }, /* Power-on */
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{ "poweron", CPU_POWERON, 0 },
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{ "control", CPU_CONTROL }, /* Control */
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{ "control", CPU_CONTROL, 0 },
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{ "features", CPU_FEATURES }, /* Features control */
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{ "features", CPU_FEATURES, 0 },
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{ "lastbranch", CPU_LBRANCH }, /* Last Branch */
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{ "lastbranch", CPU_LBRANCH, 0 },
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{ "bios", CPU_BIOS }, /* BIOS */
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{ "bios", CPU_BIOS, 0 },
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{ "freq", CPU_FREQ }, /* Frequency */
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{ "freq", CPU_FREQ, 0 },
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{ "mtrr", CPU_MTRR }, /* MTRR */
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{ "mtrr", CPU_MTRR, 0 },
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{ "perf", CPU_PERF }, /* Performance */
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{ "perf", CPU_PERF, 0 },
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{ "cache", CPU_CACHE }, /* Cache */
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{ "cache", CPU_CACHE, 0 },
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{ "sysenter", CPU_SYSENTER }, /* Sysenter */
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{ "sysenter", CPU_SYSENTER, 0 },
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{ "therm", CPU_THERM }, /* Thermal */
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{ "therm", CPU_THERM, 0 },
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{ "misc", CPU_MISC }, /* Miscellaneous */
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{ "misc", CPU_MISC, 0 },
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{ "debug", CPU_DEBUG }, /* Debug */
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{ "debug", CPU_DEBUG, 0 },
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{ "pat", CPU_PAT }, /* PAT */
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{ "pat", CPU_PAT, 0 },
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{ "vmx", CPU_VMX }, /* VMX */
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{ "vmx", CPU_VMX, 0 },
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{ "call", CPU_CALL }, /* System Call */
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{ "call", CPU_CALL, 0 },
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{ "base", CPU_BASE }, /* BASE Address */
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{ "base", CPU_BASE, 0 },
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{ "smm", CPU_SMM }, /* System mgmt mode */
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{ "smm", CPU_SMM, 0 },
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{ "svm", CPU_SVM }, /*Secure Virtial Machine*/
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{ "svm", CPU_SVM, 0 },
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{ "osvm", CPU_OSVM }, /* OS-Visible Workaround*/
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{ "osvm", CPU_OSVM, 0 },
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{ "tss", CPU_TSS }, /* Task Stack Segment */
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{ "tss", CPU_TSS, 0 },
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{ "cr", CPU_CR }, /* Control Registers */
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{ "cr", CPU_CR, 0 },
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{ "dt", CPU_DT }, /* Descriptor Table */
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{ "dt", CPU_DT, 0 },
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{ "registers", CPU_REG_ALL }, /* Select all Registers */
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{ "registers", CPU_REG_ALL, 0 },
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};
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};
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static struct cpu_file_base cpu_file[] = {
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static struct cpu_file_base cpu_file[] = {
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{ "index", CPU_REG_ALL }, /* index */
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{ "index", CPU_REG_ALL, 0 },
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{ "value", CPU_REG_ALL }, /* value */
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{ "value", CPU_REG_ALL, 1 },
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};
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};
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/* Intel Registers Range */
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/* Intel Registers Range */
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@ -608,9 +609,62 @@ static int cpu_seq_open(struct inode *inode, struct file *file)
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return err;
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return err;
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}
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}
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static int write_msr(struct cpu_private *priv, u64 val)
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{
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u32 low, high;
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high = (val >> 32) & 0xffffffff;
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low = val & 0xffffffff;
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if (!wrmsr_safe_on_cpu(priv->cpu, priv->reg, low, high))
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return 0;
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return -EPERM;
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}
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static int write_cpu_register(struct cpu_private *priv, const char *buf)
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{
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int ret = -EPERM;
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u64 val;
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ret = strict_strtoull(buf, 0, &val);
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if (ret < 0)
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return ret;
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/* Supporting only MSRs */
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if (priv->type < CPU_TSS_BIT)
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return write_msr(priv, val);
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return ret;
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}
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static ssize_t cpu_write(struct file *file, const char __user *ubuf,
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size_t count, loff_t *off)
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{
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struct seq_file *seq = file->private_data;
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struct cpu_private *priv = seq->private;
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char buf[19];
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if ((priv == NULL) || (count >= sizeof(buf)))
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return -EINVAL;
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if (copy_from_user(&buf, ubuf, count))
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return -EFAULT;
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buf[count] = 0;
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if ((cpu_base[priv->type].write) && (cpu_file[priv->file].write))
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if (!write_cpu_register(priv, buf))
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return count;
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return -EACCES;
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}
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static const struct file_operations cpu_fops = {
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static const struct file_operations cpu_fops = {
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.owner = THIS_MODULE,
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.open = cpu_seq_open,
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.open = cpu_seq_open,
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.read = seq_read,
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.read = seq_read,
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.write = cpu_write,
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.llseek = seq_lseek,
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.llseek = seq_lseek,
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.release = seq_release,
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.release = seq_release,
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};
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};
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