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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband

Browse Source 
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland/infiniband:
  RDMA: Update missed conversion of flush_scheduled_work()
  RDMA/ucma: Copy iWARP route information on queries
  RDMA/amso1100: Fix compile warnings
  RDMA/cxgb4: Set the correct device physical function for iWARP connections
  RDMA/cxgb4: Limit MAXBURST EQ context field to 256B
  IB/qib: Hold link for TX SERDES settings
  mlx4_core: Add ConnectX-3 device IDs
This commit is contained in:
Linus Torvalds 2011-02-03 11:19:26 -08:00
commit 9118626a30
7 changed files with 53 additions and 28 deletions
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2
drivers/infiniband/core/sa_query.c
View File

@ -1079,7 +1079,7 @@ static void ib_sa_remove_one(struct ib_device *device)
ib_unregister_event_handler(&sa_dev->event_handler); ib_unregister_event_handler(&sa_dev->event_handler);
flush_scheduled_work(); flush_workqueue(ib_wq);
for (i = 0; i <= sa_dev->end_port - sa_dev->start_port; ++i) { for (i = 0; i <= sa_dev->end_port - sa_dev->start_port; ++i) {
if (rdma_port_get_link_layer(device, i + 1) == IB_LINK_LAYER_INFINIBAND) { if (rdma_port_get_link_layer(device, i + 1) == IB_LINK_LAYER_INFINIBAND) {

22
drivers/infiniband/core/ucma.c
View File

@ -636,6 +636,16 @@ static void ucma_copy_iboe_route(struct rdma_ucm_query_route_resp *resp,
} }
} }
static void ucma_copy_iw_route(struct rdma_ucm_query_route_resp *resp,
struct rdma_route *route)
{
struct rdma_dev_addr *dev_addr;
dev_addr = &route->addr.dev_addr;
rdma_addr_get_dgid(dev_addr, (union ib_gid *) &resp->ib_route[0].dgid);
rdma_addr_get_sgid(dev_addr, (union ib_gid *) &resp->ib_route[0].sgid);
}
static ssize_t ucma_query_route(struct ucma_file *file, static ssize_t ucma_query_route(struct ucma_file *file,
const char __user *inbuf, const char __user *inbuf,
int in_len, int out_len) int in_len, int out_len)
@ -670,8 +680,10 @@ static ssize_t ucma_query_route(struct ucma_file *file,
resp.node_guid = (__force __u64) ctx->cm_id->device->node_guid; resp.node_guid = (__force __u64) ctx->cm_id->device->node_guid;
resp.port_num = ctx->cm_id->port_num; resp.port_num = ctx->cm_id->port_num;
if (rdma_node_get_transport(ctx->cm_id->device->node_type) == RDMA_TRANSPORT_IB) { switch (rdma_node_get_transport(ctx->cm_id->device->node_type)) {
switch (rdma_port_get_link_layer(ctx->cm_id->device, ctx->cm_id->port_num)) { case RDMA_TRANSPORT_IB:
switch (rdma_port_get_link_layer(ctx->cm_id->device,
ctx->cm_id->port_num)) {
case IB_LINK_LAYER_INFINIBAND: case IB_LINK_LAYER_INFINIBAND:
ucma_copy_ib_route(&resp, &ctx->cm_id->route); ucma_copy_ib_route(&resp, &ctx->cm_id->route);
break; break;
@ -681,6 +693,12 @@ static ssize_t ucma_query_route(struct ucma_file *file,
default: default:
break; break;
} }
break;
case RDMA_TRANSPORT_IWARP:
ucma_copy_iw_route(&resp, &ctx->cm_id->route);
break;
default:
break;
} }
out: out:

6
drivers/infiniband/hw/amso1100/c2_vq.c
View File

@ -107,7 +107,7 @@ struct c2_vq_req *vq_req_alloc(struct c2_dev *c2dev)
r = kmalloc(sizeof(struct c2_vq_req), GFP_KERNEL); r = kmalloc(sizeof(struct c2_vq_req), GFP_KERNEL);
if (r) { if (r) {
init_waitqueue_head(&r->wait_object); init_waitqueue_head(&r->wait_object);
r->reply_msg = (u64) NULL; r->reply_msg = 0;
r->event = 0; r->event = 0;
r->cm_id = NULL; r->cm_id = NULL;
r->qp = NULL; r->qp = NULL;
@ -123,7 +123,7 @@ struct c2_vq_req *vq_req_alloc(struct c2_dev *c2dev)
*/ */
void vq_req_free(struct c2_dev *c2dev, struct c2_vq_req *r) void vq_req_free(struct c2_dev *c2dev, struct c2_vq_req *r)
{ {
r->reply_msg = (u64) NULL; r->reply_msg = 0;
if (atomic_dec_and_test(&r->refcnt)) { if (atomic_dec_and_test(&r->refcnt)) {
kfree(r); kfree(r);
} }
@ -151,7 +151,7 @@ void vq_req_get(struct c2_dev *c2dev, struct c2_vq_req *r)
void vq_req_put(struct c2_dev *c2dev, struct c2_vq_req *r) void vq_req_put(struct c2_dev *c2dev, struct c2_vq_req *r)
{ {
if (atomic_dec_and_test(&r->refcnt)) { if (atomic_dec_and_test(&r->refcnt)) {
if (r->reply_msg != (u64) NULL) if (r->reply_msg != 0)
vq_repbuf_free(c2dev, vq_repbuf_free(c2dev,
(void *) (unsigned long) r->reply_msg); (void *) (unsigned long) r->reply_msg);
kfree(r); kfree(r);

2
drivers/infiniband/hw/cxgb4/cm.c
View File

@ -380,7 +380,7 @@ static void send_flowc(struct c4iw_ep *ep, struct sk_buff *skb)
16)) | FW_WR_FLOWID(ep->hwtid)); 16)) | FW_WR_FLOWID(ep->hwtid));
flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
flowc->mnemval[0].val = cpu_to_be32(0); flowc->mnemval[0].val = cpu_to_be32(PCI_FUNC(ep->com.dev->rdev.lldi.pdev->devfn) << 8);
flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
flowc->mnemval[1].val = cpu_to_be32(ep->tx_chan); flowc->mnemval[1].val = cpu_to_be32(ep->tx_chan);
flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT; flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;

4
drivers/infiniband/hw/cxgb4/qp.c
View File

@ -220,7 +220,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
V_FW_RI_RES_WR_DCAEN(0) | V_FW_RI_RES_WR_DCAEN(0) |
V_FW_RI_RES_WR_DCACPU(0) | V_FW_RI_RES_WR_DCACPU(0) |
V_FW_RI_RES_WR_FBMIN(2) | V_FW_RI_RES_WR_FBMIN(2) |
V_FW_RI_RES_WR_FBMAX(3) | V_FW_RI_RES_WR_FBMAX(2) |
V_FW_RI_RES_WR_CIDXFTHRESHO(0) | V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
V_FW_RI_RES_WR_CIDXFTHRESH(0) | V_FW_RI_RES_WR_CIDXFTHRESH(0) |
V_FW_RI_RES_WR_EQSIZE(eqsize)); V_FW_RI_RES_WR_EQSIZE(eqsize));
@ -243,7 +243,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
V_FW_RI_RES_WR_DCAEN(0) | V_FW_RI_RES_WR_DCAEN(0) |
V_FW_RI_RES_WR_DCACPU(0) | V_FW_RI_RES_WR_DCACPU(0) |
V_FW_RI_RES_WR_FBMIN(2) | V_FW_RI_RES_WR_FBMIN(2) |
V_FW_RI_RES_WR_FBMAX(3) | V_FW_RI_RES_WR_FBMAX(2) |
V_FW_RI_RES_WR_CIDXFTHRESHO(0) | V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
V_FW_RI_RES_WR_CIDXFTHRESH(0) | V_FW_RI_RES_WR_CIDXFTHRESH(0) |
V_FW_RI_RES_WR_EQSIZE(eqsize)); V_FW_RI_RES_WR_EQSIZE(eqsize));

30
drivers/infiniband/hw/qib/qib_iba7322.c
View File

@ -623,7 +623,6 @@ struct qib_chippport_specific {
u8 ibmalfusesnap; u8 ibmalfusesnap;
struct qib_qsfp_data qsfp_data; struct qib_qsfp_data qsfp_data;
char epmsgbuf[192]; /* for port error interrupt msg buffer */ char epmsgbuf[192]; /* for port error interrupt msg buffer */
u8 bounced;
}; };
static struct { static struct {
@ -1881,23 +1880,7 @@ static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
IB_PHYSPORTSTATE_DISABLED) IB_PHYSPORTSTATE_DISABLED)
qib_set_ib_7322_lstate(ppd, 0, qib_set_ib_7322_lstate(ppd, 0,
QLOGIC_IB_IBCC_LINKINITCMD_DISABLE); QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
else { else
u32 lstate;
/*
* We need the current logical link state before
* lflags are set in handle_e_ibstatuschanged.
*/
lstate = qib_7322_iblink_state(ibcs);
if (IS_QMH(dd) && !ppd->cpspec->bounced &&
ltstate == IB_PHYSPORTSTATE_LINKUP &&
(lstate >= IB_PORT_INIT &&
lstate <= IB_PORT_ACTIVE)) {
ppd->cpspec->bounced = 1;
qib_7322_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE,
IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL);
}
/* /*
* Since going into a recovery state causes the link * Since going into a recovery state causes the link
* state to go down and since recovery is transitory, * state to go down and since recovery is transitory,
@ -1911,7 +1894,6 @@ static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT && ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE) ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
qib_handle_e_ibstatuschanged(ppd, ibcs); qib_handle_e_ibstatuschanged(ppd, ibcs);
}
} }
if (*msg && iserr) if (*msg && iserr)
qib_dev_porterr(dd, ppd->port, "%s error\n", msg); qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
@ -2381,6 +2363,11 @@ static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
/* Hold the link state machine for mezz boards */
if (IS_QMH(dd) || IS_QME(dd))
qib_set_ib_7322_lstate(ppd, 0,
QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
/* Also enable IBSTATUSCHG interrupt. */ /* Also enable IBSTATUSCHG interrupt. */
val = qib_read_kreg_port(ppd, krp_errmask); val = qib_read_kreg_port(ppd, krp_errmask);
qib_write_kreg_port(ppd, krp_errmask, qib_write_kreg_port(ppd, krp_errmask,
@ -5702,6 +5689,11 @@ static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
ppd->cpspec->h1_val = h1; ppd->cpspec->h1_val = h1;
/* now change the IBC and serdes, overriding generic */ /* now change the IBC and serdes, overriding generic */
init_txdds_table(ppd, 1); init_txdds_table(ppd, 1);
/* Re-enable the physical state machine on mezz boards
* now that the correct settings have been set. */
if (IS_QMH(dd) || IS_QME(dd))
qib_set_ib_7322_lstate(ppd, 0,
QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
any++; any++;
} }
if (*nxt == '\n') if (*nxt == '\n')

15
drivers/net/mlx4/main.c
View File

@ -1286,6 +1286,21 @@ static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
{ PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/ { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
{ PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
{ PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */ { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
{ PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
{ PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
{ PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
{ PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
{ PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
{ PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
{ PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
{ PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
{ PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
{ PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
{ PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
{ PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
{ PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
{ PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
{ PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
{ 0, } { 0, }
}; };