forked from Minki/linux
ARM: mxs: get reset address from device tree
Instead of using static address definition, get reset address from device tree with mapping, so that core_initcall mxs_arch_reset_init() can be killed. The "rtc" clock code in mxs_arch_reset_init() seems to be zombie, since there is no clk lookup defined in clock driver at all. Remove it together. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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c226221359
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8f7cf8815f
@ -361,7 +361,7 @@
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ranges;
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clks: clkctrl@80040000 {
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compatible = "fsl,imx23-clkctrl";
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compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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};
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@ -756,7 +756,7 @@
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ranges;
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clks: clkctrl@80040000 {
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compatible = "fsl,imx28-clkctrl";
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compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
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reg = <0x80040000 0x2000>;
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#clock-cells = <1>;
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};
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@ -23,6 +23,8 @@
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/proc-fns.h>
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#include <asm/system_misc.h>
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@ -37,41 +39,37 @@
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#define MXS_MODULE_CLKGATE (1 << 30)
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#define MXS_MODULE_SFTRST (1 << 31)
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static void __iomem *mxs_clkctrl_reset_addr;
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/*
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* Reset the system. It is called by machine_restart().
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*/
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void mxs_restart(char mode, const char *cmd)
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{
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struct device_node *np;
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void __iomem *reset_addr;
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np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
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reset_addr = of_iomap(np, 0);
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if (!reset_addr)
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goto soft;
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if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
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reset_addr += MX23_CLKCTRL_RESET_OFFSET;
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else
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reset_addr += MX28_CLKCTRL_RESET_OFFSET;
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/* reset the chip */
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__mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
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__mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
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pr_err("Failed to assert the chip reset\n");
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/* Delay to allow the serial port to show the message */
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mdelay(50);
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soft:
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/* We'll take a jump through zero as a poor second */
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soft_restart(0);
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}
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static int __init mxs_arch_reset_init(void)
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{
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struct clk *clk;
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mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
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(cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
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MX28_CLKCTRL_RESET_OFFSET);
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clk = clk_get_sys("rtc", NULL);
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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return 0;
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}
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core_initcall(mxs_arch_reset_init);
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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