tile PCI RC: use proper accessor function
Using the low-level hv_dev_pread() API makes assumptions about the layout of datastructures in the Tilera hypervisor API; it's better to use the gxio_XXX accessor and the pcie_trio_ports_property struct. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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@@ -91,7 +91,7 @@ static int rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
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TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1
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/* Array of the PCIe ports configuration info obtained from the BIB. */
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/* Array of the PCIe ports configuration info obtained from the BIB. */
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struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
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struct pcie_trio_ports_property pcie_ports[TILEGX_NUM_TRIO];
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/* Number of configured TRIO instances. */
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/* Number of configured TRIO instances. */
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int num_trio_shims;
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int num_trio_shims;
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@@ -195,10 +195,7 @@ static int tile_pcie_open(int trio_index)
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#endif
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#endif
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/* Get the properties of the PCIe ports on this TRIO instance. */
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/* Get the properties of the PCIe ports on this TRIO instance. */
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ret = hv_dev_pread(context->fd, 0,
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ret = gxio_trio_get_port_property(context, &pcie_ports[trio_index]);
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(HV_VirtAddr)&pcie_ports[trio_index][0],
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sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES,
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GXIO_TRIO_OP_GET_PORT_PROPERTY);
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if (ret < 0) {
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if (ret < 0) {
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pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
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pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
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" on TRIO %d\n", ret, trio_index);
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" on TRIO %d\n", ret, trio_index);
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@@ -221,8 +218,8 @@ static int tile_pcie_open(int trio_index)
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unsigned int reg_offset;
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unsigned int reg_offset;
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/* Ignore ports that are not specified in the BIB. */
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/* Ignore ports that are not specified in the BIB. */
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if (!pcie_ports[trio_index][mac].allow_rc &&
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if (!pcie_ports[trio_index].ports[mac].allow_rc &&
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!pcie_ports[trio_index][mac].allow_ep)
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!pcie_ports[trio_index].ports[mac].allow_ep)
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continue;
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continue;
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reg_offset =
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reg_offset =
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@@ -243,7 +240,7 @@ static int tile_pcie_open(int trio_index)
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*/
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*/
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if (port_config.strap_state == AUTO_CONFIG_EP ||
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if (port_config.strap_state == AUTO_CONFIG_EP ||
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port_config.strap_state == AUTO_CONFIG_EP_G1)
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port_config.strap_state == AUTO_CONFIG_EP_G1)
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pcie_ports[trio_index][mac].allow_ep = 1;
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pcie_ports[trio_index].ports[mac].allow_ep = 1;
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}
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}
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}
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}
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@@ -438,9 +435,10 @@ int __init tile_pci_init(void)
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return 0;
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return 0;
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/*
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/*
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* Now determine which PCIe ports are configured to operate in RC mode.
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* Now determine which PCIe ports are configured to operate in RC
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* We look at the Board Information Block first and then see if there
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* mode. To use a port, it must be allowed to be in RC mode by the
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* are any overriding configuration by the HW strapping pin.
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* Board Information Block, and the hardware strapping pins must be
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* set to RC mode.
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*/
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*/
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for (i = 0; i < TILEGX_NUM_TRIO; i++) {
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for (i = 0; i < TILEGX_NUM_TRIO; i++) {
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gxio_trio_context_t *context = &trio_contexts[i];
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gxio_trio_context_t *context = &trio_contexts[i];
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@@ -449,7 +447,7 @@ int __init tile_pci_init(void)
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continue;
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continue;
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for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
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for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
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if (pcie_ports[i][j].allow_rc &&
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if (pcie_ports[i].ports[j].allow_rc &&
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strapped_for_rc(context, j)) {
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strapped_for_rc(context, j)) {
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pcie_rc[i][j] = 1;
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pcie_rc[i][j] = 1;
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num_rc_controllers++;
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num_rc_controllers++;
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@@ -736,7 +734,7 @@ int __init pcibios_init(void)
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__gxio_mmio_read(trio_context->mmio_base_mac +
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__gxio_mmio_read(trio_context->mmio_base_mac +
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reg_offset);
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reg_offset);
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if (!port_status.dl_up) {
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if (!port_status.dl_up) {
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if (pcie_ports[trio_index][mac].removable) {
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if (pcie_ports[trio_index].ports[mac].removable) {
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pr_info("PCI: link is down, MAC %d on TRIO %d\n",
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pr_info("PCI: link is down, MAC %d on TRIO %d\n",
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mac, trio_index);
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mac, trio_index);
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pr_info("This is expected if no PCIe card"
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pr_info("This is expected if no PCIe card"
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