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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

Browse Source 
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1745 commits)
  dp83640: free packet queues on remove
  dp83640: use proper function to free transmit time stamping packets
  ipv6: Do not use routes from locally generated RAs
  |PATCH net-next] tg3: add tx_dropped counter
  be2net: don't create multiple RX/TX rings in multi channel mode
  be2net: don't create multiple TXQs in BE2
  be2net: refactor VF setup/teardown code into be_vf_setup/clear()
  be2net: add vlan/rx-mode/flow-control config to be_setup()
  net_sched: cls_flow: use skb_header_pointer()
  ipv4: avoid useless call of the function check_peer_pmtu
  TCP: remove TCP_DEBUG
  net: Fix driver name for mdio-gpio.c
  ipv4: tcp: fix TOS value in ACK messages sent from TIME_WAIT
  rtnetlink: Add missing manual netlink notification in dev_change_net_namespaces
  ipv4: fix ipsec forward performance regression
  jme: fix irq storm after suspend/resume
  route: fix ICMP redirect validation
  net: hold sock reference while processing tx timestamps
  tcp: md5: add more const attributes
  Add ethtool -g support to virtio_net
  ...

Fix up conflicts in:
 - drivers/net/Kconfig:
	The split-up generated a trivial conflict with removal of a
	stale reference to Documentation/networking/net-modules.txt.
	Remove it from the new location instead.
 - fs/sysfs/dir.c:
	Fairly nasty conflicts with the sysfs rb-tree usage, conflicting
	with Eric Biederman's changes for tagged directories.
This commit is contained in:
Linus Torvalds 2011-10-25 13:25:22 +02:00
commit 8a9ea3237e
2493 changed files with 827847 additions and 731950 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/ABI/testing/sysfs-class-net-mesh
View File

@ -22,6 +22,14 @@ Description:
mesh will be fragmented or silently discarded if the
packet size exceeds the outgoing interface MTU.
What: /sys/class/net/<mesh_iface>/mesh/ap_isolation
Date: May 2011
Contact: Antonio Quartulli <ordex@autistici.org>
Description:
Indicates whether the data traffic going from a
wireless client to another wireless client will be
silently dropped.
What: /sys/class/net/<mesh_iface>/mesh/gw_bandwidth
Date: October 2010
Contact: Marek Lindner <lindner_marek@yahoo.de>

11
Documentation/DocBook/80211.tmpl
View File

@ -433,8 +433,18 @@
Insert notes about VLAN interfaces with hw crypto here or
in the hw crypto chapter.
</para>
<section id="ps-client">
<title>support for powersaving clients</title>
!Pinclude/net/mac80211.h AP support for powersaving clients
</section>
!Finclude/net/mac80211.h ieee80211_get_buffered_bc
!Finclude/net/mac80211.h ieee80211_beacon_get
!Finclude/net/mac80211.h ieee80211_sta_eosp_irqsafe
!Finclude/net/mac80211.h ieee80211_frame_release_type
!Finclude/net/mac80211.h ieee80211_sta_ps_transition
!Finclude/net/mac80211.h ieee80211_sta_ps_transition_ni
!Finclude/net/mac80211.h ieee80211_sta_set_buffered
!Finclude/net/mac80211.h ieee80211_sta_block_awake
</chapter>
<chapter id="multi-iface">
@ -460,7 +470,6 @@
!Finclude/net/mac80211.h sta_notify_cmd
!Finclude/net/mac80211.h ieee80211_find_sta
!Finclude/net/mac80211.h ieee80211_find_sta_by_ifaddr
!Finclude/net/mac80211.h ieee80211_sta_block_awake
</chapter>
<chapter id="hardware-scan-offload">

63
Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
View File

@ -1,61 +1,24 @@
CAN Device Tree Bindings
------------------------
2011 Freescale Semiconductor, Inc.
Flexcan CAN contoller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
fsl,flexcan-v1.0 nodes
-----------------------
In addition to the required compatible-, reg- and interrupt-properties, you can
also specify which clock source shall be used for the controller.
Required properties:
CPI Clock- Can Protocol Interface Clock
This CLK_SRC bit of CTRL(control register) selects the clock source to
the CAN Protocol Interface(CPI) to be either the peripheral clock
(driven by the PLL) or the crystal oscillator clock. The selected clock
is the one fed to the prescaler to generate the Serial Clock (Sclock).
The PRESDIV field of CTRL(control register) controls a prescaler that
generates the Serial Clock (Sclock), whose period defines the
time quantum used to compose the CAN waveform.
- compatible : Should be "fsl,<processor>-flexcan"
Can Engine Clock Source
There are two sources for CAN clock
- Platform Clock It represents the bus clock
- Oscillator Clock
An implementation should also claim any of the following compatibles
that it is fully backwards compatible with:
Peripheral Clock (PLL)
--------------
|
--------- -------------
| |CPI Clock | Prescaler | Sclock
| |---------------->| (1.. 256) |------------>
--------- -------------
| |
-------------- ---------------------CLK_SRC
Oscillator Clock
- fsl,p1010-flexcan
- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
the peripheral clock. PLL clock is fed to the
prescaler to generate the Serial Clock (Sclock).
Valid values are "oscillator" and "platform"
"oscillator": CAN engine clock source is oscillator clock.
"platform" The CAN engine clock source is the bus clock
(platform clock).
- reg : Offset and length of the register set for this device
- interrupts : Interrupt tuple for this device
- clock-frequency : The oscillator frequency driving the flexcan device
- fsl,flexcan-clock-divider : for the reference and system clock, an additional
clock divider can be specified.
- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
Example:
Note:
- v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
- P1010 does not have oscillator as the Clock Source.So the default
Clock Source is platform clock.
Examples:
can0@1c000 {
compatible = "fsl,flexcan-v1.0";
can@1c000 {
compatible = "fsl,p1010-flexcan";
reg = <0x1c000 0x1000>;
interrupts = <48 0x2>;
interrupt-parent = <&mpic>;
fsl,flexcan-clock-source = "platform";
fsl,flexcan-clock-divider = <2>;
clock-frequency = <fixed by u-boot>;
clock-frequency = <200000000>; // filled in by bootloader
};

38
Documentation/devicetree/bindings/net/smsc911x.txt Normal file
View File

@ -0,0 +1,38 @@
* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
Required properties:
- compatible : Should be "smsc,lan<model>", "smsc,lan9115"
- reg : Address and length of the io space for SMSC LAN
- interrupts : Should contain SMSC LAN interrupt line
- interrupt-parent : Should be the phandle for the interrupt controller
that services interrupts for this device
- phy-mode : String, operation mode of the PHY interface.
Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
"rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
Optional properties:
- reg-shift : Specify the quantity to shift the register offsets by
- reg-io-width : Specify the size (in bytes) of the IO accesses that
should be performed on the device. Valid value for SMSC LAN is
2 or 4. If it's omitted or invalid, the size would be 2.
- smsc,irq-active-high : Indicates the IRQ polarity is active-high
- smsc,irq-push-pull : Indicates the IRQ type is push-pull
- smsc,force-internal-phy : Forces SMSC LAN controller to use
internal PHY
- smsc,force-external-phy : Forces SMSC LAN controller to use
external PHY
- smsc,save-mac-address : Indicates that mac address needs to be saved
before resetting the controller
- local-mac-address : 6 bytes, mac address
Examples:
lan9220@f4000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0xf4000000 0x2000000>;
phy-mode = "mii";
interrupt-parent = <&gpio1>;
interrupts = <31>;
reg-io-width = <4>;
smsc,irq-push-pull;
};

9
Documentation/feature-removal-schedule.txt
View File

@ -594,9 +594,18 @@ Why: In 3.0, we can now autodetect internal 3G device and already have
Who: Lee, Chun-Yi <jlee@novell.com>
----------------------------
What: The XFS nodelaylog mount option
When: 3.3
Why: The delaylog mode that has been the default since 2.6.39 has proven
stable, and the old code is in the way of additional improvements in
the log code.
Who: Christoph Hellwig <hch@lst.de>
----------------------------
What: iwlagn alias support
When: 3.5
Why: The iwlagn module has been renamed iwlwifi. The alias will be around
for backward compatibility for several cycles and then dropped.
Who: Don Fry <donald.h.fry@intel.com>

8
Documentation/networking/batman-adv.txt
View File

@ -1,4 +1,4 @@
[state: 17-04-2011]
[state: 21-08-2011]
BATMAN-ADV
----------
@ -68,9 +68,9 @@ All mesh wide settings can be found in batman's own interface
folder:
# ls /sys/class/net/bat0/mesh/
# aggregated_ogms gw_bandwidth hop_penalty
# bonding gw_mode orig_interval
# fragmentation gw_sel_class vis_mode
# aggregated_ogms fragmentation gw_sel_class vis_mode
# ap_isolation gw_bandwidth hop_penalty
# bonding gw_mode orig_interval
There is a special folder for debugging information:

17
Documentation/networking/ip-sysctl.txt
View File

@ -1045,6 +1045,11 @@ conf/interface/*:
accept_ra - INTEGER
Accept Router Advertisements; autoconfigure using them.
It also determines whether or not to transmit Router
Solicitations. If and only if the functional setting is to
accept Router Advertisements, Router Solicitations will be
transmitted.
Possible values are:
0 Do not accept Router Advertisements.
1 Accept Router Advertisements if forwarding is disabled.
@ -1115,14 +1120,14 @@ forwarding - INTEGER
Possible values are:
0 Forwarding disabled
1 Forwarding enabled
2 Forwarding enabled (Hybrid Mode)
FALSE (0):
By default, Host behaviour is assumed. This means:
1. IsRouter flag is not set in Neighbour Advertisements.
2. Router Solicitations are being sent when necessary.
2. If accept_ra is TRUE (default), transmit Router
Solicitations.
3. If accept_ra is TRUE (default), accept Router
Advertisements (and do autoconfiguration).
4. If accept_redirects is TRUE (default), accept Redirects.
@ -1133,16 +1138,10 @@ forwarding - INTEGER
This means exactly the reverse from the above:
1. IsRouter flag is set in Neighbour Advertisements.
2. Router Solicitations are not sent.
2. Router Solicitations are not sent unless accept_ra is 2.
3. Router Advertisements are ignored unless accept_ra is 2.
4. Redirects are ignored.
TRUE (2):
Hybrid mode. Same behaviour as TRUE, except for:
2. Router Solicitations are being sent when necessary.
Default: 0 (disabled) if global forwarding is disabled (default),
otherwise 1 (enabled).

4
Documentation/networking/mac80211-injection.txt
View File

@ -23,6 +23,10 @@ radiotap headers and used to control injection:
IEEE80211_RADIOTAP_F_FRAG: frame will be fragmented if longer than the
current fragmentation threshold.
* IEEE80211_RADIOTAP_TX_FLAGS
IEEE80211_RADIOTAP_F_TX_NOACK: frame should be sent without waiting for
an ACK even if it is a unicast frame
The injection code can also skip all other currently defined radiotap fields
facilitating replay of captured radiotap headers directly.

4
Documentation/networking/netdevices.txt
View File

@ -73,7 +73,7 @@ dev->hard_start_xmit:
has to lock by itself when needed. It is recommended to use a try lock
for this and return NETDEV_TX_LOCKED when the spin lock fails.
The locking there should also properly protect against
set_multicast_list. Note that the use of NETIF_F_LLTX is deprecated.
set_rx_mode. Note that the use of NETIF_F_LLTX is deprecated.
Don't use it for new drivers.
Context: Process with BHs disabled or BH (timer),
@ -92,7 +92,7 @@ dev->tx_timeout:
Context: BHs disabled
Notes: netif_queue_stopped() is guaranteed true
dev->set_multicast_list:
dev->set_rx_mode:
Synchronization: netif_tx_lock spinlock.
Context: BHs disabled

44
Documentation/networking/stmmac.txt
View File

@ -76,7 +76,16 @@ core.
4.5) DMA descriptors
Driver handles both normal and enhanced descriptors. The latter has been only
tested on DWC Ether MAC 10/100/1000 Universal version 3.41a.
tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later.
STMMAC supports DMA descriptor to operate both in dual buffer (RING)
and linked-list(CHAINED) mode. In RING each descriptor points to two
data buffer pointers whereas in CHAINED mode they point to only one data
buffer pointer. RING mode is the default.
In CHAINED mode each descriptor will have pointer to next descriptor in
the list, hence creating the explicit chaining in the descriptor itself,
whereas such explicit chaining is not possible in RING mode.
4.6) Ethtool support
Ethtool is supported. Driver statistics and internal errors can be taken using:
@ -235,7 +244,38 @@ reset procedure etc).
o enh_desc.c: functions for handling enhanced descriptors
o norm_desc.c: functions for handling normal descriptors
5) TODO:
5) Debug Information
The driver exports many information i.e. internal statistics,
debug information, MAC and DMA registers etc.
These can be read in several ways depending on the
type of the information actually needed.
For example a user can be use the ethtool support
to get statistics: e.g. using: ethtool -S ethX
(that shows the Management counters (MMC) if supported)
or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
Compiling the Kernel with CONFIG_DEBUG_FS and enabling the
STMMAC_DEBUG_FS option the driver will export the following
debugfs entries:
/sys/kernel/debug/stmmaceth/descriptors_status
To show the DMA TX/RX descriptor rings
Developer can also use the "debug" module parameter to get
further debug information.
In the end, there are other macros (that cannot be enabled
via menuconfig) to turn-on the RX/TX DMA debugging,
specific MAC core debug printk etc. Others to enable the
debug in the TX and RX processes.
All these are only useful during the developing stage
and should never enabled inside the code for general usage.
In fact, these can generate an huge amount of debug messages.
6) TODO:
o XGMAC is not supported.
o Review the timer optimisation code to use an embedded device that will be
available in new chip generations.

218
MAINTAINERS
View File

@ -117,20 +117,20 @@ Maintainers List (try to look for most precise areas first)
M: Philip Blundell <philb@gnu.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/3c505*
F: drivers/net/ethernet/i825xx/3c505*
3C59X NETWORK DRIVER
M: Steffen Klassert <klassert@mathematik.tu-chemnitz.de>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/networking/vortex.txt
F: drivers/net/3c59x.c
F: drivers/net/ethernet/3com/3c59x.c
3CR990 NETWORK DRIVER
M: David Dillow <dave@thedillows.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/typhoon*
F: drivers/net/ethernet/3com/typhoon*
3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
M: Adam Radford <linuxraid@lsi.com>
@ -156,7 +156,7 @@ M: Realtek linux nic maintainers <nic_swsd@realtek.com>
M: Francois Romieu <romieu@fr.zoreil.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/r8169.c
F: drivers/net/ethernet/realtek/r8169.c
8250/16?50 (AND CLONE UARTS) SERIAL DRIVER
M: Greg Kroah-Hartman <gregkh@suse.de>
@ -170,8 +170,7 @@ F: include/linux/serial_8250.h
8390 NETWORK DRIVERS [WD80x3/SMC-ELITE, SMC-ULTRA, NE2000, 3C503, etc.]
L: netdev@vger.kernel.org
S: Orphan / Obsolete
F: drivers/net/*8390*
F: drivers/net/ax88796.c
F: drivers/net/ethernet/8390/
9P FILE SYSTEM
M: Eric Van Hensbergen <ericvh@gmail.com>
@ -214,7 +213,7 @@ ACENIC DRIVER
M: Jes Sorensen <jes@trained-monkey.org>
L: linux-acenic@sunsite.dk
S: Maintained
F: drivers/net/acenic*
F: drivers/net/ethernet/alteon/acenic*
ACER ASPIRE ONE TEMPERATURE AND FAN DRIVER
M: Peter Feuerer <peter@piie.net>
@ -746,7 +745,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://www.arm.linux.org.uk/
S: Maintained
F: arch/arm/mach-ebsa110/
F: drivers/net/arm/am79c961a.*
F: drivers/net/ethernet/amd/am79c961a.*
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
M: Daniel Ribeiro <drwyrm@gmail.com>
@ -1015,7 +1014,8 @@ F: arch/arm/include/asm/hardware/ioc.h
F: arch/arm/include/asm/hardware/iomd.h
F: arch/arm/include/asm/hardware/memc.h
F: arch/arm/mach-rpc/
F: drivers/net/arm/ether*
F: drivers/net/ethernet/i825xx/ether1*
F: drivers/net/ethernet/seeq/ether3*
F: drivers/scsi/arm/
ARM/SHARK MACHINE SUPPORT
@ -1127,7 +1127,7 @@ F: arch/arm/mach-nuc93x/
F: drivers/input/keyboard/w90p910_keypad.c
F: drivers/input/touchscreen/w90p910_ts.c
F: drivers/watchdog/nuc900_wdt.c
F: drivers/net/arm/w90p910_ether.c
F: drivers/net/ethernet/nuvoton/w90p910_ether.c
F: drivers/mtd/nand/nuc900_nand.c
F: drivers/rtc/rtc-nuc900.c
F: drivers/spi/spi_nuc900.c
@ -1230,7 +1230,7 @@ F: Documentation/aoe/
F: drivers/block/aoe/
ATHEROS ATH GENERIC UTILITIES
M: "Luis R. Rodriguez" <lrodriguez@atheros.com>
M: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com>
L: linux-wireless@vger.kernel.org
S: Supported
F: drivers/net/wireless/ath/*
@ -1238,7 +1238,7 @@ F: drivers/net/wireless/ath/*
ATHEROS ATH5K WIRELESS DRIVER
M: Jiri Slaby <jirislaby@gmail.com>
M: Nick Kossifidis <mickflemm@gmail.com>
M: "Luis R. Rodriguez" <lrodriguez@atheros.com>
M: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com>
M: Bob Copeland <me@bobcopeland.com>
L: linux-wireless@vger.kernel.org
L: ath5k-devel@lists.ath5k.org
@ -1246,11 +1246,19 @@ W: http://wireless.kernel.org/en/users/Drivers/ath5k
S: Maintained
F: drivers/net/wireless/ath/ath5k/
ATHEROS ATH6KL WIRELESS DRIVER
M: Kalle Valo <kvalo@qca.qualcomm.com>
L: linux-wireless@vger.kernel.org
W: http://wireless.kernel.org/en/users/Drivers/ath6kl
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath6kl.git
S: Supported
F: drivers/net/wireless/ath/ath6kl/
ATHEROS ATH9K WIRELESS DRIVER
M: "Luis R. Rodriguez" <lrodriguez@atheros.com>
M: Jouni Malinen <jmalinen@atheros.com>
M: Vasanthakumar Thiagarajan <vasanth@atheros.com>
M: Senthil Balasubramanian <senthilkumar@atheros.com>
M: "Luis R. Rodriguez" <mcgrof@qca.qualcomm.com>
M: Jouni Malinen <jouni@qca.qualcomm.com>
M: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com>
M: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
L: linux-wireless@vger.kernel.org
L: ath9k-devel@lists.ath9k.org
W: http://wireless.kernel.org/en/users/Drivers/ath9k
@ -1282,7 +1290,7 @@ L: netdev@vger.kernel.org
W: http://sourceforge.net/projects/atl1
W: http://atl1.sourceforge.net
S: Maintained
F: drivers/net/atlx/
F: drivers/net/ethernet/atheros/
ATM
M: Chas Williams <chas@cmf.nrl.navy.mil>
@ -1322,7 +1330,7 @@ F: include/video/atmel_lcdc.h
ATMEL MACB ETHERNET DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
S: Supported
F: drivers/net/macb.*
F: drivers/net/ethernet/cadence/
ATMEL SPI DRIVER
M: Nicolas Ferre <nicolas.ferre@atmel.com>
@ -1445,7 +1453,7 @@ BLACKFIN EMAC DRIVER
L: uclinux-dist-devel@blackfin.uclinux.org
W: http://blackfin.uclinux.org
S: Supported
F: drivers/net/bfin_mac.*
F: drivers/net/ethernet/adi/
BLACKFIN RTC DRIVER
M: Mike Frysinger <vapier.adi@gmail.com>
@ -1526,27 +1534,27 @@ BROADCOM B44 10/100 ETHERNET DRIVER
M: Gary Zambrano <zambrano@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/b44.*
F: drivers/net/ethernet/broadcom/b44.*
BROADCOM BNX2 GIGABIT ETHERNET DRIVER
M: Michael Chan <mchan@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/bnx2.*
F: drivers/net/bnx2_*
F: drivers/net/ethernet/broadcom/bnx2.*
F: drivers/net/ethernet/broadcom/bnx2_*
BROADCOM BNX2X 10 GIGABIT ETHERNET DRIVER
M: Eilon Greenstein <eilong@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/bnx2x/
F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM TG3 GIGABIT ETHERNET DRIVER
M: Matt Carlson <mcarlson@broadcom.com>
M: Michael Chan <mchan@broadcom.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/tg3.*
F: drivers/net/ethernet/broadcom/tg3.*
BROADCOM BRCM80211 IEEE802.11n WIRELESS DRIVER
M: Brett Rudley <brudley@broadcom.com>
@ -1575,7 +1583,7 @@ BROCADE BNA 10 GIGABIT ETHERNET DRIVER
M: Rasesh Mody <rmody@brocade.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/bna/
F: drivers/net/ethernet/brocade/bna/
BSG (block layer generic sg v4 driver)
M: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
@ -1663,7 +1671,7 @@ CAN NETWORK LAYER
M: Oliver Hartkopp <socketcan@hartkopp.net>
M: Oliver Hartkopp <oliver.hartkopp@volkswagen.de>
M: Urs Thuermann <urs.thuermann@volkswagen.de>
L: socketcan-core@lists.berlios.de (subscribers-only)
L: linux-can@vger.kernel.org
L: netdev@vger.kernel.org
W: http://developer.berlios.de/projects/socketcan/
S: Maintained
@ -1675,7 +1683,7 @@ F: include/linux/can/raw.h
CAN NETWORK DRIVERS
M: Wolfgang Grandegger <wg@grandegger.com>
L: socketcan-core@lists.berlios.de (subscribers-only)
L: linux-can@vger.kernel.org
L: netdev@vger.kernel.org
W: http://developer.berlios.de/projects/socketcan/
S: Maintained
@ -1759,13 +1767,13 @@ M: Christian Benvenuti <benve@cisco.com>
M: Roopa Prabhu <roprabhu@cisco.com>
M: David Wang <dwang2@cisco.com>
S: Supported
F: drivers/net/enic/
F: drivers/net/ethernet/cisco/enic/
CIRRUS LOGIC EP93XX ETHERNET DRIVER
M: Hartley Sweeten <hsweeten@visionengravers.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/arm/ep93xx_eth.c
F: drivers/net/ethernet/cirrus/ep93xx_eth.c
CIRRUS LOGIC EP93XX OHCI USB HOST DRIVER
M: Lennert Buytenhek <kernel@wantstofly.org>
@ -1905,7 +1913,7 @@ CPMAC ETHERNET DRIVER
M: Florian Fainelli <florian@openwrt.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/cpmac.c
F: drivers/net/ethernet/ti/cpmac.c
CPU FREQUENCY DRIVERS
M: Dave Jones <davej@redhat.com>
@ -1992,7 +2000,7 @@ M: Divy Le Ray <divy@chelsio.com>
L: netdev@vger.kernel.org
W: http://www.chelsio.com
S: Supported
F: drivers/net/cxgb3/
F: drivers/net/ethernet/chelsio/cxgb3/
CXGB3 IWARP RNIC DRIVER (IW_CXGB3)
M: Steve Wise <swise@chelsio.com>
@ -2006,7 +2014,7 @@ M: Dimitris Michailidis <dm@chelsio.com>
L: netdev@vger.kernel.org
W: http://www.chelsio.com
S: Supported
F: drivers/net/cxgb4/
F: drivers/net/ethernet/chelsio/cxgb4/
CXGB4 IWARP RNIC DRIVER (IW_CXGB4)
M: Steve Wise <swise@chelsio.com>
@ -2020,14 +2028,14 @@ M: Casey Leedom <leedom@chelsio.com>
L: netdev@vger.kernel.org
W: http://www.chelsio.com
S: Supported
F: drivers/net/cxgb4vf/
F: drivers/net/ethernet/chelsio/cxgb4vf/
STMMAC ETHERNET DRIVER
M: Giuseppe Cavallaro <peppe.cavallaro@st.com>
L: netdev@vger.kernel.org
W: http://www.stlinux.com
S: Supported
F: drivers/net/stmmac/
F: drivers/net/ethernet/stmicro/stmmac/
CYBERPRO FB DRIVER
M: Russell King <linux@arm.linux.org.uk>
@ -2071,7 +2079,7 @@ DAVICOM FAST ETHERNET (DMFE) NETWORK DRIVER
L: netdev@vger.kernel.org
S: Orphan
F: Documentation/networking/dmfe.txt
F: drivers/net/tulip/dmfe.c
F: drivers/net/ethernet/tulip/dmfe.c
DC390/AM53C974 SCSI driver
M: Kurt Garloff <garloff@suse.de>
@ -2110,7 +2118,7 @@ F: net/decnet/
DEFXX FDDI NETWORK DRIVER
M: "Maciej W. Rozycki" <macro@linux-mips.org>
S: Maintained
F: drivers/net/defxx.*
F: drivers/net/fddi/defxx.*
DELL LAPTOP DRIVER
M: Matthew Garrett <mjg59@srcf.ucam.org>
@ -2477,7 +2485,7 @@ EHEA (IBM pSeries eHEA 10Gb ethernet adapter) DRIVER
M: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ehea/
F: drivers/net/ethernet/ibm/ehea/
EMBEDDED LINUX
M: Paul Gortmaker <paul.gortmaker@windriver.com>
@ -2522,7 +2530,7 @@ ETHEREXPRESS-16 NETWORK DRIVER
M: Philip Blundell <philb@gnu.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/eexpress.*
F: drivers/net/ethernet/i825xx/eexpress.*
ETHERNET BRIDGE
M: Stephen Hemminger <shemminger@linux-foundation.org>
@ -2536,7 +2544,7 @@ F: net/bridge/
ETHERTEAM 16I DRIVER
M: Mika Kuoppala <miku@iki.fi>
S: Maintained
F: drivers/net/eth16i.c
F: drivers/net/ethernet/fujitsu/eth16i.c
EXT2 FILE SYSTEM
M: Jan Kara <jack@suse.cz>
@ -2705,7 +2713,7 @@ M: Vitaly Bordug <vbordug@ru.mvista.com>
L: linuxppc-dev@lists.ozlabs.org
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/fs_enet/
F: drivers/net/ethernet/freescale/fs_enet/
F: include/linux/fs_enet_pd.h
FREESCALE QUICC ENGINE LIBRARY
@ -2727,7 +2735,7 @@ M: Li Yang <leoli@freescale.com>
L: netdev@vger.kernel.org
L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: drivers/net/ucc_geth*
F: drivers/net/ethernet/freescale/ucc_geth*
FREESCALE QUICC ENGINE UCC UART DRIVER
M: Timur Tabi <timur@freescale.com>
@ -3065,6 +3073,7 @@ S: Maintained
F: include/linux/hippidevice.h
F: include/linux/if_hippi.h
F: net/802/hippi.c
F: drivers/net/hippi/
HOST AP DRIVER
M: Jouni Malinen <j@w1.fi>
@ -3082,7 +3091,7 @@ F: drivers/platform/x86/tc1100-wmi.c
HP100: Driver for HP 10/100 Mbit/s Voice Grade Network Adapter Series
M: Jaroslav Kysela <perex@perex.cz>
S: Maintained
F: drivers/net/hp100.*
F: drivers/net/ethernet/hp/hp100.*
HPET: High Precision Event Timers driver
M: Clemens Ladisch <clemens@ladisch.de>
@ -3180,7 +3189,7 @@ IBM Power Virtual Ethernet Device Driver
M: Santiago Leon <santil@linux.vnet.ibm.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/ibmveth.*
F: drivers/net/ethernet/ibm/ibmveth.*
IBM ServeRAID RAID DRIVER
P: Jack Hammer
@ -3347,7 +3356,7 @@ F: arch/arm/mach-ixp4xx/include/mach/qmgr.h
F: arch/arm/mach-ixp4xx/include/mach/npe.h
F: arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
F: arch/arm/mach-ixp4xx/ixp4xx_npe.c
F: drivers/net/arm/ixp4xx_eth.c
F: drivers/net/ethernet/xscale/ixp4xx_eth.c
F: drivers/net/wan/ixp4xx_hss.c
INTEL IXP4XX RANDOM NUMBER GENERATOR SUPPORT
@ -3359,7 +3368,7 @@ INTEL IXP2000 ETHERNET DRIVER
M: Lennert Buytenhek <kernel@wantstofly.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ixp2000/
F: drivers/net/ethernet/xscale/ixp2000/
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe/ixgbevf)
M: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
@ -3368,13 +3377,13 @@ M: Bruce Allan <bruce.w.allan@intel.com>
M: Carolyn Wyborny <carolyn.wyborny@intel.com>
M: Don Skidmore <donald.c.skidmore@intel.com>
M: Greg Rose <gregory.v.rose@intel.com>
M: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>
M: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
M: Alex Duyck <alexander.h.duyck@intel.com>
M: John Ronciak <john.ronciak@intel.com>
L: e1000-devel@lists.sourceforge.net
W: http://e1000.sourceforge.net/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next.git
S: Supported
F: Documentation/networking/e100.txt
F: Documentation/networking/e1000.txt
@ -3384,14 +3393,7 @@ F: Documentation/networking/igbvf.txt
F: Documentation/networking/ixgb.txt
F: Documentation/networking/ixgbe.txt
F: Documentation/networking/ixgbevf.txt
F: drivers/net/e100.c
F: drivers/net/e1000/
F: drivers/net/e1000e/
F: drivers/net/igb/
F: drivers/net/igbvf/
F: drivers/net/ixgb/
F: drivers/net/ixgbe/
F: drivers/net/ixgbevf/
F: drivers/net/ethernet/intel/
INTEL MRST PMU DRIVER
M: Len Brown <len.brown@intel.com>
@ -3443,7 +3445,7 @@ M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
M: Intel Linux Wireless <ilw@linux.intel.com>
L: linux-wireless@vger.kernel.org
W: http://intellinuxwireless.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-2.6.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi.git
S: Supported
F: drivers/net/wireless/iwlwifi/
@ -3459,7 +3461,7 @@ IOC3 ETHERNET DRIVER
M: Ralf Baechle <ralf@linux-mips.org>
L: linux-mips@linux-mips.org
S: Maintained
F: drivers/net/ioc3-eth.c
F: drivers/net/ethernet/sgi/ioc3-eth.c
IOC3 SERIAL DRIVER
M: Pat Gefre <pfg@sgi.com>
@ -3477,7 +3479,7 @@ M: Francois Romieu <romieu@fr.zoreil.com>
M: Sorbica Shieh <sorbica@icplus.com.tw>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ipg.*
F: drivers/net/ethernet/icplus/ipg.*
IPATH DRIVER
M: Mike Marciniszyn <infinipath@qlogic.com>
@ -3625,7 +3627,7 @@ JME NETWORK DRIVER
M: Guo-Fu Tseng <cooldavid@cooldavid.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/jme.*
F: drivers/net/ethernet/jme.*
JOURNALLING FLASH FILE SYSTEM V2 (JFFS2)
M: David Woodhouse <dwmw2@infradead.org>
@ -4156,7 +4158,7 @@ MARVELL MV643XX ETHERNET DRIVER
M: Lennert Buytenhek <buytenh@wantstofly.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/mv643xx_eth.*
F: drivers/net/ethernet/marvell/mv643xx_eth.*
F: include/linux/mv643xx.h
MARVELL MWIFIEX WIRELESS DRIVER
@ -4370,12 +4372,12 @@ M: Andrew Gallatin <gallatin@myri.com>
L: netdev@vger.kernel.org
W: http://www.myri.com/scs/download-Myri10GE.html
S: Supported
F: drivers/net/myri10ge/
F: drivers/net/ethernet/myricom/myri10ge/
NATSEMI ETHERNET DRIVER (DP8381x)
M: Tim Hockin <thockin@hockin.org>
S: Maintained
F: drivers/net/natsemi.c
F: drivers/net/ethernet/natsemi/natsemi.c
NATIVE INSTRUMENTS USB SOUND INTERFACE DRIVER
M: Daniel Mack <zonque@gmail.com>
@ -4415,9 +4417,8 @@ W: http://trac.neterion.com/cgi-bin/trac.cgi/wiki/Linux?Anonymous
W: http://trac.neterion.com/cgi-bin/trac.cgi/wiki/X3100Linux?Anonymous
S: Supported
F: Documentation/networking/s2io.txt
F: drivers/net/s2io*
F: Documentation/networking/vxge.txt
F: drivers/net/vxge/
F: drivers/net/ethernet/neterion/
NETFILTER/IPTABLES/IPCHAINS
P: Rusty Russell
@ -4531,11 +4532,23 @@ F: include/linux/if_*
F: include/linux/*device.h
NETXEN (1/10) GbE SUPPORT
M: Amit Kumar Salecha <amit.salecha@qlogic.com>
M: Sony Chacko <sony.chacko@qlogic.com>
M: Rajesh Borundia <rajesh.borundia@qlogic.com>
L: netdev@vger.kernel.org
W: http://www.qlogic.com
S: Supported
F: drivers/net/netxen/
F: drivers/net/ethernet/qlogic/netxen/
NFC SUBSYSTEM
M: Lauro Ramos Venancio <lauro.venancio@openbossa.org>
M: Aloisio Almeida Jr <aloisio.almeida@openbossa.org>
M: Samuel Ortiz <sameo@linux.intel.com>
L: linux-wireless@vger.kernel.org
S: Maintained
F: net/nfc/
F: include/linux/nfc.h
F: include/net/nfc/
F: drivers/nfc/
NFS, SUNRPC, AND LOCKD CLIENTS
M: Trond Myklebust <Trond.Myklebust@netapp.com>
@ -4556,7 +4569,7 @@ M: Jan-Pascal van Best <janpascal@vanbest.org>
M: Andreas Mohr <andi@lisas.de>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ni5010.*
F: drivers/net/ethernet/racal/ni5010.*
NILFS2 FILESYSTEM
M: KONISHI Ryusuke <konishi.ryusuke@lab.ntt.co.jp>
@ -4822,7 +4835,7 @@ PA SEMI ETHERNET DRIVER
M: Olof Johansson <olof@lixom.net>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/pasemi_mac.*
F: drivers/net/ethernet/pasemi/*
PA SEMI SMBUS DRIVER
M: Olof Johansson <olof@lixom.net>
@ -4969,7 +4982,7 @@ PCNET32 NETWORK DRIVER
M: Don Fry <pcnet32@frontier.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/pcnet32.c
F: drivers/net/ethernet/amd/pcnet32.c
PCRYPT PARALLEL CRYPTO ENGINE
M: Steffen Klassert <steffen.klassert@secunet.com>
@ -5101,7 +5114,7 @@ PPP PROTOCOL DRIVERS AND COMPRESSORS
M: Paul Mackerras <paulus@samba.org>
L: linux-ppp@vger.kernel.org
S: Maintained
F: drivers/net/ppp_*
F: drivers/net/ppp/ppp_*
PPP OVER ATM (RFC 2364)
M: Mitchell Blank Jr <mitch@sfgoth.com>
@ -5112,8 +5125,8 @@ F: include/linux/atmppp.h
PPP OVER ETHERNET
M: Michal Ostrowski <mostrows@earthlink.net>
S: Maintained
F: drivers/net/pppoe.c
F: drivers/net/pppox.c
F: drivers/net/ppp/pppoe.c
F: drivers/net/ppp/pppox.c
PPP OVER L2TP
M: James Chapman <jchapman@katalix.com>
@ -5134,7 +5147,7 @@ PPTP DRIVER
M: Dmitry Kozlov <xeb@mail.ru>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/pptp.c
F: drivers/net/ppp/pptp.c
W: http://sourceforge.net/projects/accel-pptp
PREEMPTIBLE KERNEL
@ -5163,7 +5176,7 @@ M: Geoff Levand <geoff@infradead.org>
L: netdev@vger.kernel.org
L: cbe-oss-dev@lists.ozlabs.org
S: Maintained
F: drivers/net/ps3_gelic_net.*
F: drivers/net/ethernet/toshiba/ps3_gelic_net.*
PS3 PLATFORM SUPPORT
M: Geoff Levand <geoff@infradead.org>
@ -5281,23 +5294,24 @@ M: linux-driver@qlogic.com
L: netdev@vger.kernel.org
S: Supported
F: Documentation/networking/LICENSE.qla3xxx
F: drivers/net/qla3xxx.*
F: drivers/net/ethernet/qlogic/qla3xxx.*
QLOGIC QLCNIC (1/10)Gb ETHERNET DRIVER
M: Amit Kumar Salecha <amit.salecha@qlogic.com>
M: Anirban Chakraborty <anirban.chakraborty@qlogic.com>
M: Sony Chacko <sony.chacko@qlogic.com>
M: linux-driver@qlogic.com
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/qlcnic/
F: drivers/net/ethernet/qlogic/qlcnic/
QLOGIC QLGE 10Gb ETHERNET DRIVER
M: Anirban Chakraborty <anirban.chakraborty@qlogic.com>
M: Jitendra Kalsaria <jitendra.kalsaria@qlogic.com>
M: Ron Mercer <ron.mercer@qlogic.com>
M: linux-driver@qlogic.com
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/qlge/
F: drivers/net/ethernet/qlogic/qlge/
QNX4 FILESYSTEM
M: Anders Larsen <al@alarsen.net>
@ -5379,7 +5393,7 @@ RDC R6040 FAST ETHERNET DRIVER
M: Florian Fainelli <florian@openwrt.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/r6040.c
F: drivers/net/ethernet/rdc/r6040.c
RDS - RELIABLE DATAGRAM SOCKETS
M: Andy Grover <andy.grover@oracle.com>
@ -5783,7 +5797,7 @@ M: Ajit Khaparde <ajit.khaparde@emulex.com>
L: netdev@vger.kernel.org
W: http://www.emulex.com
S: Supported
F: drivers/net/benet/
F: drivers/net/ethernet/emulex/benet/
SFC NETWORK DRIVER
M: Solarflare linux maintainers <linux-net-drivers@solarflare.com>
@ -5791,7 +5805,7 @@ M: Steve Hodgson <shodgson@solarflare.com>
M: Ben Hutchings <bhutchings@solarflare.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/sfc/
F: drivers/net/ethernet/sfc/
SGI GRU DRIVER
M: Jack Steiner <steiner@sgi.com>
@ -5857,14 +5871,14 @@ SIS 190 ETHERNET DRIVER
M: Francois Romieu <romieu@fr.zoreil.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/sis190.c
F: drivers/net/ethernet/sis/sis190.c
SIS 900/7016 FAST ETHERNET DRIVER
M: Daniele Venzano <venza@brownhat.org>
W: http://www.brownhat.org/sis900.html
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/sis900.*
F: drivers/net/ethernet/sis/sis900.*
SIS 96X I2C/SMBUS DRIVER
M: "Mark M. Hoffman" <mhoffman@lightlink.com>
@ -5891,8 +5905,7 @@ SKGE, SKY2 10/100/1000 GIGABIT ETHERNET DRIVERS
M: Stephen Hemminger <shemminger@linux-foundation.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/skge.*
F: drivers/net/sky2.*
F: drivers/net/ethernet/marvell/sk*
SLAB ALLOCATOR
M: Christoph Lameter <cl@linux-foundation.org>
@ -5906,7 +5919,7 @@ F: mm/sl?b.c
SMC91x ETHERNET DRIVER
M: Nicolas Pitre <nico@fluxnic.net>
S: Odd Fixes
F: drivers/net/smc91x.*
F: drivers/net/ethernet/smsc/smc91x.*
SMM665 HARDWARE MONITOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
@ -5941,13 +5954,13 @@ M: Steve Glendinning <steve.glendinning@smsc.com>
L: netdev@vger.kernel.org
S: Supported
F: include/linux/smsc911x.h
F: drivers/net/smsc911x.*
F: drivers/net/ethernet/smsc/smsc911x.*
SMSC9420 PCI ETHERNET DRIVER
M: Steve Glendinning <steve.glendinning@smsc.com>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/smsc9420.*
F: drivers/net/ethernet/smsc/smsc9420.*
SN-IA64 (Itanium) SUB-PLATFORM
M: Jes Sorensen <jes@sgi.com>
@ -5981,7 +5994,7 @@ SONIC NETWORK DRIVER
M: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/sonic.*
F: drivers/net/ethernet/natsemi/sonic.*
SONICS SILICON BACKPLANE DRIVER (SSB)
M: Michael Buesch <m@bues.ch>
@ -6122,7 +6135,7 @@ M: Jens Osterkamp <jens@de.ibm.com>
L: netdev@vger.kernel.org
S: Supported
F: Documentation/networking/spider_net.txt
F: drivers/net/spider_net*
F: drivers/net/ethernet/toshiba/spider_net*
SPU FILE SYSTEM
M: Jeremy Kerr <jk@ozlabs.org>
@ -6169,12 +6182,6 @@ M: Jakub Schmidtke <sjakub@gmail.com>
S: Odd Fixes
F: drivers/staging/asus_oled/
STAGING - ATHEROS ATH6KL WIRELESS DRIVER
M: Luis R. Rodriguez <mcgrof@gmail.com>
M: Naveen Singh <nsingh@atheros.com>
S: Odd Fixes
F: drivers/staging/ath6kl/
STAGING - COMEDI
M: Ian Abbott <abbotti@mev.co.uk>
M: Mori Hess <fmhess@users.sourceforge.net>
@ -6300,7 +6307,7 @@ F: drivers/staging/xgifb/
STARFIRE/DURALAN NETWORK DRIVER
M: Ion Badulescu <ionut@badula.org>
S: Odd Fixes
F: drivers/net/starfire*
F: drivers/net/ethernet/adaptec/starfire*
SUN3/3X
M: Sam Creasey <sammy@sammy.net>
@ -6309,6 +6316,7 @@ S: Maintained
F: arch/m68k/kernel/*sun3*
F: arch/m68k/sun3*/
F: arch/m68k/include/asm/sun3*
F: drivers/net/ethernet/i825xx/sun3*
SUPERH
M: Paul Mundt <lethal@linux-sh.org>
@ -6396,7 +6404,7 @@ TEHUTI ETHERNET DRIVER
M: Andy Gospodarek <andy@greyhouse.net>
L: netdev@vger.kernel.org
S: Supported
F: drivers/net/tehuti*
F: drivers/net/ethernet/tehuti/*
Telecom Clock Driver for MCPL0010
M: Mark Gross <mark.gross@intel.com>
@ -6447,7 +6455,7 @@ W: http://www.tilera.com/scm/
S: Supported
F: arch/tile/
F: drivers/tty/hvc/hvc_tile.c
F: drivers/net/tile/
F: drivers/net/ethernet/tile/
F: drivers/edac/tile_edac.c
TLAN NETWORK DRIVER
@ -6456,7 +6464,7 @@ L: tlan-devel@lists.sourceforge.net (subscribers-only)
W: http://sourceforge.net/projects/tlan/
S: Maintained
F: Documentation/networking/tlan.txt
F: drivers/net/tlan.*
F: drivers/net/ethernet/ti/tlan.*
TOMOYO SECURITY MODULE
M: Kentaro Takeda <takedakn@nttdata.co.jp>
@ -6550,7 +6558,7 @@ TULIP NETWORK DRIVERS
M: Grant Grundler <grundler@parisc-linux.org>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/tulip/
F: drivers/net/ethernet/tulip/
TUN/TAP driver
M: Maxim Krasnyansky <maxk@qualcomm.com>
@ -6596,7 +6604,7 @@ W: http://uclinux-h8.sourceforge.jp/
S: Supported
F: arch/h8300/
F: drivers/ide/ide-h8300.c
F: drivers/net/ne-h8300.c
F: drivers/net/ethernet/8390/ne-h8300.c
UDF FILESYSTEM
M: Jan Kara <jack@suse.cz>
@ -7024,7 +7032,7 @@ F: include/linux/vhost.h
VIA RHINE NETWORK DRIVER
M: Roger Luethi <rl@hellgate.ch>
S: Maintained
F: drivers/net/via-rhine.c
F: drivers/net/ethernet/via/via-rhine.c
VIAPRO SMBUS DRIVER
M: Jean Delvare <khali@linux-fr.org>
@ -7052,7 +7060,7 @@ VIA VELOCITY NETWORK DRIVER
M: Francois Romieu <romieu@fr.zoreil.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/via-velocity.*
F: drivers/net/ethernet/via/via-velocity.*
VLAN (802.1Q)
M: Patrick McHardy <kaber@trash.net>

1
arch/cris/arch-v10/drivers/Kconfig
View File

@ -4,6 +4,7 @@ config ETRAX_ETHERNET
bool "Ethernet support"
depends on ETRAX_ARCH_V10
select NET_ETHERNET
select NET_CORE
select MII
help
This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet

1
arch/cris/arch-v32/drivers/Kconfig
View File

@ -4,6 +4,7 @@ config ETRAX_ETHERNET
bool "Ethernet support"
depends on ETRAX_ARCH_V32
select NET_ETHERNET
select NET_CORE
select MII
help
This option enables the ETRAX FS built-in 10/100Mbit Ethernet

2
arch/ia64/hp/sim/simeth.c
View File

@ -172,7 +172,7 @@ static const struct net_device_ops simeth_netdev_ops = {
.ndo_stop = simeth_close,
.ndo_start_xmit = simeth_tx,
.ndo_get_stats = simeth_get_stats,
.ndo_set_multicast_list = set_multicast_list, /* not yet used */
.ndo_set_rx_mode = set_multicast_list, /* not yet used */
};

8
arch/mips/Kconfig
View File

@ -92,15 +92,8 @@ config BCM47XX
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_LITTLE_ENDIAN
select SSB
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
select SSB_B43_PCI_BRIDGE if PCI
select SSB_PCICORE_HOSTMODE if PCI
select GENERIC_GPIO
select SYS_HAS_EARLY_PRINTK
select CFE
@ -791,6 +784,7 @@ endchoice
source "arch/mips/alchemy/Kconfig"
source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/jz4740/Kconfig"

31
arch/mips/bcm47xx/Kconfig Normal file
View File

@ -0,0 +1,31 @@
if BCM47XX
config BCM47XX_SSB
bool "SSB Support for Broadcom BCM47XX"
select SYS_HAS_CPU_MIPS32_R1
select SSB
select SSB_DRIVER_MIPS
select SSB_DRIVER_EXTIF
select SSB_EMBEDDED
select SSB_B43_PCI_BRIDGE if PCI
select SSB_PCICORE_HOSTMODE if PCI
default y
help
Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
This will generate an image with support for SSB and MIPS32 R1 instruction set.
config BCM47XX_BCMA
bool "BCMA Support for Broadcom BCM47XX"
select SYS_HAS_CPU_MIPS32_R2
select BCMA
select BCMA_HOST_SOC
select BCMA_DRIVER_MIPS
select BCMA_DRIVER_PCI_HOSTMODE if PCI
default y
help
Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
This will generate an image with support for BCMA and MIPS32 R2 instruction set.
endif

3
arch/mips/bcm47xx/Makefile
View File

@ -3,4 +3,5 @@
# under Linux.
#
obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o

84
arch/mips/bcm47xx/gpio.c
View File

@ -20,42 +20,82 @@ static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES);
int gpio_request(unsigned gpio, const char *tag)
{
if (ssb_chipco_available(&ssb_bcm47xx.chipco) &&
((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
return -EINVAL;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
return -EINVAL;
if (ssb_extif_available(&ssb_bcm47xx.extif) &&
((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
return -EINVAL;
if (ssb_extif_available(&bcm47xx_bus.ssb.extif) &&
((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
return -EINVAL;
if (test_and_set_bit(gpio, gpio_in_use))
return -EBUSY;
if (test_and_set_bit(gpio, gpio_in_use))
return -EBUSY;
return 0;
return 0;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
if (gpio >= BCM47XX_CHIPCO_GPIO_LINES)
return -EINVAL;
if (test_and_set_bit(gpio, gpio_in_use))
return -EBUSY;
return 0;
#endif
}
return -EINVAL;
}
EXPORT_SYMBOL(gpio_request);
void gpio_free(unsigned gpio)
{
if (ssb_chipco_available(&ssb_bcm47xx.chipco) &&
((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
return;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
return;
if (ssb_extif_available(&ssb_bcm47xx.extif) &&
((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
return;
if (ssb_extif_available(&bcm47xx_bus.ssb.extif) &&
((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
return;
clear_bit(gpio, gpio_in_use);
clear_bit(gpio, gpio_in_use);
return;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
if (gpio >= BCM47XX_CHIPCO_GPIO_LINES)
return;
clear_bit(gpio, gpio_in_use);
return;
#endif
}
}
EXPORT_SYMBOL(gpio_free);
int gpio_to_irq(unsigned gpio)
{
if (ssb_chipco_available(&ssb_bcm47xx.chipco))
return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
else if (ssb_extif_available(&ssb_bcm47xx.extif))
return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
else
return -EINVAL;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))
return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
else if (ssb_extif_available(&bcm47xx_bus.ssb.extif))
return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;
else
return -EINVAL;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2;
#endif
}
return -EINVAL;
}
EXPORT_SYMBOL_GPL(gpio_to_irq);

12
arch/mips/bcm47xx/irq.c
View File

@ -26,6 +26,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <asm/irq_cpu.h>
#include <bcm47xx.h>
void plat_irq_dispatch(void)
{
@ -51,5 +52,16 @@ void plat_irq_dispatch(void)
void __init arch_init_irq(void)
{
#ifdef CONFIG_BCM47XX_BCMA
if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core,
BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31);
/*
* the kernel reads the timer irq from some register and thinks
* it's #5, but we offset it by 2 and route to #7
*/
cp0_compare_irq = 7;
}
#endif
mips_cpu_irq_init();
}

29
arch/mips/bcm47xx/nvram.c
View File

@ -26,14 +26,35 @@ static char nvram_buf[NVRAM_SPACE];
/* Probe for NVRAM header */
static void early_nvram_init(void)
{
struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
#ifdef CONFIG_BCM47XX_SSB
struct ssb_mipscore *mcore_ssb;
#endif
#ifdef CONFIG_BCM47XX_BCMA
struct bcma_drv_cc *bcma_cc;
#endif
struct nvram_header *header;
int i;
u32 base, lim, off;
u32 base = 0;
u32 lim = 0;
u32 off;
u32 *src, *dst;
base = mcore->flash_window;
lim = mcore->flash_window_size;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
mcore_ssb = &bcm47xx_bus.ssb.mipscore;
base = mcore_ssb->flash_window;
lim = mcore_ssb->flash_window_size;
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
base = bcma_cc->pflash.window;
lim = bcma_cc->pflash.window_size;
break;
#endif
}
off = FLASH_MIN;
while (off <= lim) {

46
arch/mips/bcm47xx/serial.c
View File

@ -23,10 +23,11 @@ static struct platform_device uart8250_device = {
},
};
static int __init uart8250_init(void)
#ifdef CONFIG_BCM47XX_SSB
static int __init uart8250_init_ssb(void)
{
int i;
struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore);
struct ssb_mipscore *mcore = &(bcm47xx_bus.ssb.mipscore);
memset(&uart8250_data, 0, sizeof(uart8250_data));
@ -44,6 +45,47 @@ static int __init uart8250_init(void)
}
return platform_device_register(&uart8250_device);
}
#endif
#ifdef CONFIG_BCM47XX_BCMA
static int __init uart8250_init_bcma(void)
{
int i;
struct bcma_drv_cc *cc = &(bcm47xx_bus.bcma.bus.drv_cc);
memset(&uart8250_data, 0, sizeof(uart8250_data));
for (i = 0; i < cc->nr_serial_ports; i++) {
struct plat_serial8250_port *p = &(uart8250_data[i]);
struct bcma_serial_port *bcma_port;
bcma_port = &(cc->serial_ports[i]);
p->mapbase = (unsigned int) bcma_port->regs;
p->membase = (void *) bcma_port->regs;
p->irq = bcma_port->irq + 2;
p->uartclk = bcma_port->baud_base;
p->regshift = bcma_port->reg_shift;
p->iotype = UPIO_MEM;
p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
}
return platform_device_register(&uart8250_device);
}
#endif
static int __init uart8250_init(void)
{
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
return uart8250_init_ssb();
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
return uart8250_init_bcma();
#endif
}
return -EINVAL;
}
module_init(uart8250_init);

90
arch/mips/bcm47xx/setup.c
View File

@ -29,21 +29,36 @@
#include <linux/types.h>
#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_embedded.h>
#include <linux/bcma/bcma_soc.h>
#include <asm/bootinfo.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <bcm47xx.h>
#include <asm/mach-bcm47xx/nvram.h>
struct ssb_bus ssb_bcm47xx;
EXPORT_SYMBOL(ssb_bcm47xx);
union bcm47xx_bus bcm47xx_bus;
EXPORT_SYMBOL(bcm47xx_bus);
enum bcm47xx_bus_type bcm47xx_bus_type;
EXPORT_SYMBOL(bcm47xx_bus_type);
static void bcm47xx_machine_restart(char *command)
{
printk(KERN_ALERT "Please stand by while rebooting the system...\n");
local_irq_disable();
/* Set the watchdog timer to reset immediately */
ssb_watchdog_timer_set(&ssb_bcm47xx, 1);
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
break;
#endif
}
while (1)
cpu_relax();
}
@ -52,11 +67,23 @@ static void bcm47xx_machine_halt(void)
{
/* Disable interrupts and watchdog and spin forever */
local_irq_disable();
ssb_watchdog_timer_set(&ssb_bcm47xx, 0);
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
break;
#endif
}
while (1)
cpu_relax();
}
#ifdef CONFIG_BCM47XX_SSB
#define READ_FROM_NVRAM(_outvar, name, buf) \
if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
sprom->_outvar = simple_strtoul(buf, NULL, 0);
@ -247,7 +274,7 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
return 0;
}
void __init plat_mem_setup(void)
static void __init bcm47xx_register_ssb(void)
{
int err;
char buf[100];
@ -258,12 +285,12 @@ void __init plat_mem_setup(void)
printk(KERN_WARNING "bcm47xx: someone else already registered"
" a ssb SPROM callback handler (err %d)\n", err);
err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
err = ssb_bus_ssbbus_register(&(bcm47xx_bus.ssb), SSB_ENUM_BASE,
bcm47xx_get_invariants);
if (err)
panic("Failed to initialize SSB bus (err %d)\n", err);
mcore = &ssb_bcm47xx.mipscore;
mcore = &bcm47xx_bus.ssb.mipscore;
if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
if (strstr(buf, "console=ttyS1")) {
struct ssb_serial_port port;
@ -276,8 +303,57 @@ void __init plat_mem_setup(void)
memcpy(&mcore->serial_ports[1], &port, sizeof(port));
}
}
}
#endif
#ifdef CONFIG_BCM47XX_BCMA
static void __init bcm47xx_register_bcma(void)
{
int err;
err = bcma_host_soc_register(&bcm47xx_bus.bcma);
if (err)
panic("Failed to initialize BCMA bus (err %d)\n", err);
}
#endif
void __init plat_mem_setup(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
if (c->cputype == CPU_74K) {
printk(KERN_INFO "bcm47xx: using bcma bus\n");
#ifdef CONFIG_BCM47XX_BCMA
bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
bcm47xx_register_bcma();
#endif
} else {
printk(KERN_INFO "bcm47xx: using ssb bus\n");
#ifdef CONFIG_BCM47XX_SSB
bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
bcm47xx_register_ssb();
#endif
}
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
}
static int __init bcm47xx_register_bus_complete(void)
{
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
/* Nothing to do */
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_bus_register(&bcm47xx_bus.bcma.bus);
break;
#endif
}
return 0;
}
device_initcall(bcm47xx_register_bus_complete);

16
arch/mips/bcm47xx/time.c
View File

@ -30,7 +30,7 @@
void __init plat_time_init(void)
{
unsigned long hz;
unsigned long hz = 0;
/*
* Use deterministic values for initial counter interrupt
@ -39,7 +39,19 @@ void __init plat_time_init(void)
write_c0_count(0);
write_c0_compare(0xffff);
hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
break;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
break;
#endif
}
if (!hz)
hz = 100000000;

14
arch/mips/bcm47xx/wgt634u.c
View File

@ -108,7 +108,7 @@ static irqreturn_t gpio_interrupt(int irq, void *ignored)
/* Interrupts are shared, check if the current one is
a GPIO interrupt. */
if (!ssb_chipco_irq_status(&ssb_bcm47xx.chipco,
if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco,
SSB_CHIPCO_IRQ_GPIO))
return IRQ_NONE;
@ -132,22 +132,26 @@ static int __init wgt634u_init(void)
* machine. Use the MAC address as an heuristic. Netgear Inc. has
* been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
*/
u8 *et0mac;
u8 *et0mac = ssb_bcm47xx.sprom.et0mac;
if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
return -ENODEV;
et0mac = bcm47xx_bus.ssb.sprom.et0mac;
if (et0mac[0] == 0x00 &&
((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
(et0mac[1] == 0x0f && et0mac[2] == 0xb5))) {
struct ssb_mipscore *mcore = &ssb_bcm47xx.mipscore;
struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore;
printk(KERN_INFO "WGT634U machine detected.\n");
if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET),
gpio_interrupt, IRQF_SHARED,
"WGT634U GPIO", &ssb_bcm47xx.chipco)) {
"WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) {
gpio_direction_input(WGT634U_GPIO_RESET);
gpio_intmask(WGT634U_GPIO_RESET, 1);
ssb_chipco_irq_mask(&ssb_bcm47xx.chipco,
ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco,
SSB_CHIPCO_IRQ_GPIO,
SSB_CHIPCO_IRQ_GPIO);
}

26
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
View File

@ -19,7 +19,29 @@
#ifndef __ASM_BCM47XX_H
#define __ASM_BCM47XX_H
/* SSB bus */
extern struct ssb_bus ssb_bcm47xx;
#include <linux/ssb/ssb.h>
#include <linux/bcma/bcma.h>
#include <linux/bcma/bcma_soc.h>
enum bcm47xx_bus_type {
#ifdef CONFIG_BCM47XX_SSB
BCM47XX_BUS_TYPE_SSB,
#endif
#ifdef CONFIG_BCM47XX_BCMA
BCM47XX_BUS_TYPE_BCMA,
#endif
};
union bcm47xx_bus {
#ifdef CONFIG_BCM47XX_SSB
struct ssb_bus ssb;
#endif
#ifdef CONFIG_BCM47XX_BCMA
struct bcma_soc bcma;
#endif
};
extern union bcm47xx_bus bcm47xx_bus;
extern enum bcm47xx_bus_type bcm47xx_bus_type;
#endif /* __ASM_BCM47XX_H */

108
arch/mips/include/asm/mach-bcm47xx/gpio.h
View File

@ -10,6 +10,7 @@
#define __BCM47XX_GPIO_H
#include <linux/ssb/ssb_embedded.h>
#include <linux/bcma/bcma.h>
#include <asm/mach-bcm47xx/bcm47xx.h>
#define BCM47XX_EXTIF_GPIO_LINES 5
@ -21,41 +22,118 @@ extern int gpio_to_irq(unsigned gpio);
static inline int gpio_get_value(unsigned gpio)
{
return ssb_gpio_in(&ssb_bcm47xx, 1 << gpio);
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc,
1 << gpio);
#endif
}
return -EINVAL;
}
static inline void gpio_set_value(unsigned gpio, int value)
{
ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
value ? 1 << gpio : 0);
return;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
value ? 1 << gpio : 0);
return;
#endif
}
}
static inline int gpio_direction_input(unsigned gpio)
{
ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 0);
return 0;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
return 0;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
0);
return 0;
#endif
}
return -EINVAL;
}
static inline int gpio_direction_output(unsigned gpio, int value)
{
/* first set the gpio out value */
ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
/* then set the gpio mode */
ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
return 0;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
/* first set the gpio out value */
ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
value ? 1 << gpio : 0);
/* then set the gpio mode */
ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
return 0;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
/* first set the gpio out value */
bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
value ? 1 << gpio : 0);
/* then set the gpio mode */
bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
1 << gpio);
return 0;
#endif
}
return -EINVAL;
}
static inline int gpio_intmask(unsigned gpio, int value)
{
ssb_gpio_intmask(&ssb_bcm47xx, 1 << gpio,
value ? 1 << gpio : 0);
return 0;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
value ? 1 << gpio : 0);
return 0;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
1 << gpio, value ? 1 << gpio : 0);
return 0;
#endif
}
return -EINVAL;
}
static inline int gpio_polarity(unsigned gpio, int value)
{
ssb_gpio_polarity(&ssb_bcm47xx, 1 << gpio,
value ? 1 << gpio : 0);
return 0;
switch (bcm47xx_bus_type) {
#ifdef CONFIG_BCM47XX_SSB
case BCM47XX_BUS_TYPE_SSB:
ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
value ? 1 << gpio : 0);
return 0;
#endif
#ifdef CONFIG_BCM47XX_BCMA
case BCM47XX_BUS_TYPE_BCMA:
bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
1 << gpio, value ? 1 << gpio : 0);
return 0;
#endif
}
return -EINVAL;
}

6
arch/mips/pci/pci-bcm47xx.c
View File

@ -25,6 +25,7 @@
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/ssb/ssb.h>
#include <bcm47xx.h>
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
@ -33,9 +34,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int pcibios_plat_dev_init(struct pci_dev *dev)
{
#ifdef CONFIG_BCM47XX_SSB
int res;
u8 slot, pin;
if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
return 0;
res = ssb_pcibios_plat_dev_init(dev);
if (res < 0) {
printk(KERN_ALERT "PCI: Failed to init device %s\n",
@ -55,5 +60,6 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
}
dev->irq = res;
#endif
return 0;
}

2
arch/mips/txx9/generic/setup_tx4939.c
View File

@ -321,7 +321,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
static u32 tx4939_get_eth_speed(struct net_device *dev)
{
struct ethtool_cmd cmd;
if (dev_ethtool_get_settings(dev, &cmd))
if (__ethtool_get_settings(dev, &cmd))
return 100; /* default 100Mbps */
return ethtool_cmd_speed(&cmd);

2
arch/powerpc/Kconfig
View File

@ -656,6 +656,8 @@ config SBUS
config FSL_SOC
bool
select HAVE_CAN_FLEXCAN if NET && CAN
select PPC_CLOCK if CAN_FLEXCAN
config FSL_PCI
bool

10
arch/powerpc/boot/dts/p1010rdb.dts
View File

@ -23,6 +23,8 @@
ethernet2 = &enet2;
pci0 = &pci0;
pci1 = &pci1;
can0 = &can0;
can1 = &can1;
};
memory {
@ -169,14 +171,6 @@
};
};
can0@1c000 {
fsl,flexcan-clock-source = "platform";
};
can1@1d000 {
fsl,flexcan-clock-source = "platform";
};
usb@22000 {
phy_type = "utmi";
};

10
arch/powerpc/boot/dts/p1010si.dtsi
View File

@ -140,20 +140,18 @@
interrupt-parent = <&mpic>;
};
can0@1c000 {
compatible = "fsl,flexcan-v1.0";
can0: can@1c000 {
compatible = "fsl,p1010-flexcan";
reg = <0x1c000 0x1000>;
interrupts = <48 0x2>;
interrupt-parent = <&mpic>;
fsl,flexcan-clock-divider = <2>;
};
can1@1d000 {
compatible = "fsl,flexcan-v1.0";
can1: can@1d000 {
compatible = "fsl,p1010-flexcan";
reg = <0x1d000 0x1000>;
interrupts = <61 0x2>;
interrupt-parent = <&mpic>;
fsl,flexcan-clock-divider = <2>;
};
L2: l2-cache-controller@20000 {

11
arch/powerpc/configs/40x/acadia_defconfig
View File

@ -44,12 +44,13 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_MII=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_IBM_NEW_EMAC_DEBUG=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
CONFIG_IBM_EMAC_DEBUG=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/40x/ep405_defconfig
View File

@ -42,8 +42,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

5
arch/powerpc/configs/40x/hcu4_defconfig
View File

@ -43,8 +43,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

9
arch/powerpc/configs/40x/kilauea_defconfig
View File

@ -51,10 +51,11 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

9
arch/powerpc/configs/40x/makalu_defconfig
View File

@ -43,10 +43,11 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/40x/walnut_defconfig
View File

@ -40,8 +40,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

9
arch/powerpc/configs/44x/arches_defconfig
View File

@ -44,10 +44,11 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/44x/bamboo_defconfig
View File

@ -32,8 +32,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

9
arch/powerpc/configs/44x/bluestone_defconfig
View File

@ -38,10 +38,11 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=2

9
arch/powerpc/configs/44x/canyonlands_defconfig
View File

@ -49,10 +49,11 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/44x/ebony_defconfig
View File

@ -40,8 +40,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

9
arch/powerpc/configs/44x/eiger_defconfig
View File

@ -55,10 +55,11 @@ CONFIG_FUSION=y
CONFIG_FUSION_SAS=y
CONFIG_I2O=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
CONFIG_E1000E=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/44x/icon_defconfig
View File

@ -56,8 +56,9 @@ CONFIG_FUSION_SAS=y
CONFIG_FUSION_CTL=y
CONFIG_FUSION_LOGGING=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_WLAN is not set

5
arch/powerpc/configs/44x/katmai_defconfig
View File

@ -42,8 +42,9 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

11
arch/powerpc/configs/44x/redwood_defconfig
View File

@ -53,11 +53,12 @@ CONFIG_FUSION=y
CONFIG_FUSION_SAS=y
CONFIG_I2O=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_NEW_EMAC_RXB=256
CONFIG_IBM_NEW_EMAC_TXB=256
CONFIG_IBM_NEW_EMAC_DEBUG=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
CONFIG_IBM_EMAC_RXB=256
CONFIG_IBM_EMAC_TXB=256
CONFIG_IBM_EMAC_DEBUG=y
CONFIG_E1000E=y
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/44x/sam440ep_defconfig
View File

@ -44,8 +44,9 @@ CONFIG_ATA=y
# CONFIG_SATA_PMP is not set
CONFIG_SATA_SIL=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_INPUT_FF_MEMLESS=m

5
arch/powerpc/configs/44x/sequoia_defconfig
View File

@ -46,8 +46,9 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

5
arch/powerpc/configs/44x/taishan_defconfig
View File

@ -40,8 +40,9 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_MACINTOSH_DRIVERS=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set

5
arch/powerpc/configs/44x/warp_defconfig
View File

@ -54,9 +54,10 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SPI_ATTRS=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_MII=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_IBM_EMAC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT is not set

5
arch/powerpc/configs/ppc40x_defconfig
View File

@ -50,8 +50,9 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
CONFIG_XILINX_SYSACE=m
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set

5
arch/powerpc/configs/ppc44x_defconfig
View File

@ -63,8 +63,9 @@ CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_NET_ETHERNET=y
CONFIG_IBM_NEW_EMAC=y
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_IBM=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set

12
arch/powerpc/platforms/40x/Kconfig
View File

@ -130,21 +130,21 @@ config 405GP
bool
select IBM405_ERR77
select IBM405_ERR51
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_ZMII
config 405EP
bool
config 405EX
bool
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
config 405EZ
bool
select IBM_NEW_EMAC_NO_FLOW_CTRL
select IBM_NEW_EMAC_MAL_CLR_ICINTSTAT
select IBM_NEW_EMAC_MAL_COMMON_ERR
select IBM_EMAC_NO_FLOW_CTRL
select IBM_EMAC_MAL_CLR_ICINTSTAT
select IBM_EMAC_MAL_COMMON_ERR
config 405GPR
bool

54
arch/powerpc/platforms/44x/Kconfig
View File

@ -23,7 +23,7 @@ config BLUESTONE
default n
select PPC44x_SIMPLE
select APM821xx
select IBM_NEW_EMAC_RGMII
select IBM_EMAC_RGMII
help
This option enables support for the APM APM821xx Evaluation board.
@ -122,8 +122,8 @@ config CANYONLANDS
select PPC4xx_PCI_EXPRESS
select PCI_MSI
select PPC4xx_MSI
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII
help
This option enables support for the AMCC PPC460EX evaluation board.
@ -135,8 +135,8 @@ config GLACIER
select 460EX # Odd since it uses 460GT but the effects are the same
select PCI
select PPC4xx_PCI_EXPRESS
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII
help
This option enables support for the AMCC PPC460GT evaluation board.
@ -161,7 +161,7 @@ config EIGER
select 460SX
select PCI
select PPC4xx_PCI_EXPRESS
select IBM_NEW_EMAC_RGMII
select IBM_EMAC_RGMII
help
This option enables support for the AMCC PPC460SX evaluation board.
@ -260,59 +260,59 @@ config 440EP
bool
select PPC_FPU
select IBM440EP_ERR42
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_ZMII
select USB_ARCH_HAS_OHCI
config 440EPX
bool
select PPC_FPU
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII
config 440GRX
bool
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII
config 440GP
bool
select IBM_NEW_EMAC_ZMII
select IBM_EMAC_ZMII
config 440GX
bool
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII #test only
select IBM_NEW_EMAC_TAH #test only
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII #test only
select IBM_EMAC_TAH #test only
config 440SP
bool
config 440SPe
bool
select IBM_NEW_EMAC_EMAC4
select IBM_EMAC_EMAC4
config 460EX
bool
select PPC_FPU
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_TAH
select IBM_EMAC_EMAC4
select IBM_EMAC_TAH
config 460SX
bool
select PPC_FPU
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII
select IBM_NEW_EMAC_TAH
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII
select IBM_EMAC_TAH
config APM821xx
bool
select PPC_FPU
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_TAH
select IBM_EMAC_EMAC4
select IBM_EMAC_TAH
# 44x errata/workaround config symbols, selected by the CPU models above
config IBM440EP_ERR42

8
arch/powerpc/platforms/cell/Kconfig
View File

@ -17,10 +17,10 @@ config PPC_CELL_NATIVE
select PPC_CELL_COMMON
select MPIC
select PPC_IO_WORKAROUNDS
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII #test only
select IBM_NEW_EMAC_TAH #test only
select IBM_EMAC_EMAC4
select IBM_EMAC_RGMII
select IBM_EMAC_ZMII #test only
select IBM_EMAC_TAH #test only
default n
config PPC_IBM_CELL_BLADE

78
arch/s390/include/asm/qdio.h
View File

@ -122,6 +122,40 @@ struct slibe {
u64 parms;
};
/**
* struct qaob - queue asynchronous operation block
* @res0: reserved parameters
* @res1: reserved parameter
* @res2: reserved parameter
* @res3: reserved parameter
* @aorc: asynchronous operation return code
* @flags: internal flags
* @cbtbs: control block type
* @sb_count: number of storage blocks
* @sba: storage block element addresses
* @dcount: size of storage block elements
* @user0: user defineable value
* @res4: reserved paramater
* @user1: user defineable value
* @user2: user defineable value
*/
struct qaob {
u64 res0[6];
u8 res1;
u8 res2;
u8 res3;
u8 aorc;
u8 flags;
u16 cbtbs;
u8 sb_count;
u64 sba[QDIO_MAX_ELEMENTS_PER_BUFFER];
u16 dcount[QDIO_MAX_ELEMENTS_PER_BUFFER];
u64 user0;
u64 res4[2];
u64 user1;
u64 user2;
} __attribute__ ((packed, aligned(256)));
/**
* struct slib - storage list information block (SLIB)
* @nsliba: next SLIB address (if any)
@ -225,6 +259,41 @@ struct slsb {
#define CHSC_AC2_DATA_DIV_AVAILABLE 0x0010
#define CHSC_AC2_DATA_DIV_ENABLED 0x0002
/**
* struct qdio_outbuf_state - SBAL related asynchronous operation information
* (for communication with upper layer programs)
* (only required for use with completion queues)
* @flags: flags indicating state of buffer
* @aob: pointer to QAOB used for the particular SBAL
* @user: pointer to upper layer program's state information related to SBAL
* (stored in user1 data of QAOB)
*/
struct qdio_outbuf_state {
u8 flags;
struct qaob *aob;
void *user;
};
#define QDIO_OUTBUF_STATE_FLAG_NONE 0x00
#define QDIO_OUTBUF_STATE_FLAG_PENDING 0x01
#define CHSC_AC1_INITIATE_INPUTQ 0x80
/* qdio adapter-characteristics-1 flag */
#define AC1_SIGA_INPUT_NEEDED 0x40 /* process input queues */
#define AC1_SIGA_OUTPUT_NEEDED 0x20 /* process output queues */
#define AC1_SIGA_SYNC_NEEDED 0x10 /* ask hypervisor to sync */
#define AC1_AUTOMATIC_SYNC_ON_THININT 0x08 /* set by hypervisor */
#define AC1_AUTOMATIC_SYNC_ON_OUT_PCI 0x04 /* set by hypervisor */
#define AC1_SC_QEBSM_AVAILABLE 0x02 /* available for subchannel */
#define AC1_SC_QEBSM_ENABLED 0x01 /* enabled for subchannel */
#define CHSC_AC2_DATA_DIV_AVAILABLE 0x0010
#define CHSC_AC2_DATA_DIV_ENABLED 0x0002
#define CHSC_AC3_FORMAT2_CQ_AVAILABLE 0x8000
struct qdio_ssqd_desc {
u8 flags;
u8:8;
@ -243,8 +312,7 @@ struct qdio_ssqd_desc {
u64 sch_token;
u8 mro;
u8 mri;
u8:8;
u8 sbalic;
u16 qdioac3;
u16:16;
u8:8;
u8 mmwc;
@ -280,9 +348,11 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
* @no_output_qs: number of output queues
* @input_handler: handler to be called for input queues
* @output_handler: handler to be called for output queues
* @queue_start_poll: polling handlers (one per input queue or NULL)
* @int_parm: interruption parameter
* @input_sbal_addr_array: address of no_input_qs * 128 pointers
* @output_sbal_addr_array: address of no_output_qs * 128 pointers
* @output_sbal_state_array: no_output_qs * 128 state info (for CQ or NULL)
*/
struct qdio_initialize {
struct ccw_device *cdev;
@ -297,11 +367,12 @@ struct qdio_initialize {
unsigned int no_output_qs;
qdio_handler_t *input_handler;
qdio_handler_t *output_handler;
void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
int scan_threshold;
unsigned long int_parm;
void **input_sbal_addr_array;
void **output_sbal_addr_array;
struct qdio_outbuf_state *output_sbal_state_array;
};
#define QDIO_STATE_INACTIVE 0x00000002 /* after qdio_cleanup */
@ -316,6 +387,7 @@ struct qdio_initialize {
extern int qdio_allocate(struct qdio_initialize *);
extern int qdio_establish(struct qdio_initialize *);
extern int qdio_activate(struct ccw_device *);
extern void qdio_release_aob(struct qaob *);
extern int do_QDIO(struct ccw_device *, unsigned int, int, unsigned int,
unsigned int);
extern int qdio_start_irq(struct ccw_device *, int);

25
arch/sh/include/asm/sh_eth.h
View File

@ -1,25 +0,0 @@
#ifndef __ASM_SH_ETH_H__
#define __ASM_SH_ETH_H__
#include <linux/phy.h>
enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN};
enum {
SH_ETH_REG_GIGABIT,
SH_ETH_REG_FAST_SH4,
SH_ETH_REG_FAST_SH3_SH2
};
struct sh_eth_plat_data {
int phy;
int edmac_endian;
int register_type;
phy_interface_t phy_interface;
void (*set_mdio_gate)(unsigned long addr);
unsigned char mac_addr[6];
unsigned no_ether_link:1;
unsigned ether_link_active_low:1;
};
#endif

2
arch/um/drivers/net_kern.c
View File

@ -368,7 +368,7 @@ static const struct net_device_ops uml_netdev_ops = {
.ndo_open = uml_net_open,
.ndo_stop = uml_net_close,
.ndo_start_xmit = uml_net_start_xmit,
.ndo_set_multicast_list = uml_net_set_multicast_list,
.ndo_set_rx_mode = uml_net_set_multicast_list,
.ndo_tx_timeout = uml_net_tx_timeout,
.ndo_set_mac_address = eth_mac_addr,
.ndo_change_mtu = uml_net_change_mtu,

2
arch/xtensa/platforms/iss/network.c
View File

@ -633,7 +633,7 @@ static const struct net_device_ops iss_netdev_ops = {
.ndo_set_mac_address = iss_net_set_mac,
//.ndo_do_ioctl = iss_net_ioctl,
.ndo_tx_timeout = iss_net_tx_timeout,
.ndo_set_multicast_list = iss_net_set_multicast_list,
.ndo_set_rx_mode = iss_net_set_multicast_list,
};
static int iss_net_configure(int index, char *init)

5
drivers/atm/eni.c
View File

@ -1134,8 +1134,9 @@ DPRINTK("doing direct send\n"); /* @@@ well, this doesn't work anyway */
skb_headlen(skb));
else
put_dma(tx->index,eni_dev->dma,&j,(unsigned long)
skb_shinfo(skb)->frags[i].page + skb_shinfo(skb)->frags[i].page_offset,
skb_shinfo(skb)->frags[i].size);
skb_frag_page(&skb_shinfo(skb)->frags[i]) +
skb_shinfo(skb)->frags[i].page_offset,
skb_frag_size(&skb_shinfo(skb)->frags[i]));
}
if (skb->len & 3)
put_dma(tx->index,eni_dev->dma,&j,zeroes,4-(skb->len & 3));

261
drivers/atm/iphase.c
View File

@ -818,127 +818,152 @@ static void ia_hw_type(IADEV *iadev) {
}
static void IaFrontEndIntr(IADEV *iadev) {
volatile IA_SUNI *suni;
volatile ia_mb25_t *mb25;
volatile suni_pm7345_t *suni_pm7345;
if(iadev->phy_type & FE_25MBIT_PHY) {
mb25 = (ia_mb25_t*)iadev->phy;
iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
} else if (iadev->phy_type & FE_DS3_PHY) {
suni_pm7345 = (suni_pm7345_t *)iadev->phy;
/* clear FRMR interrupts */
(void) suni_pm7345->suni_ds3_frm_intr_stat;
iadev->carrier_detect =
Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV));
} else if (iadev->phy_type & FE_E3_PHY ) {
suni_pm7345 = (suni_pm7345_t *)iadev->phy;
(void) suni_pm7345->suni_e3_frm_maint_intr_ind;
iadev->carrier_detect =
Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat&SUNI_E3_LOS));
}
else {
suni = (IA_SUNI *)iadev->phy;
(void) suni->suni_rsop_status;
iadev->carrier_detect = Boolean(!(suni->suni_rsop_status & SUNI_LOSV));
}
if (iadev->carrier_detect)
printk("IA: SUNI carrier detected\n");
else
printk("IA: SUNI carrier lost signal\n");
return;
static u32 ia_phy_read32(struct iadev_priv *ia, unsigned int reg)
{
return readl(ia->phy + (reg >> 2));
}
static void ia_mb25_init (IADEV *iadev)
static void ia_phy_write32(struct iadev_priv *ia, unsigned int reg, u32 val)
{
writel(val, ia->phy + (reg >> 2));
}
static void ia_frontend_intr(struct iadev_priv *iadev)
{
u32 status;
if (iadev->phy_type & FE_25MBIT_PHY) {
status = ia_phy_read32(iadev, MB25_INTR_STATUS);
iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
} else if (iadev->phy_type & FE_DS3_PHY) {
ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
} else if (iadev->phy_type & FE_E3_PHY) {
ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
} else {
status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
}
printk(KERN_INFO "IA: SUNI carrier %s\n",
iadev->carrier_detect ? "detected" : "lost signal");
}
static void ia_mb25_init(struct iadev_priv *iadev)
{
volatile ia_mb25_t *mb25 = (ia_mb25_t*)iadev->phy;
#if 0
mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;
#endif
mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC;
mb25->mb25_diag_control = 0;
/*
* Initialize carrier detect state
*/
iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
return;
}
ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
static void ia_suni_pm7345_init (IADEV *iadev)
iadev->carrier_detect =
(ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
}
struct ia_reg {
u16 reg;
u16 val;
};
static void ia_phy_write(struct iadev_priv *iadev,
const struct ia_reg *regs, int len)
{
volatile suni_pm7345_t *suni_pm7345 = (suni_pm7345_t *)iadev->phy;
if (iadev->phy_type & FE_DS3_PHY)
{
iadev->carrier_detect =
Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV));
suni_pm7345->suni_ds3_frm_intr_enbl = 0x17;
suni_pm7345->suni_ds3_frm_cfg = 1;
suni_pm7345->suni_ds3_tran_cfg = 1;
suni_pm7345->suni_config = 0;
suni_pm7345->suni_splr_cfg = 0;
suni_pm7345->suni_splt_cfg = 0;
}
else
{
iadev->carrier_detect =
Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat & SUNI_E3_LOS));
suni_pm7345->suni_e3_frm_fram_options = 0x4;
suni_pm7345->suni_e3_frm_maint_options = 0x20;
suni_pm7345->suni_e3_frm_fram_intr_enbl = 0x1d;
suni_pm7345->suni_e3_frm_maint_intr_enbl = 0x30;
suni_pm7345->suni_e3_tran_stat_diag_options = 0x0;
suni_pm7345->suni_e3_tran_fram_options = 0x1;
suni_pm7345->suni_config = SUNI_PM7345_E3ENBL;
suni_pm7345->suni_splr_cfg = 0x41;
suni_pm7345->suni_splt_cfg = 0x41;
}
/*
* Enable RSOP loss of signal interrupt.
*/
suni_pm7345->suni_intr_enbl = 0x28;
/*
* Clear error counters
*/
suni_pm7345->suni_id_reset = 0;
while (len--) {
ia_phy_write32(iadev, regs->reg, regs->val);
regs++;
}
}
/*
* Clear "PMCTST" in master test register.
*/
suni_pm7345->suni_master_test = 0;
static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev)
{
static const struct ia_reg suni_ds3_init [] = {
{ SUNI_DS3_FRM_INTR_ENBL, 0x17 },
{ SUNI_DS3_FRM_CFG, 0x01 },
{ SUNI_DS3_TRAN_CFG, 0x01 },
{ SUNI_CONFIG, 0 },
{ SUNI_SPLR_CFG, 0 },
{ SUNI_SPLT_CFG, 0 }
};
u32 status;
suni_pm7345->suni_rxcp_ctrl = 0x2c;
suni_pm7345->suni_rxcp_fctrl = 0x81;
suni_pm7345->suni_rxcp_idle_pat_h1 =
suni_pm7345->suni_rxcp_idle_pat_h2 =
suni_pm7345->suni_rxcp_idle_pat_h3 = 0;
suni_pm7345->suni_rxcp_idle_pat_h4 = 1;
suni_pm7345->suni_rxcp_idle_mask_h1 = 0xff;
suni_pm7345->suni_rxcp_idle_mask_h2 = 0xff;
suni_pm7345->suni_rxcp_idle_mask_h3 = 0xff;
suni_pm7345->suni_rxcp_idle_mask_h4 = 0xfe;
suni_pm7345->suni_rxcp_cell_pat_h1 =
suni_pm7345->suni_rxcp_cell_pat_h2 =
suni_pm7345->suni_rxcp_cell_pat_h3 = 0;
suni_pm7345->suni_rxcp_cell_pat_h4 = 1;
suni_pm7345->suni_rxcp_cell_mask_h1 =
suni_pm7345->suni_rxcp_cell_mask_h2 =
suni_pm7345->suni_rxcp_cell_mask_h3 =
suni_pm7345->suni_rxcp_cell_mask_h4 = 0xff;
suni_pm7345->suni_txcp_ctrl = 0xa4;
suni_pm7345->suni_txcp_intr_en_sts = 0x10;
suni_pm7345->suni_txcp_idle_pat_h5 = 0x55;
suni_pm7345->suni_config &= ~(SUNI_PM7345_LLB |
SUNI_PM7345_CLB |
SUNI_PM7345_DLB |
SUNI_PM7345_PLB);
status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
}
static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev)
{
static const struct ia_reg suni_e3_init [] = {
{ SUNI_E3_FRM_FRAM_OPTIONS, 0x04 },
{ SUNI_E3_FRM_MAINT_OPTIONS, 0x20 },
{ SUNI_E3_FRM_FRAM_INTR_ENBL, 0x1d },
{ SUNI_E3_FRM_MAINT_INTR_ENBL, 0x30 },
{ SUNI_E3_TRAN_STAT_DIAG_OPTIONS, 0 },
{ SUNI_E3_TRAN_FRAM_OPTIONS, 0x01 },
{ SUNI_CONFIG, SUNI_PM7345_E3ENBL },
{ SUNI_SPLR_CFG, 0x41 },
{ SUNI_SPLT_CFG, 0x41 }
};
u32 status;
status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
}
static void ia_suni_pm7345_init(struct iadev_priv *iadev)
{
static const struct ia_reg suni_init [] = {
/* Enable RSOP loss of signal interrupt. */
{ SUNI_INTR_ENBL, 0x28 },
/* Clear error counters. */
{ SUNI_ID_RESET, 0 },
/* Clear "PMCTST" in master test register. */
{ SUNI_MASTER_TEST, 0 },
{ SUNI_RXCP_CTRL, 0x2c },
{ SUNI_RXCP_FCTRL, 0x81 },
{ SUNI_RXCP_IDLE_PAT_H1, 0 },
{ SUNI_RXCP_IDLE_PAT_H2, 0 },
{ SUNI_RXCP_IDLE_PAT_H3, 0 },
{ SUNI_RXCP_IDLE_PAT_H4, 0x01 },
{ SUNI_RXCP_IDLE_MASK_H1, 0xff },
{ SUNI_RXCP_IDLE_MASK_H2, 0xff },
{ SUNI_RXCP_IDLE_MASK_H3, 0xff },
{ SUNI_RXCP_IDLE_MASK_H4, 0xfe },
{ SUNI_RXCP_CELL_PAT_H1, 0 },
{ SUNI_RXCP_CELL_PAT_H2, 0 },
{ SUNI_RXCP_CELL_PAT_H3, 0 },
{ SUNI_RXCP_CELL_PAT_H4, 0x01 },
{ SUNI_RXCP_CELL_MASK_H1, 0xff },
{ SUNI_RXCP_CELL_MASK_H2, 0xff },
{ SUNI_RXCP_CELL_MASK_H3, 0xff },
{ SUNI_RXCP_CELL_MASK_H4, 0xff },
{ SUNI_TXCP_CTRL, 0xa4 },
{ SUNI_TXCP_INTR_EN_STS, 0x10 },
{ SUNI_TXCP_IDLE_PAT_H5, 0x55 }
};
if (iadev->phy_type & FE_DS3_PHY)
ia_suni_pm7345_init_ds3(iadev);
else
ia_suni_pm7345_init_e3(iadev);
ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
~(SUNI_PM7345_LLB | SUNI_PM7345_CLB |
SUNI_PM7345_DLB | SUNI_PM7345_PLB));
#ifdef __SNMP__
suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;
#endif /* __SNMP__ */
@ -1425,10 +1450,10 @@ static int rx_init(struct atm_dev *dev)
iadev->dma + IPHASE5575_RX_LIST_ADDR);
IF_INIT(printk("Tx Dle list addr: 0x%p value: 0x%0x\n",
iadev->dma+IPHASE5575_TX_LIST_ADDR,
*(u32*)(iadev->dma+IPHASE5575_TX_LIST_ADDR));
readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
printk("Rx Dle list addr: 0x%p value: 0x%0x\n",
iadev->dma+IPHASE5575_RX_LIST_ADDR,
*(u32*)(iadev->dma+IPHASE5575_RX_LIST_ADDR));)
readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
writew(0, iadev->reass_reg+MODE_REG);
@ -2208,7 +2233,7 @@ static irqreturn_t ia_int(int irq, void *dev_id)
if (status & STAT_DLERINT)
{
/* Clear this bit by writing a 1 to it. */
*(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLERINT;
writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
rx_dle_intr(dev);
}
if (status & STAT_SEGINT)
@ -2219,13 +2244,13 @@ static irqreturn_t ia_int(int irq, void *dev_id)
}
if (status & STAT_DLETINT)
{
*(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLETINT;
writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
tx_dle_intr(dev);
}
if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT))
{
if (status & STAT_FEINT)
IaFrontEndIntr(iadev);
ia_frontend_intr(iadev);
}
}
return IRQ_RETVAL(handled);
@ -2556,7 +2581,7 @@ static int __devinit ia_start(struct atm_dev *dev)
goto err_free_rx;
}
/* Get iadev->carrier_detect status */
IaFrontEndIntr(iadev);
ia_frontend_intr(iadev);
}
return 0;
@ -2827,7 +2852,7 @@ static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
case 0xb:
if (!capable(CAP_NET_ADMIN)) return -EPERM;
IaFrontEndIntr(iadev);
ia_frontend_intr(iadev);
break;
case 0xa:
if (!capable(CAP_NET_ADMIN)) return -EPERM;

391
drivers/atm/iphase.h
View File

@ -889,79 +889,71 @@ typedef struct ia_rtn_q {
} IARTN_Q;
#define SUNI_LOSV 0x04
typedef struct {
u32 suni_master_reset; /* SUNI Master Reset and Identity */
u32 suni_master_config; /* SUNI Master Configuration */
u32 suni_master_intr_stat; /* SUNI Master Interrupt Status */
u32 suni_reserved1; /* Reserved */
u32 suni_master_clk_monitor;/* SUNI Master Clock Monitor */
u32 suni_master_control; /* SUNI Master Clock Monitor */
u32 suni_reserved2[10]; /* Reserved */
enum ia_suni {
SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
SUNI_RESERVED1 = 0x00c, /* Reserved */
SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
/* Reserved (10) */
SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
u32 suni_rsop_control; /* RSOP Control/Interrupt Enable */
u32 suni_rsop_status; /* RSOP Status/Interrupt States */
u32 suni_rsop_section_bip8l;/* RSOP Section BIP-8 LSB */
u32 suni_rsop_section_bip8m;/* RSOP Section BIP-8 MSB */
u32 suni_tsop_control; /* TSOP Control */
u32 suni_tsop_diag; /* TSOP Disgnostics */
u32 suni_tsop_reserved[2]; /* TSOP Reserved */
u32 suni_rlop_cs; /* RLOP Control/Status */
u32 suni_rlop_intr; /* RLOP Interrupt Enable/Status */
u32 suni_rlop_line_bip24l; /* RLOP Line BIP-24 LSB */
u32 suni_rlop_line_bip24; /* RLOP Line BIP-24 */
u32 suni_rlop_line_bip24m; /* RLOP Line BIP-24 MSB */
u32 suni_rlop_line_febel; /* RLOP Line FEBE LSB */
u32 suni_rlop_line_febe; /* RLOP Line FEBE */
u32 suni_rlop_line_febem; /* RLOP Line FEBE MSB */
u32 suni_tlop_control; /* TLOP Control */
u32 suni_tlop_disg; /* TLOP Disgnostics */
u32 suni_tlop_reserved[14]; /* TLOP Reserved */
u32 suni_rpop_cs; /* RPOP Status/Control */
u32 suni_rpop_intr; /* RPOP Interrupt/Status */
u32 suni_rpop_reserved; /* RPOP Reserved */
u32 suni_rpop_intr_ena; /* RPOP Interrupt Enable */
u32 suni_rpop_reserved1[3]; /* RPOP Reserved */
u32 suni_rpop_path_sig; /* RPOP Path Signal Label */
u32 suni_rpop_bip8l; /* RPOP Path BIP-8 LSB */
u32 suni_rpop_bip8m; /* RPOP Path BIP-8 MSB */
u32 suni_rpop_febel; /* RPOP Path FEBE LSB */
u32 suni_rpop_febem; /* RPOP Path FEBE MSB */
u32 suni_rpop_reserved2[4]; /* RPOP Reserved */
u32 suni_tpop_cntrl_daig; /* TPOP Control/Disgnostics */
u32 suni_tpop_pointer_ctrl; /* TPOP Pointer Control */
u32 suni_tpop_sourcer_ctrl; /* TPOP Source Control */
u32 suni_tpop_reserved1[2]; /* TPOP Reserved */
u32 suni_tpop_arb_prtl; /* TPOP Arbitrary Pointer LSB */
u32 suni_tpop_arb_prtm; /* TPOP Arbitrary Pointer MSB */
u32 suni_tpop_reserved2; /* TPOP Reserved */
u32 suni_tpop_path_sig; /* TPOP Path Signal Lable */
u32 suni_tpop_path_status; /* TPOP Path Status */
u32 suni_tpop_reserved3[6]; /* TPOP Reserved */
u32 suni_racp_cs; /* RACP Control/Status */
u32 suni_racp_intr; /* RACP Interrupt Enable/Status */
u32 suni_racp_hdr_pattern; /* RACP Match Header Pattern */
u32 suni_racp_hdr_mask; /* RACP Match Header Mask */
u32 suni_racp_corr_hcs; /* RACP Correctable HCS Error Count */
u32 suni_racp_uncorr_hcs; /* RACP Uncorrectable HCS Error Count */
u32 suni_racp_reserved[10]; /* RACP Reserved */
u32 suni_tacp_control; /* TACP Control */
u32 suni_tacp_idle_hdr_pat; /* TACP Idle Cell Header Pattern */
u32 suni_tacp_idle_pay_pay; /* TACP Idle Cell Payld Octet Pattern */
u32 suni_tacp_reserved[5]; /* TACP Reserved */
u32 suni_reserved3[24]; /* Reserved */
u32 suni_master_test; /* SUNI Master Test */
u32 suni_reserved_test; /* SUNI Reserved for Test */
} IA_SUNI;
SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
/* Reserved (2) */
SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
/* Reserved (14) */
SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
/* Reserved (3) */
SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
/* Reserved (4) */
SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
/* Reserved (2) */
SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
/* Reserved (6) */
SUNI_RACP_CS = 0x140, /* RACP Control/Status */
SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
/* Reserved (10) */
SUNI_TACP_CONTROL = 0x180, /* TACP Control */
SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
/* Reserved (5) */
/* Reserved (24) */
/* FIXME: unused but name conflicts.
* SUNI_MASTER_TEST = 0x200, SUNI Master Test */
SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
};
typedef struct _SUNI_STATS_
{
@ -993,13 +985,11 @@ typedef struct _SUNI_STATS_
u32 racp_uchcs_count; // uncorrectable HCS error count
} IA_SUNI_STATS;
typedef struct iadev_t {
typedef struct iadev_priv {
/*-----base pointers into (i)chipSAR+ address space */
u32 __iomem *phy; /* base pointer into phy(SUNI) */
u32 __iomem *dma; /* base pointer into DMA control
registers */
u32 __iomem *reg; /* base pointer to SAR registers
- Bus Interface Control Regs */
u32 __iomem *phy; /* Base pointer into phy (SUNI). */
u32 __iomem *dma; /* Base pointer into DMA control registers. */
u32 __iomem *reg; /* Base pointer to SAR registers. */
u32 __iomem *seg_reg; /* base pointer to segmentation engine
internal registers */
u32 __iomem *reass_reg; /* base pointer to reassemble engine
@ -1071,14 +1061,14 @@ typedef struct iadev_t {
#define INPH_IA_VCC(v) ((struct ia_vcc *) (v)->dev_data)
/******************* IDT77105 25MB/s PHY DEFINE *****************************/
typedef struct {
u_int mb25_master_ctrl; /* Master control */
u_int mb25_intr_status; /* Interrupt status */
u_int mb25_diag_control; /* Diagnostic control */
u_int mb25_led_hec; /* LED driver and HEC status/control */
u_int mb25_low_byte_counter; /* Low byte counter */
u_int mb25_high_byte_counter; /* High byte counter */
} ia_mb25_t;
enum ia_mb25 {
MB25_MASTER_CTRL = 0x00, /* Master control */
MB25_INTR_STATUS = 0x04, /* Interrupt status */
MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
MB25_LOW_BYTE_COUNTER = 0x10,
MB25_HIGH_BYTE_COUNTER = 0x14
};
/*
* Master Control
@ -1127,122 +1117,121 @@ typedef struct {
#define FE_E3_PHY 0x0090 /* E3 */
/*********************** SUNI_PM7345 PHY DEFINE HERE *********************/
typedef struct _suni_pm7345_t
{
u_int suni_config; /* SUNI Configuration */
u_int suni_intr_enbl; /* SUNI Interrupt Enable */
u_int suni_intr_stat; /* SUNI Interrupt Status */
u_int suni_control; /* SUNI Control */
u_int suni_id_reset; /* SUNI Reset and Identity */
u_int suni_data_link_ctrl;
u_int suni_rboc_conf_intr_enbl;
u_int suni_rboc_stat;
u_int suni_ds3_frm_cfg;
u_int suni_ds3_frm_intr_enbl;
u_int suni_ds3_frm_intr_stat;
u_int suni_ds3_frm_stat;
u_int suni_rfdl_cfg;
u_int suni_rfdl_enbl_stat;
u_int suni_rfdl_stat;
u_int suni_rfdl_data;
u_int suni_pmon_chng;
u_int suni_pmon_intr_enbl_stat;
u_int suni_reserved1[0x13-0x11];
u_int suni_pmon_lcv_evt_cnt_lsb;
u_int suni_pmon_lcv_evt_cnt_msb;
u_int suni_pmon_fbe_evt_cnt_lsb;
u_int suni_pmon_fbe_evt_cnt_msb;
u_int suni_pmon_sez_det_cnt_lsb;
u_int suni_pmon_sez_det_cnt_msb;
u_int suni_pmon_pe_evt_cnt_lsb;
u_int suni_pmon_pe_evt_cnt_msb;
u_int suni_pmon_ppe_evt_cnt_lsb;
u_int suni_pmon_ppe_evt_cnt_msb;
u_int suni_pmon_febe_evt_cnt_lsb;
u_int suni_pmon_febe_evt_cnt_msb;
u_int suni_ds3_tran_cfg;
u_int suni_ds3_tran_diag;
u_int suni_reserved2[0x23-0x21];
u_int suni_xfdl_cfg;
u_int suni_xfdl_intr_st;
u_int suni_xfdl_xmit_data;
u_int suni_xboc_code;
u_int suni_splr_cfg;
u_int suni_splr_intr_en;
u_int suni_splr_intr_st;
u_int suni_splr_status;
u_int suni_splt_cfg;
u_int suni_splt_cntl;
u_int suni_splt_diag_g1;
u_int suni_splt_f1;
u_int suni_cppm_loc_meters;
u_int suni_cppm_chng_of_cppm_perf_meter;
u_int suni_cppm_b1_err_cnt_lsb;
u_int suni_cppm_b1_err_cnt_msb;
u_int suni_cppm_framing_err_cnt_lsb;
u_int suni_cppm_framing_err_cnt_msb;
u_int suni_cppm_febe_cnt_lsb;
u_int suni_cppm_febe_cnt_msb;
u_int suni_cppm_hcs_err_cnt_lsb;
u_int suni_cppm_hcs_err_cnt_msb;
u_int suni_cppm_idle_un_cell_cnt_lsb;
u_int suni_cppm_idle_un_cell_cnt_msb;
u_int suni_cppm_rcv_cell_cnt_lsb;
u_int suni_cppm_rcv_cell_cnt_msb;
u_int suni_cppm_xmit_cell_cnt_lsb;
u_int suni_cppm_xmit_cell_cnt_msb;
u_int suni_rxcp_ctrl;
u_int suni_rxcp_fctrl;
u_int suni_rxcp_intr_en_sts;
u_int suni_rxcp_idle_pat_h1;
u_int suni_rxcp_idle_pat_h2;
u_int suni_rxcp_idle_pat_h3;
u_int suni_rxcp_idle_pat_h4;
u_int suni_rxcp_idle_mask_h1;
u_int suni_rxcp_idle_mask_h2;
u_int suni_rxcp_idle_mask_h3;
u_int suni_rxcp_idle_mask_h4;
u_int suni_rxcp_cell_pat_h1;
u_int suni_rxcp_cell_pat_h2;
u_int suni_rxcp_cell_pat_h3;
u_int suni_rxcp_cell_pat_h4;
u_int suni_rxcp_cell_mask_h1;
u_int suni_rxcp_cell_mask_h2;
u_int suni_rxcp_cell_mask_h3;
u_int suni_rxcp_cell_mask_h4;
u_int suni_rxcp_hcs_cs;
u_int suni_rxcp_lcd_cnt_threshold;
u_int suni_reserved3[0x57-0x54];
u_int suni_txcp_ctrl;
u_int suni_txcp_intr_en_sts;
u_int suni_txcp_idle_pat_h1;
u_int suni_txcp_idle_pat_h2;
u_int suni_txcp_idle_pat_h3;
u_int suni_txcp_idle_pat_h4;
u_int suni_txcp_idle_pat_h5;
u_int suni_txcp_idle_payload;
u_int suni_e3_frm_fram_options;
u_int suni_e3_frm_maint_options;
u_int suni_e3_frm_fram_intr_enbl;
u_int suni_e3_frm_fram_intr_ind_stat;
u_int suni_e3_frm_maint_intr_enbl;
u_int suni_e3_frm_maint_intr_ind;
u_int suni_e3_frm_maint_stat;
u_int suni_reserved4;
u_int suni_e3_tran_fram_options;
u_int suni_e3_tran_stat_diag_options;
u_int suni_e3_tran_bip_8_err_mask;
u_int suni_e3_tran_maint_adapt_options;
u_int suni_ttb_ctrl;
u_int suni_ttb_trail_trace_id_stat;
u_int suni_ttb_ind_addr;
u_int suni_ttb_ind_data;
u_int suni_ttb_exp_payload_type;
u_int suni_ttb_payload_type_ctrl_stat;
u_int suni_pad5[0x7f-0x71];
u_int suni_master_test;
u_int suni_pad6[0xff-0x80];
}suni_pm7345_t;
enum suni_pm7345 {
SUNI_CONFIG = 0x000, /* SUNI Configuration */
SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
SUNI_CONTROL = 0x00c, /* SUNI Control */
SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
SUNI_DATA_LINK_CTRL = 0x014,
SUNI_RBOC_CONF_INTR_ENBL = 0x018,
SUNI_RBOC_STAT = 0x01c,
SUNI_DS3_FRM_CFG = 0x020,
SUNI_DS3_FRM_INTR_ENBL = 0x024,
SUNI_DS3_FRM_INTR_STAT = 0x028,
SUNI_DS3_FRM_STAT = 0x02c,
SUNI_RFDL_CFG = 0x030,
SUNI_RFDL_ENBL_STAT = 0x034,
SUNI_RFDL_STAT = 0x038,
SUNI_RFDL_DATA = 0x03c,
SUNI_PMON_CHNG = 0x040,
SUNI_PMON_INTR_ENBL_STAT = 0x044,
/* SUNI_RESERVED1 (0x13 - 0x11) */
SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
SUNI_DS3_TRAN_CFG = 0x080,
SUNI_DS3_TRAN_DIAG = 0x084,
/* SUNI_RESERVED2 (0x23 - 0x21) */
SUNI_XFDL_CFG = 0x090,
SUNI_XFDL_INTR_ST = 0x094,
SUNI_XFDL_XMIT_DATA = 0x098,
SUNI_XBOC_CODE = 0x09c,
SUNI_SPLR_CFG = 0x0a0,
SUNI_SPLR_INTR_EN = 0x0a4,
SUNI_SPLR_INTR_ST = 0x0a8,
SUNI_SPLR_STATUS = 0x0ac,
SUNI_SPLT_CFG = 0x0b0,
SUNI_SPLT_CNTL = 0x0b4,
SUNI_SPLT_DIAG_G1 = 0x0b8,
SUNI_SPLT_F1 = 0x0bc,
SUNI_CPPM_LOC_METERS = 0x0c0,
SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
SUNI_RXCP_CTRL = 0x100,
SUNI_RXCP_FCTRL = 0x104,
SUNI_RXCP_INTR_EN_STS = 0x108,
SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
SUNI_RXCP_IDLE_PAT_H2 = 0x110,
SUNI_RXCP_IDLE_PAT_H3 = 0x114,
SUNI_RXCP_IDLE_PAT_H4 = 0x118,
SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
SUNI_RXCP_IDLE_MASK_H2 = 0x120,
SUNI_RXCP_IDLE_MASK_H3 = 0x124,
SUNI_RXCP_IDLE_MASK_H4 = 0x128,
SUNI_RXCP_CELL_PAT_H1 = 0x12c,
SUNI_RXCP_CELL_PAT_H2 = 0x130,
SUNI_RXCP_CELL_PAT_H3 = 0x134,
SUNI_RXCP_CELL_PAT_H4 = 0x138,
SUNI_RXCP_CELL_MASK_H1 = 0x13c,
SUNI_RXCP_CELL_MASK_H2 = 0x140,
SUNI_RXCP_CELL_MASK_H3 = 0x144,
SUNI_RXCP_CELL_MASK_H4 = 0x148,
SUNI_RXCP_HCS_CS = 0x14c,
SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
/* SUNI_RESERVED3 (0x57 - 0x54) */
SUNI_TXCP_CTRL = 0x160,
SUNI_TXCP_INTR_EN_STS = 0x164,
SUNI_TXCP_IDLE_PAT_H1 = 0x168,
SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
SUNI_TXCP_IDLE_PAT_H3 = 0x170,
SUNI_TXCP_IDLE_PAT_H4 = 0x174,
SUNI_TXCP_IDLE_PAT_H5 = 0x178,
SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
SUNI_E3_FRM_MAINT_STAT = 0x198,
SUNI_RESERVED4 = 0x19c,
SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
SUNI_TTB_CTRL = 0x1b0,
SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
SUNI_TTB_IND_ADDR = 0x1b8,
SUNI_TTB_IND_DATA = 0x1bc,
SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
/* SUNI_PAD5 (0x7f - 0x71) */
SUNI_MASTER_TEST = 0x200,
/* SUNI_PAD6 (0xff - 0x80) */
};
#define SUNI_PM7345_T suni_pm7345_t
#define SUNI_PM7345 0x20 /* Suni chip type */

17
drivers/base/class.c
View File

@ -47,6 +47,18 @@ static ssize_t class_attr_store(struct kobject *kobj, struct attribute *attr,
return ret;
}
static const void *class_attr_namespace(struct kobject *kobj,
const struct attribute *attr)
{
struct class_attribute *class_attr = to_class_attr(attr);
struct subsys_private *cp = to_subsys_private(kobj);
const void *ns = NULL;
if (class_attr->namespace)
ns = class_attr->namespace(cp->class, class_attr);
return ns;
}
static void class_release(struct kobject *kobj)
{
struct subsys_private *cp = to_subsys_private(kobj);
@ -72,8 +84,9 @@ static const struct kobj_ns_type_operations *class_child_ns_type(struct kobject
}
static const struct sysfs_ops class_sysfs_ops = {
.show = class_attr_show,
.store = class_attr_store,
.show = class_attr_show,
.store = class_attr_store,
.namespace = class_attr_namespace,
};
static struct kobj_type class_ktype = {

13
drivers/bcma/Kconfig
View File

@ -33,6 +33,19 @@ config BCMA_DRIVER_PCI_HOSTMODE
help
PCI core hostmode operation (external PCI bus).
config BCMA_HOST_SOC
bool
depends on BCMA_DRIVER_MIPS
config BCMA_DRIVER_MIPS
bool "BCMA Broadcom MIPS core driver"
depends on BCMA && MIPS
help
Driver for the Broadcom MIPS core attached to Broadcom specific
Advanced Microcontroller Bus.
If unsure, say N
config BCMA_DEBUG
bool "BCMA debugging"
depends on BCMA

2
drivers/bcma/Makefile
View File

@ -2,7 +2,9 @@ bcma-y += main.o scan.o core.o sprom.o
bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
bcma-y += driver_pci.o
bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
bcma-$(CONFIG_BCMA_HOST_PCI) += host_pci.o
bcma-$(CONFIG_BCMA_HOST_SOC) += host_soc.o
obj-$(CONFIG_BCMA) += bcma.o
ccflags-$(CONFIG_BCMA_DEBUG) := -DDEBUG

16
drivers/bcma/bcma_private.h
View File

@ -15,13 +15,29 @@ struct bcma_bus;
/* main.c */
int bcma_bus_register(struct bcma_bus *bus);
void bcma_bus_unregister(struct bcma_bus *bus);
int __init bcma_bus_early_register(struct bcma_bus *bus,
struct bcma_device *core_cc,
struct bcma_device *core_mips);
/* scan.c */
int bcma_bus_scan(struct bcma_bus *bus);
int __init bcma_bus_scan_early(struct bcma_bus *bus,
struct bcma_device_id *match,
struct bcma_device *core);
void bcma_init_bus(struct bcma_bus *bus);
/* sprom.c */
int bcma_sprom_get(struct bcma_bus *bus);
/* driver_chipcommon.c */
#ifdef CONFIG_BCMA_DRIVER_MIPS
void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
#endif /* CONFIG_BCMA_DRIVER_MIPS */
/* driver_chipcommon_pmu.c */
u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
#ifdef CONFIG_BCMA_HOST_PCI
/* host_pci.c */
extern int __init bcma_host_pci_init(void);

2
drivers/bcma/core.c
View File

@ -110,6 +110,8 @@ EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
u32 bcma_core_dma_translation(struct bcma_device *core)
{
switch (core->bus->hosttype) {
case BCMA_HOSTTYPE_SOC:
return 0;
case BCMA_HOSTTYPE_PCI:
if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
return BCMA_DMA_TRANSLATION_DMA64_CMT;

53
drivers/bcma/driver_chipcommon.c
View File

@ -26,6 +26,9 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
u32 leddc_on = 10;
u32 leddc_off = 90;
if (cc->setup_done)
return;
if (cc->core->id.rev >= 11)
cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
@ -52,6 +55,8 @@ void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
(leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
}
cc->setup_done = true;
}
/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
@ -101,3 +106,51 @@ u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
{
return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
}
#ifdef CONFIG_BCMA_DRIVER_MIPS
void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
{
unsigned int irq;
u32 baud_base;
u32 i;
unsigned int ccrev = cc->core->id.rev;
struct bcma_serial_port *ports = cc->serial_ports;
if (ccrev >= 11 && ccrev != 15) {
/* Fixed ALP clock */
baud_base = bcma_pmu_alp_clock(cc);
if (ccrev >= 21) {
/* Turn off UART clock before switching clocksource. */
bcma_cc_write32(cc, BCMA_CC_CORECTL,
bcma_cc_read32(cc, BCMA_CC_CORECTL)
& ~BCMA_CC_CORECTL_UARTCLKEN);
}
/* Set the override bit so we don't divide it */
bcma_cc_write32(cc, BCMA_CC_CORECTL,
bcma_cc_read32(cc, BCMA_CC_CORECTL)
| BCMA_CC_CORECTL_UARTCLK0);
if (ccrev >= 21) {
/* Re-enable the UART clock. */
bcma_cc_write32(cc, BCMA_CC_CORECTL,
bcma_cc_read32(cc, BCMA_CC_CORECTL)
| BCMA_CC_CORECTL_UARTCLKEN);
}
} else {
pr_err("serial not supported on this device ccrev: 0x%x\n",
ccrev);
return;
}
irq = bcma_core_mips_irq(cc->core);
/* Determine the registers of the UARTs */
cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
for (i = 0; i < cc->nr_serial_ports; i++) {
ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
(i * 256);
ports[i].irq = irq;
ports[i].baud_base = baud_base;
ports[i].reg_shift = 0;
}
}
#endif /* CONFIG_BCMA_DRIVER_MIPS */

191
drivers/bcma/driver_chipcommon_pmu.c
View File

@ -11,20 +11,47 @@
#include "bcma_private.h"
#include <linux/bcma/bcma.h>
static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set)
static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
{
u32 value;
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
}
bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
{
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
u32 set)
{
bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set)
{
bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
value &= mask;
value |= set;
bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value);
bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
u32 set)
{
bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
{
@ -83,6 +110,24 @@ void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
}
}
/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
{
struct bcma_bus *bus = cc->core->bus;
u32 val;
val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
if (enable) {
val |= BCMA_CHIPCTL_4331_EXTPA_EN;
if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
} else {
val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
}
bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
}
void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
@ -92,7 +137,7 @@ void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
break;
case 0x4331:
pr_err("Enabling Ext PA lines not implemented\n");
/* BCM4331 workaround is SPROM-related, we put it in sprom.c */
break;
case 43224:
if (bus->chipinfo.rev == 0) {
@ -136,3 +181,129 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
bcma_pmu_swreg_init(cc);
bcma_pmu_workarounds(cc);
}
u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4716:
case 0x4748:
case 47162:
case 0x4313:
case 0x5357:
case 0x4749:
case 53572:
/* always 20Mhz */
return 20000 * 1000;
case 0x5356:
case 0x5300:
/* always 25Mhz */
return 25000 * 1000;
default:
pr_warn("No ALP clock specified for %04X device, "
"pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
}
return BCMA_CC_PMU_ALP_CLOCK;
}
/* Find the output of the "m" pll divider given pll controls that start with
* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
*/
static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
u32 tmp, div, ndiv, p1, p2, fc;
struct bcma_bus *bus = cc->core->bus;
BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
BUG_ON(!m || m > 4);
if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
/* Detect failure in clock setting */
tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
if (tmp & 0x40000)
return 133 * 1000000;
}
tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
BCMA_CC_PPL_MDIV_MASK;
tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
/* Do calculation in Mhz */
fc = bcma_pmu_alp_clock(cc) / 1000000;
fc = (p1 * ndiv * fc) / p2;
/* Return clock in Hertz */
return (fc / div) * 1000000;
}
/* query bus clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
switch (bus->chipinfo.id) {
case 0x4716:
case 0x4748:
case 47162:
return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5356:
return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5357:
case 0x4749:
return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 0x5300:
return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
BCMA_CC_PMU5_MAINPLL_SSB);
case 53572:
return 75000000;
default:
pr_warn("No backplane clock specified for %04X device, "
"pmu rev. %d, using default %d Hz\n",
bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
}
return BCMA_CC_PMU_HT_CLOCK;
}
/* query cpu clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
{
struct bcma_bus *bus = cc->core->bus;
if (bus->chipinfo.id == 53572)
return 300000000;
if (cc->pmu.rev >= 5) {
u32 pll;
switch (bus->chipinfo.id) {
case 0x5356:
pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
break;
case 0x5357:
case 0x4749:
pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
break;
default:
pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
break;
}
/* TODO: if (bus->chipinfo.id == 0x5300)
return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
}
return bcma_pmu_get_clockcontrol(cc);
}

256
drivers/bcma/driver_mips.c Normal file
View File

@ -0,0 +1,256 @@
/*
* Broadcom specific AMBA
* Broadcom MIPS32 74K core driver
*
* Copyright 2009, Broadcom Corporation
* Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
* Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com>
* Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include "bcma_private.h"
#include <linux/bcma/bcma.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>
/* The 47162a0 hangs when reading MIPS DMP registers registers */
static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
{
return dev->bus->chipinfo.id == 47162 && dev->bus->chipinfo.rev == 0 &&
dev->id.id == BCMA_CORE_MIPS_74K;
}
/* The 5357b0 hangs when reading USB20H DMP registers */
static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev)
{
return (dev->bus->chipinfo.id == 0x5357 ||
dev->bus->chipinfo.id == 0x4749) &&
dev->bus->chipinfo.pkg == 11 &&
dev->id.id == BCMA_CORE_USB20_HOST;
}
static inline u32 mips_read32(struct bcma_drv_mips *mcore,
u16 offset)
{
return bcma_read32(mcore->core, offset);
}
static inline void mips_write32(struct bcma_drv_mips *mcore,
u16 offset,
u32 value)
{
bcma_write32(mcore->core, offset, value);
}
static const u32 ipsflag_irq_mask[] = {
0,
BCMA_MIPS_IPSFLAG_IRQ1,
BCMA_MIPS_IPSFLAG_IRQ2,
BCMA_MIPS_IPSFLAG_IRQ3,
BCMA_MIPS_IPSFLAG_IRQ4,
};
static const u32 ipsflag_irq_shift[] = {
0,
BCMA_MIPS_IPSFLAG_IRQ1_SHIFT,
BCMA_MIPS_IPSFLAG_IRQ2_SHIFT,
BCMA_MIPS_IPSFLAG_IRQ3_SHIFT,
BCMA_MIPS_IPSFLAG_IRQ4_SHIFT,
};
static u32 bcma_core_mips_irqflag(struct bcma_device *dev)
{
u32 flag;
if (bcma_core_mips_bcm47162a0_quirk(dev))
return dev->core_index;
if (bcma_core_mips_bcm5357b0_quirk(dev))
return dev->core_index;
flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
return flag & 0x1F;
}
/* Get the MIPS IRQ assignment for a specified device.
* If unassigned, 0 is returned.
*/
unsigned int bcma_core_mips_irq(struct bcma_device *dev)
{
struct bcma_device *mdev = dev->bus->drv_mips.core;
u32 irqflag;
unsigned int irq;
irqflag = bcma_core_mips_irqflag(dev);
for (irq = 1; irq <= 4; irq++)
if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
(1 << irqflag))
return irq;
return 0;
}
EXPORT_SYMBOL(bcma_core_mips_irq);
static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
{
unsigned int oldirq = bcma_core_mips_irq(dev);
struct bcma_bus *bus = dev->bus;
struct bcma_device *mdev = bus->drv_mips.core;
u32 irqflag;
irqflag = bcma_core_mips_irqflag(dev);
BUG_ON(oldirq == 6);
dev->irq = irq + 2;
/* clear the old irq */
if (oldirq == 0)
bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
~(1 << irqflag));
else
bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 0);
/* assign the new one */
if (irq == 0) {
bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
(1 << irqflag));
} else {
u32 oldirqflag = bcma_read32(mdev,
BCMA_MIPS_MIPS74K_INTMASK(irq));
if (oldirqflag) {
struct bcma_device *core;
/* backplane irq line is in use, find out who uses
* it and set user to irq 0
*/
list_for_each_entry_reverse(core, &bus->cores, list) {
if ((1 << bcma_core_mips_irqflag(core)) ==
oldirqflag) {
bcma_core_mips_set_irq(core, 0);
break;
}
}
}
bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq),
1 << irqflag);
}
pr_info("set_irq: core 0x%04x, irq %d => %d\n",
dev->id.id, oldirq + 2, irq + 2);
}
static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
{
int i;
static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
for (i = 0; i <= 6; i++)
printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
printk("\n");
}
static void bcma_core_mips_dump_irq(struct bcma_bus *bus)
{
struct bcma_device *core;
list_for_each_entry_reverse(core, &bus->cores, list) {
bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
}
}
u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
return bcma_pmu_get_clockcpu(&bus->drv_cc);
pr_err("No PMU available, need this to get the cpu clock\n");
return 0;
}
EXPORT_SYMBOL(bcma_cpu_clock);
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
case BCMA_CC_FLASHT_STSER:
case BCMA_CC_FLASHT_ATSER:
pr_err("Serial flash not supported.\n");
break;
case BCMA_CC_FLASHT_PARA:
pr_info("found parallel flash.\n");
bus->drv_cc.pflash.window = 0x1c000000;
bus->drv_cc.pflash.window_size = 0x02000000;
if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
BCMA_CC_FLASH_CFG_DS) == 0)
bus->drv_cc.pflash.buswidth = 1;
else
bus->drv_cc.pflash.buswidth = 2;
break;
default:
pr_err("flash not supported.\n");
}
}
void bcma_core_mips_init(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus;
struct bcma_device *core;
bus = mcore->core->bus;
pr_info("Initializing MIPS core...\n");
if (!mcore->setup_done)
mcore->assigned_irqs = 1;
/* Assign IRQs to all cores on the bus */
list_for_each_entry_reverse(core, &bus->cores, list) {
int mips_irq;
if (core->irq)
continue;
mips_irq = bcma_core_mips_irq(core);
if (mips_irq > 4)
core->irq = 0;
else
core->irq = mips_irq + 2;
if (core->irq > 5)
continue;
switch (core->id.id) {
case BCMA_CORE_PCI:
case BCMA_CORE_PCIE:
case BCMA_CORE_ETHERNET:
case BCMA_CORE_ETHERNET_GBIT:
case BCMA_CORE_MAC_GBIT:
case BCMA_CORE_80211:
case BCMA_CORE_USB20_HOST:
/* These devices get their own IRQ line if available,
* the rest goes on IRQ0
*/
if (mcore->assigned_irqs <= 4)
bcma_core_mips_set_irq(core,
mcore->assigned_irqs++);
break;
}
}
pr_info("IRQ reconfiguration done\n");
bcma_core_mips_dump_irq(bus);
if (mcore->setup_done)
return;
bcma_chipco_serial_init(&bus->drv_cc);
bcma_core_mips_flash_detect(mcore);
mcore->setup_done = true;
}

16
drivers/bcma/driver_pci.c
View File

@ -173,7 +173,7 @@ static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
return false;
#ifdef CONFIG_SSB_DRIVER_PCICORE
if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
return false;
#endif /* CONFIG_SSB_DRIVER_PCICORE */
@ -189,6 +189,9 @@ static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
void bcma_core_pci_init(struct bcma_drv_pci *pc)
{
if (pc->setup_done)
return;
if (bcma_core_pci_is_in_hostmode(pc)) {
#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
bcma_core_pci_hostmode_init(pc);
@ -198,6 +201,8 @@ void bcma_core_pci_init(struct bcma_drv_pci *pc)
} else {
bcma_core_pci_clientmode_init(pc);
}
pc->setup_done = true;
}
int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
@ -205,7 +210,14 @@ int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
{
struct pci_dev *pdev = pc->core->bus->host_pci;
u32 coremask, tmp;
int err;
int err = 0;
if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) {
/* This bcma device is not on a PCI host-bus. So the IRQs are
* not routed through the PCI core.
* So we must not enable routing through the PCI core. */
goto out;
}
err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp);
if (err)

183
drivers/bcma/host_soc.c Normal file
View File

@ -0,0 +1,183 @@
/*
* Broadcom specific AMBA
* System on Chip (SoC) Host
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
#include "bcma_private.h"
#include "scan.h"
#include <linux/bcma/bcma.h>
#include <linux/bcma/bcma_soc.h>
static u8 bcma_host_soc_read8(struct bcma_device *core, u16 offset)
{
return readb(core->io_addr + offset);
}
static u16 bcma_host_soc_read16(struct bcma_device *core, u16 offset)
{
return readw(core->io_addr + offset);
}
static u32 bcma_host_soc_read32(struct bcma_device *core, u16 offset)
{
return readl(core->io_addr + offset);
}
static void bcma_host_soc_write8(struct bcma_device *core, u16 offset,
u8 value)
{
writeb(value, core->io_addr + offset);
}
static void bcma_host_soc_write16(struct bcma_device *core, u16 offset,
u16 value)
{
writew(value, core->io_addr + offset);
}
static void bcma_host_soc_write32(struct bcma_device *core, u16 offset,
u32 value)
{
writel(value, core->io_addr + offset);
}
#ifdef CONFIG_BCMA_BLOCKIO
static void bcma_host_soc_block_read(struct bcma_device *core, void *buffer,
size_t count, u16 offset, u8 reg_width)
{
void __iomem *addr = core->io_addr + offset;
switch (reg_width) {
case sizeof(u8): {
u8 *buf = buffer;
while (count) {
*buf = __raw_readb(addr);
buf++;
count--;
}
break;
}
case sizeof(u16): {
__le16 *buf = buffer;
WARN_ON(count & 1);
while (count) {
*buf = (__force __le16)__raw_readw(addr);
buf++;
count -= 2;
}
break;
}
case sizeof(u32): {
__le32 *buf = buffer;
WARN_ON(count & 3);
while (count) {
*buf = (__force __le32)__raw_readl(addr);
buf++;
count -= 4;
}
break;
}
default:
WARN_ON(1);
}
}
static void bcma_host_soc_block_write(struct bcma_device *core,
const void *buffer,
size_t count, u16 offset, u8 reg_width)
{
void __iomem *addr = core->io_addr + offset;
switch (reg_width) {
case sizeof(u8): {
const u8 *buf = buffer;
while (count) {
__raw_writeb(*buf, addr);
buf++;
count--;
}
break;
}
case sizeof(u16): {
const __le16 *buf = buffer;
WARN_ON(count & 1);
while (count) {
__raw_writew((__force u16)(*buf), addr);
buf++;
count -= 2;
}
break;
}
case sizeof(u32): {
const __le32 *buf = buffer;
WARN_ON(count & 3);
while (count) {
__raw_writel((__force u32)(*buf), addr);
buf++;
count -= 4;
}
break;
}
default:
WARN_ON(1);
}
}
#endif /* CONFIG_BCMA_BLOCKIO */
static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
{
return readl(core->io_wrap + offset);
}
static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
u32 value)
{
writel(value, core->io_wrap + offset);
}
const struct bcma_host_ops bcma_host_soc_ops = {
.read8 = bcma_host_soc_read8,
.read16 = bcma_host_soc_read16,
.read32 = bcma_host_soc_read32,
.write8 = bcma_host_soc_write8,
.write16 = bcma_host_soc_write16,
.write32 = bcma_host_soc_write32,
#ifdef CONFIG_BCMA_BLOCKIO
.block_read = bcma_host_soc_block_read,
.block_write = bcma_host_soc_block_write,
#endif
.aread32 = bcma_host_soc_aread32,
.awrite32 = bcma_host_soc_awrite32,
};
int __init bcma_host_soc_register(struct bcma_soc *soc)
{
struct bcma_bus *bus = &soc->bus;
int err;
/* iomap only first core. We have to read some register on this core
* to scan the bus.
*/
bus->mmio = ioremap_nocache(BCMA_ADDR_BASE, BCMA_CORE_SIZE * 1);
if (!bus->mmio)
return -ENOMEM;
/* Host specific */
bus->hosttype = BCMA_HOSTTYPE_SOC;
bus->ops = &bcma_host_soc_ops;
/* Register */
err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
if (err)
iounmap(bus->mmio);
return err;
}

70
drivers/bcma/main.c
View File

@ -68,6 +68,10 @@ static struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
static void bcma_release_core_dev(struct device *dev)
{
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
if (core->io_addr)
iounmap(core->io_addr);
if (core->io_wrap)
iounmap(core->io_wrap);
kfree(core);
}
@ -82,6 +86,7 @@ static int bcma_register_cores(struct bcma_bus *bus)
case BCMA_CORE_CHIPCOMMON:
case BCMA_CORE_PCI:
case BCMA_CORE_PCIE:
case BCMA_CORE_MIPS_74K:
continue;
}
@ -95,7 +100,10 @@ static int bcma_register_cores(struct bcma_bus *bus)
core->dma_dev = &bus->host_pci->dev;
core->irq = bus->host_pci->irq;
break;
case BCMA_HOSTTYPE_NONE:
case BCMA_HOSTTYPE_SOC:
core->dev.dma_mask = &core->dev.coherent_dma_mask;
core->dma_dev = &core->dev;
break;
case BCMA_HOSTTYPE_SDIO:
break;
}
@ -142,6 +150,13 @@ int bcma_bus_register(struct bcma_bus *bus)
bcma_core_chipcommon_init(&bus->drv_cc);
}
/* Init MIPS core */
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
if (core) {
bus->drv_mips.core = core;
bcma_core_mips_init(&bus->drv_mips);
}
/* Init PCIE core */
core = bcma_find_core(bus, BCMA_CORE_PCIE);
if (core) {
@ -171,6 +186,59 @@ void bcma_bus_unregister(struct bcma_bus *bus)
bcma_unregister_cores(bus);
}
int __init bcma_bus_early_register(struct bcma_bus *bus,
struct bcma_device *core_cc,
struct bcma_device *core_mips)
{
int err;
struct bcma_device *core;
struct bcma_device_id match;
bcma_init_bus(bus);
match.manuf = BCMA_MANUF_BCM;
match.id = BCMA_CORE_CHIPCOMMON;
match.class = BCMA_CL_SIM;
match.rev = BCMA_ANY_REV;
/* Scan for chip common core */
err = bcma_bus_scan_early(bus, &match, core_cc);
if (err) {
pr_err("Failed to scan for common core: %d\n", err);
return -1;
}
match.manuf = BCMA_MANUF_MIPS;
match.id = BCMA_CORE_MIPS_74K;
match.class = BCMA_CL_SIM;
match.rev = BCMA_ANY_REV;
/* Scan for mips core */
err = bcma_bus_scan_early(bus, &match, core_mips);
if (err) {
pr_err("Failed to scan for mips core: %d\n", err);
return -1;
}
/* Init CC core */
core = bcma_find_core(bus, BCMA_CORE_CHIPCOMMON);
if (core) {
bus->drv_cc.core = core;
bcma_core_chipcommon_init(&bus->drv_cc);
}
/* Init MIPS core */
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
if (core) {
bus->drv_mips.core = core;
bcma_core_mips_init(&bus->drv_mips);
}
pr_info("Early bus registered\n");
return 0;
}
int __bcma_driver_register(struct bcma_driver *drv, struct module *owner)
{
drv->drv.name = drv->name;

356
drivers/bcma/scan.c
View File

@ -200,18 +200,162 @@ static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
return addrl;
}
int bcma_bus_scan(struct bcma_bus *bus)
static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus,
u16 index)
{
u32 erombase;
u32 __iomem *eromptr, *eromend;
struct bcma_device *core;
list_for_each_entry(core, &bus->cores, list) {
if (core->core_index == index)
return core;
}
return NULL;
}
static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
struct bcma_device_id *match, int core_num,
struct bcma_device *core)
{
s32 tmp;
u8 i, j;
s32 cia, cib;
u8 ports[2], wrappers[2];
s32 tmp;
u8 i, j;
/* get CIs */
cia = bcma_erom_get_ci(bus, eromptr);
if (cia < 0) {
bcma_erom_push_ent(eromptr);
if (bcma_erom_is_end(bus, eromptr))
return -ESPIPE;
return -EILSEQ;
}
cib = bcma_erom_get_ci(bus, eromptr);
if (cib < 0)
return -EILSEQ;
int err;
/* parse CIs */
core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
if (((core->id.manuf == BCMA_MANUF_ARM) &&
(core->id.id == 0xFFF)) ||
(ports[1] == 0)) {
bcma_erom_skip_component(bus, eromptr);
return -ENXIO;
}
/* check if component is a core at all */
if (wrappers[0] + wrappers[1] == 0) {
/* we could save addrl of the router
if (cid == BCMA_CORE_OOB_ROUTER)
*/
bcma_erom_skip_component(bus, eromptr);
return -ENXIO;
}
if (bcma_erom_is_bridge(bus, eromptr)) {
bcma_erom_skip_component(bus, eromptr);
return -ENXIO;
}
if (bcma_find_core_by_index(bus, core_num)) {
bcma_erom_skip_component(bus, eromptr);
return -ENODEV;
}
if (match && ((match->manuf != BCMA_ANY_MANUF &&
match->manuf != core->id.manuf) ||
(match->id != BCMA_ANY_ID && match->id != core->id.id) ||
(match->rev != BCMA_ANY_REV && match->rev != core->id.rev) ||
(match->class != BCMA_ANY_CLASS && match->class != core->id.class)
)) {
bcma_erom_skip_component(bus, eromptr);
return -ENODEV;
}
/* get & parse master ports */
for (i = 0; i < ports[0]; i++) {
s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
if (mst_port_d < 0)
return -EILSEQ;
}
/* get & parse slave ports */
for (i = 0; i < ports[1]; i++) {
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, eromptr,
SCAN_ADDR_TYPE_SLAVE, i);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: slave port %d "
* "has %d descriptors\n", i, j); */
break;
} else {
if (i == 0 && j == 0)
core->addr = tmp;
}
}
}
/* get & parse master wrappers */
for (i = 0; i < wrappers[0]; i++) {
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, eromptr,
SCAN_ADDR_TYPE_MWRAP, i);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: master wrapper %d "
* "has %d descriptors\n", i, j); */
break;
} else {
if (i == 0 && j == 0)
core->wrap = tmp;
}
}
}
/* get & parse slave wrappers */
for (i = 0; i < wrappers[1]; i++) {
u8 hack = (ports[1] == 1) ? 0 : 1;
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, eromptr,
SCAN_ADDR_TYPE_SWRAP, i + hack);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: master wrapper %d "
* has %d descriptors\n", i, j); */
break;
} else {
if (wrappers[0] == 0 && !i && !j)
core->wrap = tmp;
}
}
}
if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
if (!core->io_addr)
return -ENOMEM;
core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
if (!core->io_wrap) {
iounmap(core->io_addr);
return -ENOMEM;
}
}
return 0;
}
void bcma_init_bus(struct bcma_bus *bus)
{
s32 tmp;
if (bus->init_done)
return;
INIT_LIST_HEAD(&bus->cores);
bus->nr_cores = 0;
@ -222,9 +366,27 @@ int bcma_bus_scan(struct bcma_bus *bus)
bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
bus->init_done = true;
}
int bcma_bus_scan(struct bcma_bus *bus)
{
u32 erombase;
u32 __iomem *eromptr, *eromend;
int err, core_num = 0;
bcma_init_bus(bus);
erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
eromptr = bus->mmio;
if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
if (!eromptr)
return -ENOMEM;
} else {
eromptr = bus->mmio;
}
eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
bcma_scan_switch_core(bus, erombase);
@ -236,125 +398,89 @@ int bcma_bus_scan(struct bcma_bus *bus)
INIT_LIST_HEAD(&core->list);
core->bus = bus;
/* get CIs */
cia = bcma_erom_get_ci(bus, &eromptr);
if (cia < 0) {
bcma_erom_push_ent(&eromptr);
if (bcma_erom_is_end(bus, &eromptr))
break;
err= -EILSEQ;
goto out;
}
cib = bcma_erom_get_ci(bus, &eromptr);
if (cib < 0) {
err= -EILSEQ;
goto out;
}
/* parse CIs */
core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
if (((core->id.manuf == BCMA_MANUF_ARM) &&
(core->id.id == 0xFFF)) ||
(ports[1] == 0)) {
bcma_erom_skip_component(bus, &eromptr);
err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core);
if (err == -ENODEV) {
core_num++;
continue;
}
/* check if component is a core at all */
if (wrappers[0] + wrappers[1] == 0) {
/* we could save addrl of the router
if (cid == BCMA_CORE_OOB_ROUTER)
*/
bcma_erom_skip_component(bus, &eromptr);
} else if (err == -ENXIO)
continue;
}
else if (err == -ESPIPE)
break;
else if (err < 0)
return err;
if (bcma_erom_is_bridge(bus, &eromptr)) {
bcma_erom_skip_component(bus, &eromptr);
continue;
}
/* get & parse master ports */
for (i = 0; i < ports[0]; i++) {
u32 mst_port_d = bcma_erom_get_mst_port(bus, &eromptr);
if (mst_port_d < 0) {
err= -EILSEQ;
goto out;
}
}
/* get & parse slave ports */
for (i = 0; i < ports[1]; i++) {
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, &eromptr,
SCAN_ADDR_TYPE_SLAVE, i);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: slave port %d "
* "has %d descriptors\n", i, j); */
break;
} else {
if (i == 0 && j == 0)
core->addr = tmp;
}
}
}
/* get & parse master wrappers */
for (i = 0; i < wrappers[0]; i++) {
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, &eromptr,
SCAN_ADDR_TYPE_MWRAP, i);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: master wrapper %d "
* "has %d descriptors\n", i, j); */
break;
} else {
if (i == 0 && j == 0)
core->wrap = tmp;
}
}
}
/* get & parse slave wrappers */
for (i = 0; i < wrappers[1]; i++) {
u8 hack = (ports[1] == 1) ? 0 : 1;
for (j = 0; ; j++) {
tmp = bcma_erom_get_addr_desc(bus, &eromptr,
SCAN_ADDR_TYPE_SWRAP, i + hack);
if (tmp < 0) {
/* no more entries for port _i_ */
/* pr_debug("erom: master wrapper %d "
* has %d descriptors\n", i, j); */
break;
} else {
if (wrappers[0] == 0 && !i && !j)
core->wrap = tmp;
}
}
}
core->core_index = core_num++;
bus->nr_cores++;
pr_info("Core %d found: %s "
"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
bus->nr_cores, bcma_device_name(&core->id),
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
core->core_index = bus->nr_cores++;
list_add(&core->list, &bus->cores);
continue;
out:
return err;
}
if (bus->hosttype == BCMA_HOSTTYPE_SOC)
iounmap(eromptr);
return 0;
}
int __init bcma_bus_scan_early(struct bcma_bus *bus,
struct bcma_device_id *match,
struct bcma_device *core)
{
u32 erombase;
u32 __iomem *eromptr, *eromend;
int err = -ENODEV;
int core_num = 0;
erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
if (!eromptr)
return -ENOMEM;
} else {
eromptr = bus->mmio;
}
eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
bcma_scan_switch_core(bus, erombase);
while (eromptr < eromend) {
memset(core, 0, sizeof(*core));
INIT_LIST_HEAD(&core->list);
core->bus = bus;
err = bcma_get_next_core(bus, &eromptr, match, core_num, core);
if (err == -ENODEV) {
core_num++;
continue;
} else if (err == -ENXIO)
continue;
else if (err == -ESPIPE)
break;
else if (err < 0)
return err;
core->core_index = core_num++;
bus->nr_cores++;
pr_info("Core %d found: %s "
"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
core->core_index, bcma_device_name(&core->id),
core->id.manuf, core->id.id, core->id.rev,
core->id.class);
list_add(&core->list, &bus->cores);
err = 0;
break;
}
if (bus->hosttype == BCMA_HOSTTYPE_SOC)
iounmap(eromptr);
return err;
}

15
drivers/bcma/sprom.c
View File

@ -133,6 +133,15 @@ static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
*(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
}
bus->sprom.board_rev = sprom[SPOFF(SSB_SPROM8_BOARDREV)];
bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
}
int bcma_sprom_get(struct bcma_bus *bus)
@ -152,6 +161,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
if (!sprom)
return -ENOMEM;
if (bus->chipinfo.id == 0x4331)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
/* Most cards have SPROM moved by additional offset 0x30 (48 dwords).
* According to brcm80211 this applies to cards with PCIe rev >= 6
* TODO: understand this condition and use it */
@ -159,6 +171,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
BCMA_CC_SPROM_PCIE6;
bcma_sprom_read(bus, offset, sprom);
if (bus->chipinfo.id == 0x4331)
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
err = bcma_sprom_valid(sprom);
if (err)
goto out;

6
drivers/bluetooth/btusb.c
View File

@ -60,6 +60,9 @@ static struct usb_device_id btusb_table[] = {
/* Generic Bluetooth USB device */
{ USB_DEVICE_INFO(0xe0, 0x01, 0x01) },
/* Broadcom SoftSailing reporting vendor specific */
{ USB_DEVICE(0x05ac, 0x21e1) },
/* Apple MacBookPro 7,1 */
{ USB_DEVICE(0x05ac, 0x8213) },
@ -708,8 +711,7 @@ static int btusb_send_frame(struct sk_buff *skb)
break;
case HCI_ACLDATA_PKT:
if (!data->bulk_tx_ep || (hdev->conn_hash.acl_num < 1 &&
hdev->conn_hash.le_num < 1))
if (!data->bulk_tx_ep)
return -ENODEV;
urb = usb_alloc_urb(0, GFP_ATOMIC);

26
drivers/connector/cn_proc.c
View File

@ -205,6 +205,32 @@ void proc_ptrace_connector(struct task_struct *task, int ptrace_id)
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
}
void proc_comm_connector(struct task_struct *task)
{
struct cn_msg *msg;
struct proc_event *ev;
struct timespec ts;
__u8 buffer[CN_PROC_MSG_SIZE];
if (atomic_read(&proc_event_num_listeners) < 1)
return;
msg = (struct cn_msg *)buffer;
ev = (struct proc_event *)msg->data;
get_seq(&msg->seq, &ev->cpu);
ktime_get_ts(&ts); /* get high res monotonic timestamp */
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
ev->what = PROC_EVENT_COMM;
ev->event_data.comm.process_pid = task->pid;
ev->event_data.comm.process_tgid = task->tgid;
get_task_comm(ev->event_data.comm.comm, task);
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
msg->ack = 0; /* not used */
msg->len = sizeof(*ev);
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
}
void proc_exit_connector(struct task_struct *task)
{
struct cn_msg *msg;

11
drivers/infiniband/hw/amso1100/c2.c
View File

@ -800,13 +800,10 @@ static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
/* Loop thru additional data fragments and queue them */
if (skb_shinfo(skb)->nr_frags) {
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
maplen = frag->size;
mapaddr =
pci_map_page(c2dev->pcidev, frag->page,
frag->page_offset, maplen,
PCI_DMA_TODEVICE);
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
maplen = skb_frag_size(frag);
mapaddr = skb_frag_dma_map(&c2dev->pcidev->dev, frag,
0, maplen, DMA_TO_DEVICE);
elem = elem->next;
elem->skb = NULL;
elem->mapaddr = mapaddr;

2
drivers/infiniband/hw/cxgb3/Makefile
View File

@ -1,4 +1,4 @@
ccflags-y := -Idrivers/net/cxgb3
ccflags-y := -Idrivers/net/ethernet/chelsio/cxgb3
obj-$(CONFIG_INFINIBAND_CXGB3) += iw_cxgb3.o

2
drivers/infiniband/hw/cxgb4/Makefile
View File

@ -1,4 +1,4 @@
ccflags-y := -Idrivers/net/cxgb4
ccflags-y := -Idrivers/net/ethernet/chelsio/cxgb4
obj-$(CONFIG_INFINIBAND_CXGB4) += iw_cxgb4.o

3
drivers/infiniband/hw/mlx4/Kconfig
View File

@ -1,6 +1,7 @@
config MLX4_INFINIBAND
tristate "Mellanox ConnectX HCA support"
depends on NETDEVICES && NETDEV_10000 && PCI
depends on NETDEVICES && ETHERNET && PCI
select NET_VENDOR_MELLANOX
select MLX4_CORE
---help---
This driver provides low-level InfiniBand support for

29
drivers/infiniband/hw/nes/nes_nic.c
View File

@ -441,13 +441,13 @@ static int nes_nic_send(struct sk_buff *skb, struct net_device *netdev)
nesnic->tx_skb[nesnic->sq_head] = skb;
for (skb_fragment_index = 0; skb_fragment_index < skb_shinfo(skb)->nr_frags;
skb_fragment_index++) {
bus_address = pci_map_page( nesdev->pcidev,
skb_shinfo(skb)->frags[skb_fragment_index].page,
skb_shinfo(skb)->frags[skb_fragment_index].page_offset,
skb_shinfo(skb)->frags[skb_fragment_index].size,
PCI_DMA_TODEVICE);
skb_frag_t *frag =
&skb_shinfo(skb)->frags[skb_fragment_index];
bus_address = skb_frag_dma_map(&nesdev->pcidev->dev,
frag, 0, skb_frag_size(frag),
DMA_TO_DEVICE);
wqe_fragment_length[wqe_fragment_index] =
cpu_to_le16(skb_shinfo(skb)->frags[skb_fragment_index].size);
cpu_to_le16(skb_frag_size(&skb_shinfo(skb)->frags[skb_fragment_index]));
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_LOW_IDX+(2*wqe_fragment_index),
bus_address);
wqe_fragment_index++;
@ -561,11 +561,12 @@ tso_sq_no_longer_full:
/* Map all the buffers */
for (tso_frag_count=0; tso_frag_count < skb_shinfo(skb)->nr_frags;
tso_frag_count++) {
tso_bus_address[tso_frag_count] = pci_map_page( nesdev->pcidev,
skb_shinfo(skb)->frags[tso_frag_count].page,
skb_shinfo(skb)->frags[tso_frag_count].page_offset,
skb_shinfo(skb)->frags[tso_frag_count].size,
PCI_DMA_TODEVICE);
skb_frag_t *frag =
&skb_shinfo(skb)->frags[tso_frag_count];
tso_bus_address[tso_frag_count] =
skb_frag_dma_map(&nesdev->pcidev->dev,
frag, 0, skb_frag_size(frag),
DMA_TO_DEVICE);
}
tso_frag_index = 0;
@ -636,11 +637,11 @@ tso_sq_no_longer_full:
}
while (wqe_fragment_index < 5) {
wqe_fragment_length[wqe_fragment_index] =
cpu_to_le16(skb_shinfo(skb)->frags[tso_frag_index].size);
cpu_to_le16(skb_frag_size(&skb_shinfo(skb)->frags[tso_frag_index]));
set_wqe_64bit_value(nic_sqe->wqe_words, NES_NIC_SQ_WQE_FRAG0_LOW_IDX+(2*wqe_fragment_index),
(u64)tso_bus_address[tso_frag_index]);
wqe_fragment_index++;
tso_wqe_length += skb_shinfo(skb)->frags[tso_frag_index++].size;
tso_wqe_length += skb_frag_size(&skb_shinfo(skb)->frags[tso_frag_index++]);
if (wqe_fragment_index < 5)
wqe_fragment_length[wqe_fragment_index] = 0;
if (tso_frag_index == tso_frag_count)
@ -1638,7 +1639,7 @@ static const struct net_device_ops nes_netdev_ops = {
.ndo_get_stats = nes_netdev_get_stats,
.ndo_tx_timeout = nes_netdev_tx_timeout,
.ndo_set_mac_address = nes_netdev_set_mac_address,
.ndo_set_multicast_list = nes_netdev_set_multicast_list,
.ndo_set_rx_mode = nes_netdev_set_multicast_list,
.ndo_change_mtu = nes_netdev_change_mtu,
.ndo_validate_addr = eth_validate_addr,
.ndo_fix_features = nes_fix_features,

7
drivers/infiniband/ulp/ipoib/ipoib_cm.c
View File

@ -169,7 +169,7 @@ static struct sk_buff *ipoib_cm_alloc_rx_skb(struct net_device *dev,
goto partial_error;
skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
mapping[i + 1] = ib_dma_map_page(priv->ca, skb_shinfo(skb)->frags[i].page,
mapping[i + 1] = ib_dma_map_page(priv->ca, page,
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (unlikely(ib_dma_mapping_error(priv->ca, mapping[i + 1])))
goto partial_error;
@ -537,12 +537,13 @@ static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
if (length == 0) {
/* don't need this page */
skb_fill_page_desc(toskb, i, frag->page, 0, PAGE_SIZE);
skb_fill_page_desc(toskb, i, skb_frag_page(frag),
0, PAGE_SIZE);
--skb_shinfo(skb)->nr_frags;
} else {
size = min(length, (unsigned) PAGE_SIZE);
frag->size = size;
skb_frag_size_set(frag, size);
skb->data_len += size;
skb->truesize += size;
skb->len += size;

23
drivers/infiniband/ulp/ipoib/ipoib_ib.c
View File

@ -117,7 +117,7 @@ static void ipoib_ud_skb_put_frags(struct ipoib_dev_priv *priv,
size = length - IPOIB_UD_HEAD_SIZE;
frag->size = size;
skb_frag_size_set(frag, size);
skb->data_len += size;
skb->truesize += size;
} else
@ -182,7 +182,7 @@ static struct sk_buff *ipoib_alloc_rx_skb(struct net_device *dev, int id)
goto partial_error;
skb_fill_page_desc(skb, 0, page, 0, PAGE_SIZE);
mapping[1] =
ib_dma_map_page(priv->ca, skb_shinfo(skb)->frags[0].page,
ib_dma_map_page(priv->ca, page,
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (unlikely(ib_dma_mapping_error(priv->ca, mapping[1])))
goto partial_error;
@ -322,9 +322,10 @@ static int ipoib_dma_map_tx(struct ib_device *ca,
off = 0;
for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
mapping[i + off] = ib_dma_map_page(ca, frag->page,
frag->page_offset, frag->size,
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
mapping[i + off] = ib_dma_map_page(ca,
skb_frag_page(frag),
frag->page_offset, skb_frag_size(frag),
DMA_TO_DEVICE);
if (unlikely(ib_dma_mapping_error(ca, mapping[i + off])))
goto partial_error;
@ -333,8 +334,9 @@ static int ipoib_dma_map_tx(struct ib_device *ca,
partial_error:
for (; i > 0; --i) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
ib_dma_unmap_page(ca, mapping[i - !off], frag->size, DMA_TO_DEVICE);
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
ib_dma_unmap_page(ca, mapping[i - !off], skb_frag_size(frag), DMA_TO_DEVICE);
}
if (off)
@ -358,8 +360,9 @@ static void ipoib_dma_unmap_tx(struct ib_device *ca,
off = 0;
for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
ib_dma_unmap_page(ca, mapping[i + off], frag->size,
const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
ib_dma_unmap_page(ca, mapping[i + off], skb_frag_size(frag),
DMA_TO_DEVICE);
}
}
@ -509,7 +512,7 @@ static inline int post_send(struct ipoib_dev_priv *priv,
for (i = 0; i < nr_frags; ++i) {
priv->tx_sge[i + off].addr = mapping[i + off];
priv->tx_sge[i + off].length = frags[i].size;
priv->tx_sge[i + off].length = skb_frag_size(&frags[i]);
}
priv->tx_wr.num_sge = nr_frags + off;
priv->tx_wr.wr_id = wr_id;

2
drivers/infiniband/ulp/ipoib/ipoib_main.c
View File

@ -998,7 +998,7 @@ static const struct net_device_ops ipoib_netdev_ops = {
.ndo_fix_features = ipoib_fix_features,
.ndo_start_xmit = ipoib_start_xmit,
.ndo_tx_timeout = ipoib_timeout,
.ndo_set_multicast_list = ipoib_set_mcast_list,
.ndo_set_rx_mode = ipoib_set_mcast_list,
.ndo_neigh_setup = ipoib_neigh_setup_dev,
};

2
drivers/media/dvb/dvb-core/dvb_net.c
View File

@ -1230,7 +1230,7 @@ static const struct net_device_ops dvb_netdev_ops = {
.ndo_open = dvb_net_open,
.ndo_stop = dvb_net_stop,
.ndo_start_xmit = dvb_net_tx,
.ndo_set_multicast_list = dvb_net_set_multicast_list,
.ndo_set_rx_mode = dvb_net_set_multicast_list,
.ndo_set_mac_address = dvb_net_set_mac,
.ndo_change_mtu = eth_change_mtu,
.ndo_validate_addr = eth_validate_addr,

896
drivers/net/3c501.c
View File

@ -1,896 +0,0 @@
/* 3c501.c: A 3Com 3c501 Ethernet driver for Linux. */
/*
Written 1992,1993,1994 Donald Becker
Copyright 1993 United States Government as represented by the
Director, National Security Agency. This software may be used and
distributed according to the terms of the GNU General Public License,
incorporated herein by reference.
This is a device driver for the 3Com Etherlink 3c501.
Do not purchase this card, even as a joke. It's performance is horrible,
and it breaks in many ways.
The original author may be reached as becker@scyld.com, or C/O
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
Fixed (again!) the missing interrupt locking on TX/RX shifting.
Alan Cox <alan@lxorguk.ukuu.org.uk>
Removed calls to init_etherdev since they are no longer needed, and
cleaned up modularization just a bit. The driver still allows only
the default address for cards when loaded as a module, but that's
really less braindead than anyone using a 3c501 board. :)
19950208 (invid@msen.com)
Added traps for interrupts hitting the window as we clear and TX load
the board. Now getting 150K/second FTP with a 3c501 card. Still playing
with a TX-TX optimisation to see if we can touch 180-200K/second as seems
theoretically maximum.
19950402 Alan Cox <alan@lxorguk.ukuu.org.uk>
Cleaned up for 2.3.x because we broke SMP now.
20000208 Alan Cox <alan@lxorguk.ukuu.org.uk>
Check up pass for 2.5. Nothing significant changed
20021009 Alan Cox <alan@lxorguk.ukuu.org.uk>
Fixed zero fill corner case
20030104 Alan Cox <alan@lxorguk.ukuu.org.uk>
For the avoidance of doubt the "preferred form" of this code is one which
is in an open non patent encumbered format. Where cryptographic key signing
forms part of the process of creating an executable the information
including keys needed to generate an equivalently functional executable
are deemed to be part of the source code.
*/
/**
* DOC: 3c501 Card Notes
*
* Some notes on this thing if you have to hack it. [Alan]
*
* Some documentation is available from 3Com. Due to the boards age
* standard responses when you ask for this will range from 'be serious'
* to 'give it to a museum'. The documentation is incomplete and mostly
* of historical interest anyway.
*
* The basic system is a single buffer which can be used to receive or
* transmit a packet. A third command mode exists when you are setting
* things up.
*
* If it's transmitting it's not receiving and vice versa. In fact the
* time to get the board back into useful state after an operation is
* quite large.
*
* The driver works by keeping the board in receive mode waiting for a
* packet to arrive. When one arrives it is copied out of the buffer
* and delivered to the kernel. The card is reloaded and off we go.
*
* When transmitting lp->txing is set and the card is reset (from
* receive mode) [possibly losing a packet just received] to command
* mode. A packet is loaded and transmit mode triggered. The interrupt
* handler runs different code for transmit interrupts and can handle
* returning to receive mode or retransmissions (yes you have to help
* out with those too).
*
* DOC: Problems
*
* There are a wide variety of undocumented error returns from the card
* and you basically have to kick the board and pray if they turn up. Most
* only occur under extreme load or if you do something the board doesn't
* like (eg touching a register at the wrong time).
*
* The driver is less efficient than it could be. It switches through
* receive mode even if more transmits are queued. If this worries you buy
* a real Ethernet card.
*
* The combination of slow receive restart and no real multicast
* filter makes the board unusable with a kernel compiled for IP
* multicasting in a real multicast environment. That's down to the board,
* but even with no multicast programs running a multicast IP kernel is
* in group 224.0.0.1 and you will therefore be listening to all multicasts.
* One nv conference running over that Ethernet and you can give up.
*
*/
#define DRV_NAME "3c501"
#define DRV_VERSION "2002/10/09"
static const char version[] =
DRV_NAME ".c: " DRV_VERSION " Alan Cox (alan@lxorguk.ukuu.org.uk).\n";
/*
* Braindamage remaining:
* The 3c501 board.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fcntl.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
#include <linux/bitops.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/init.h>
#include "3c501.h"
/*
* The boilerplate probe code.
*/
static int io = 0x280;
static int irq = 5;
static int mem_start;
/**
* el1_probe: - probe for a 3c501
* @dev: The device structure passed in to probe.
*
* This can be called from two places. The network layer will probe using
* a device structure passed in with the probe information completed. For a
* modular driver we use #init_module to fill in our own structure and probe
* for it.
*
* Returns 0 on success. ENXIO if asked not to probe and ENODEV if asked to
* probe and failing to find anything.
*/
struct net_device * __init el1_probe(int unit)
{
struct net_device *dev = alloc_etherdev(sizeof(struct net_local));
static const unsigned ports[] = { 0x280, 0x300, 0};
const unsigned *port;
int err = 0;
if (!dev)
return ERR_PTR(-ENOMEM);
if (unit >= 0) {
sprintf(dev->name, "eth%d", unit);
netdev_boot_setup_check(dev);
io = dev->base_addr;
irq = dev->irq;
mem_start = dev->mem_start & 7;
}
if (io > 0x1ff) { /* Check a single specified location. */
err = el1_probe1(dev, io);
} else if (io != 0) {
err = -ENXIO; /* Don't probe at all. */
} else {
for (port = ports; *port && el1_probe1(dev, *port); port++)
;
if (!*port)
err = -ENODEV;
}
if (err)
goto out;
err = register_netdev(dev);
if (err)
goto out1;
return dev;
out1:
release_region(dev->base_addr, EL1_IO_EXTENT);
out:
free_netdev(dev);
return ERR_PTR(err);
}
static const struct net_device_ops el_netdev_ops = {
.ndo_open = el_open,
.ndo_stop = el1_close,
.ndo_start_xmit = el_start_xmit,
.ndo_tx_timeout = el_timeout,
.ndo_set_multicast_list = set_multicast_list,
.ndo_change_mtu = eth_change_mtu,
.ndo_set_mac_address = eth_mac_addr,
.ndo_validate_addr = eth_validate_addr,
};
/**
* el1_probe1:
* @dev: The device structure to use
* @ioaddr: An I/O address to probe at.
*
* The actual probe. This is iterated over by #el1_probe in order to
* check all the applicable device locations.
*
* Returns 0 for a success, in which case the device is activated,
* EAGAIN if the IRQ is in use by another driver, and ENODEV if the
* board cannot be found.
*/
static int __init el1_probe1(struct net_device *dev, int ioaddr)
{
struct net_local *lp;
const char *mname; /* Vendor name */
unsigned char station_addr[6];
int autoirq = 0;
int i;
/*
* Reserve I/O resource for exclusive use by this driver
*/
if (!request_region(ioaddr, EL1_IO_EXTENT, DRV_NAME))
return -ENODEV;
/*
* Read the station address PROM data from the special port.
*/
for (i = 0; i < 6; i++) {
outw(i, ioaddr + EL1_DATAPTR);
station_addr[i] = inb(ioaddr + EL1_SAPROM);
}
/*
* Check the first three octets of the S.A. for 3Com's prefix, or
* for the Sager NP943 prefix.
*/
if (station_addr[0] == 0x02 && station_addr[1] == 0x60 &&
station_addr[2] == 0x8c)
mname = "3c501";
else if (station_addr[0] == 0x00 && station_addr[1] == 0x80 &&
station_addr[2] == 0xC8)
mname = "NP943";
else {
release_region(ioaddr, EL1_IO_EXTENT);
return -ENODEV;
}
/*
* We auto-IRQ by shutting off the interrupt line and letting it
* float high.
*/
dev->irq = irq;
if (dev->irq < 2) {
unsigned long irq_mask;
irq_mask = probe_irq_on();
inb(RX_STATUS); /* Clear pending interrupts. */
inb(TX_STATUS);
outb(AX_LOOP + 1, AX_CMD);
outb(0x00, AX_CMD);
mdelay(20);
autoirq = probe_irq_off(irq_mask);
if (autoirq == 0) {
pr_warning("%s probe at %#x failed to detect IRQ line.\n",
mname, ioaddr);
release_region(ioaddr, EL1_IO_EXTENT);
return -EAGAIN;
}
}
outb(AX_RESET+AX_LOOP, AX_CMD); /* Loopback mode. */
dev->base_addr = ioaddr;
memcpy(dev->dev_addr, station_addr, ETH_ALEN);
if (mem_start & 0xf)
el_debug = mem_start & 0x7;
if (autoirq)
dev->irq = autoirq;
pr_info("%s: %s EtherLink at %#lx, using %sIRQ %d.\n",
dev->name, mname, dev->base_addr,
autoirq ? "auto":"assigned ", dev->irq);
#ifdef CONFIG_IP_MULTICAST
pr_warning("WARNING: Use of the 3c501 in a multicast kernel is NOT recommended.\n");
#endif
if (el_debug)
pr_debug("%s", version);
lp = netdev_priv(dev);
memset(lp, 0, sizeof(struct net_local));
spin_lock_init(&lp->lock);
/*
* The EL1-specific entries in the device structure.
*/
dev->netdev_ops = &el_netdev_ops;
dev->watchdog_timeo = HZ;
dev->ethtool_ops = &netdev_ethtool_ops;
return 0;
}
/**
* el1_open:
* @dev: device that is being opened
*
* When an ifconfig is issued which changes the device flags to include
* IFF_UP this function is called. It is only called when the change
* occurs, not when the interface remains up. #el1_close will be called
* when it goes down.
*
* Returns 0 for a successful open, or -EAGAIN if someone has run off
* with our interrupt line.
*/
static int el_open(struct net_device *dev)
{
int retval;
int ioaddr = dev->base_addr;
struct net_local *lp = netdev_priv(dev);
unsigned long flags;
if (el_debug > 2)
pr_debug("%s: Doing el_open()...\n", dev->name);
retval = request_irq(dev->irq, el_interrupt, 0, dev->name, dev);
if (retval)
return retval;
spin_lock_irqsave(&lp->lock, flags);
el_reset(dev);
spin_unlock_irqrestore(&lp->lock, flags);
lp->txing = 0; /* Board in RX mode */
outb(AX_RX, AX_CMD); /* Aux control, irq and receive enabled */
netif_start_queue(dev);
return 0;
}
/**
* el_timeout:
* @dev: The 3c501 card that has timed out
*
* Attempt to restart the board. This is basically a mixture of extreme
* violence and prayer
*
*/
static void el_timeout(struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
int ioaddr = dev->base_addr;
if (el_debug)
pr_debug("%s: transmit timed out, txsr %#2x axsr=%02x rxsr=%02x.\n",
dev->name, inb(TX_STATUS),
inb(AX_STATUS), inb(RX_STATUS));
dev->stats.tx_errors++;
outb(TX_NORM, TX_CMD);
outb(RX_NORM, RX_CMD);
outb(AX_OFF, AX_CMD); /* Just trigger a false interrupt. */
outb(AX_RX, AX_CMD); /* Aux control, irq and receive enabled */
lp->txing = 0; /* Ripped back in to RX */
netif_wake_queue(dev);
}
/**
* el_start_xmit:
* @skb: The packet that is queued to be sent
* @dev: The 3c501 card we want to throw it down
*
* Attempt to send a packet to a 3c501 card. There are some interesting
* catches here because the 3c501 is an extremely old and therefore
* stupid piece of technology.
*
* If we are handling an interrupt on the other CPU we cannot load a packet
* as we may still be attempting to retrieve the last RX packet buffer.
*
* When a transmit times out we dump the card into control mode and just
* start again. It happens enough that it isn't worth logging.
*
* We avoid holding the spin locks when doing the packet load to the board.
* The device is very slow, and its DMA mode is even slower. If we held the
* lock while loading 1500 bytes onto the controller we would drop a lot of
* serial port characters. This requires we do extra locking, but we have
* no real choice.
*/
static netdev_tx_t el_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
int ioaddr = dev->base_addr;
unsigned long flags;
/*
* Avoid incoming interrupts between us flipping txing and flipping
* mode as the driver assumes txing is a faithful indicator of card
* state
*/
spin_lock_irqsave(&lp->lock, flags);
/*
* Avoid timer-based retransmission conflicts.
*/
netif_stop_queue(dev);
do {
int len = skb->len;
int pad = 0;
int gp_start;
unsigned char *buf = skb->data;
if (len < ETH_ZLEN)
pad = ETH_ZLEN - len;
gp_start = 0x800 - (len + pad);
lp->tx_pkt_start = gp_start;
lp->collisions = 0;
dev->stats.tx_bytes += skb->len;
/*
* Command mode with status cleared should [in theory]
* mean no more interrupts can be pending on the card.
*/
outb_p(AX_SYS, AX_CMD);
inb_p(RX_STATUS);
inb_p(TX_STATUS);
lp->loading = 1;
lp->txing = 1;
/*
* Turn interrupts back on while we spend a pleasant
* afternoon loading bytes into the board
*/
spin_unlock_irqrestore(&lp->lock, flags);
/* Set rx packet area to 0. */
outw(0x00, RX_BUF_CLR);
/* aim - packet will be loaded into buffer start */
outw(gp_start, GP_LOW);
/* load buffer (usual thing each byte increments the pointer) */
outsb(DATAPORT, buf, len);
if (pad) {
while (pad--) /* Zero fill buffer tail */
outb(0, DATAPORT);
}
/* the board reuses the same register */
outw(gp_start, GP_LOW);
if (lp->loading != 2) {
/* fire ... Trigger xmit. */
outb(AX_XMIT, AX_CMD);
lp->loading = 0;
if (el_debug > 2)
pr_debug(" queued xmit.\n");
dev_kfree_skb(skb);
return NETDEV_TX_OK;
}
/* A receive upset our load, despite our best efforts */
if (el_debug > 2)
pr_debug("%s: burped during tx load.\n", dev->name);
spin_lock_irqsave(&lp->lock, flags);
} while (1);
}
/**
* el_interrupt:
* @irq: Interrupt number
* @dev_id: The 3c501 that burped
*
* Handle the ether interface interrupts. The 3c501 needs a lot more
* hand holding than most cards. In particular we get a transmit interrupt
* with a collision error because the board firmware isn't capable of rewinding
* its own transmit buffer pointers. It can however count to 16 for us.
*
* On the receive side the card is also very dumb. It has no buffering to
* speak of. We simply pull the packet out of its PIO buffer (which is slow)
* and queue it for the kernel. Then we reset the card for the next packet.
*
* We sometimes get surprise interrupts late both because the SMP IRQ delivery
* is message passing and because the card sometimes seems to deliver late. I
* think if it is part way through a receive and the mode is changed it carries
* on receiving and sends us an interrupt. We have to band aid all these cases
* to get a sensible 150kBytes/second performance. Even then you want a small
* TCP window.
*/
static irqreturn_t el_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct net_local *lp;
int ioaddr;
int axsr; /* Aux. status reg. */
ioaddr = dev->base_addr;
lp = netdev_priv(dev);
spin_lock(&lp->lock);
/*
* What happened ?
*/
axsr = inb(AX_STATUS);
/*
* Log it
*/
if (el_debug > 3)
pr_debug("%s: el_interrupt() aux=%#02x\n", dev->name, axsr);
if (lp->loading == 1 && !lp->txing)
pr_warning("%s: Inconsistent state loading while not in tx\n",
dev->name);
if (lp->txing) {
/*
* Board in transmit mode. May be loading. If we are
* loading we shouldn't have got this.
*/
int txsr = inb(TX_STATUS);
if (lp->loading == 1) {
if (el_debug > 2)
pr_debug("%s: Interrupt while loading [txsr=%02x gp=%04x rp=%04x]\n",
dev->name, txsr, inw(GP_LOW), inw(RX_LOW));
/* Force a reload */
lp->loading = 2;
spin_unlock(&lp->lock);
goto out;
}
if (el_debug > 6)
pr_debug("%s: txsr=%02x gp=%04x rp=%04x\n", dev->name,
txsr, inw(GP_LOW), inw(RX_LOW));
if ((axsr & 0x80) && (txsr & TX_READY) == 0) {
/*
* FIXME: is there a logic to whether to keep
* on trying or reset immediately ?
*/
if (el_debug > 1)
pr_debug("%s: Unusual interrupt during Tx, txsr=%02x axsr=%02x gp=%03x rp=%03x.\n",
dev->name, txsr, axsr,
inw(ioaddr + EL1_DATAPTR),
inw(ioaddr + EL1_RXPTR));
lp->txing = 0;
netif_wake_queue(dev);
} else if (txsr & TX_16COLLISIONS) {
/*
* Timed out
*/
if (el_debug)
pr_debug("%s: Transmit failed 16 times, Ethernet jammed?\n", dev->name);
outb(AX_SYS, AX_CMD);
lp->txing = 0;
dev->stats.tx_aborted_errors++;
netif_wake_queue(dev);
} else if (txsr & TX_COLLISION) {
/*
* Retrigger xmit.
*/
if (el_debug > 6)
pr_debug("%s: retransmitting after a collision.\n", dev->name);
/*
* Poor little chip can't reset its own start
* pointer
*/
outb(AX_SYS, AX_CMD);
outw(lp->tx_pkt_start, GP_LOW);
outb(AX_XMIT, AX_CMD);
dev->stats.collisions++;
spin_unlock(&lp->lock);
goto out;
} else {
/*
* It worked.. we will now fall through and receive
*/
dev->stats.tx_packets++;
if (el_debug > 6)
pr_debug("%s: Tx succeeded %s\n", dev->name,
(txsr & TX_RDY) ? "." : "but tx is busy!");
/*
* This is safe the interrupt is atomic WRT itself.
*/
lp->txing = 0;
/* In case more to transmit */
netif_wake_queue(dev);
}
} else {
/*
* In receive mode.
*/
int rxsr = inb(RX_STATUS);
if (el_debug > 5)
pr_debug("%s: rxsr=%02x txsr=%02x rp=%04x\n",
dev->name, rxsr, inb(TX_STATUS), inw(RX_LOW));
/*
* Just reading rx_status fixes most errors.
*/
if (rxsr & RX_MISSED)
dev->stats.rx_missed_errors++;
else if (rxsr & RX_RUNT) {
/* Handled to avoid board lock-up. */
dev->stats.rx_length_errors++;
if (el_debug > 5)
pr_debug("%s: runt.\n", dev->name);
} else if (rxsr & RX_GOOD) {
/*
* Receive worked.
*/
el_receive(dev);
} else {
/*
* Nothing? Something is broken!
*/
if (el_debug > 2)
pr_debug("%s: No packet seen, rxsr=%02x **resetting 3c501***\n",
dev->name, rxsr);
el_reset(dev);
}
}
/*
* Move into receive mode
*/
outb(AX_RX, AX_CMD);
outw(0x00, RX_BUF_CLR);
inb(RX_STATUS); /* Be certain that interrupts are cleared. */
inb(TX_STATUS);
spin_unlock(&lp->lock);
out:
return IRQ_HANDLED;
}
/**
* el_receive:
* @dev: Device to pull the packets from
*
* We have a good packet. Well, not really "good", just mostly not broken.
* We must check everything to see if it is good. In particular we occasionally
* get wild packet sizes from the card. If the packet seems sane we PIO it
* off the card and queue it for the protocol layers.
*/
static void el_receive(struct net_device *dev)
{
int ioaddr = dev->base_addr;
int pkt_len;
struct sk_buff *skb;
pkt_len = inw(RX_LOW);
if (el_debug > 4)
pr_debug(" el_receive %d.\n", pkt_len);
if (pkt_len < 60 || pkt_len > 1536) {
if (el_debug)
pr_debug("%s: bogus packet, length=%d\n",
dev->name, pkt_len);
dev->stats.rx_over_errors++;
return;
}
/*
* Command mode so we can empty the buffer
*/
outb(AX_SYS, AX_CMD);
skb = dev_alloc_skb(pkt_len+2);
/*
* Start of frame
*/
outw(0x00, GP_LOW);
if (skb == NULL) {
pr_info("%s: Memory squeeze, dropping packet.\n", dev->name);
dev->stats.rx_dropped++;
return;
} else {
skb_reserve(skb, 2); /* Force 16 byte alignment */
/*
* The read increments through the bytes. The interrupt
* handler will fix the pointer when it returns to
* receive mode.
*/
insb(DATAPORT, skb_put(skb, pkt_len), pkt_len);
skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb);
dev->stats.rx_packets++;
dev->stats.rx_bytes += pkt_len;
}
}
/**
* el_reset: Reset a 3c501 card
* @dev: The 3c501 card about to get zapped
*
* Even resetting a 3c501 isn't simple. When you activate reset it loses all
* its configuration. You must hold the lock when doing this. The function
* cannot take the lock itself as it is callable from the irq handler.
*/
static void el_reset(struct net_device *dev)
{
struct net_local *lp = netdev_priv(dev);
int ioaddr = dev->base_addr;
if (el_debug > 2)
pr_info("3c501 reset...\n");
outb(AX_RESET, AX_CMD); /* Reset the chip */
/* Aux control, irq and loopback enabled */
outb(AX_LOOP, AX_CMD);
{
int i;
for (i = 0; i < 6; i++) /* Set the station address. */
outb(dev->dev_addr[i], ioaddr + i);
}
outw(0, RX_BUF_CLR); /* Set rx packet area to 0. */
outb(TX_NORM, TX_CMD); /* tx irq on done, collision */
outb(RX_NORM, RX_CMD); /* Set Rx commands. */
inb(RX_STATUS); /* Clear status. */
inb(TX_STATUS);
lp->txing = 0;
}
/**
* el1_close:
* @dev: 3c501 card to shut down
*
* Close a 3c501 card. The IFF_UP flag has been cleared by the user via
* the SIOCSIFFLAGS ioctl. We stop any further transmissions being queued,
* and then disable the interrupts. Finally we reset the chip. The effects
* of the rest will be cleaned up by #el1_open. Always returns 0 indicating
* a success.
*/
static int el1_close(struct net_device *dev)
{
int ioaddr = dev->base_addr;
if (el_debug > 2)
pr_info("%s: Shutting down Ethernet card at %#x.\n",
dev->name, ioaddr);
netif_stop_queue(dev);
/*
* Free and disable the IRQ.
*/
free_irq(dev->irq, dev);
outb(AX_RESET, AX_CMD); /* Reset the chip */
return 0;
}
/**
* set_multicast_list:
* @dev: The device to adjust
*
* Set or clear the multicast filter for this adaptor to use the best-effort
* filtering supported. The 3c501 supports only three modes of filtering.
* It always receives broadcasts and packets for itself. You can choose to
* optionally receive all packets, or all multicast packets on top of this.
*/
static void set_multicast_list(struct net_device *dev)
{
int ioaddr = dev->base_addr;
if (dev->flags & IFF_PROMISC) {
outb(RX_PROM, RX_CMD);
inb(RX_STATUS);
} else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
/* Multicast or all multicast is the same */
outb(RX_MULT, RX_CMD);
inb(RX_STATUS); /* Clear status. */
} else {
outb(RX_NORM, RX_CMD);
inb(RX_STATUS);
}
}
static void netdev_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strcpy(info->driver, DRV_NAME);
strcpy(info->version, DRV_VERSION);
sprintf(info->bus_info, "ISA 0x%lx", dev->base_addr);
}
static u32 netdev_get_msglevel(struct net_device *dev)
{
return debug;
}
static void netdev_set_msglevel(struct net_device *dev, u32 level)
{
debug = level;
}
static const struct ethtool_ops netdev_ethtool_ops = {
.get_drvinfo = netdev_get_drvinfo,
.get_msglevel = netdev_get_msglevel,
.set_msglevel = netdev_set_msglevel,
};
#ifdef MODULE
static struct net_device *dev_3c501;
module_param(io, int, 0);
module_param(irq, int, 0);
MODULE_PARM_DESC(io, "EtherLink I/O base address");
MODULE_PARM_DESC(irq, "EtherLink IRQ number");
/**
* init_module:
*
* When the driver is loaded as a module this function is called. We fake up
* a device structure with the base I/O and interrupt set as if it were being
* called from Space.c. This minimises the extra code that would otherwise
* be required.
*
* Returns 0 for success or -EIO if a card is not found. Returning an error
* here also causes the module to be unloaded
*/
int __init init_module(void)
{
dev_3c501 = el1_probe(-1);
if (IS_ERR(dev_3c501))
return PTR_ERR(dev_3c501);
return 0;
}
/**
* cleanup_module:
*
* The module is being unloaded. We unhook our network device from the system
* and then free up the resources we took when the card was found.
*/
void __exit cleanup_module(void)
{
struct net_device *dev = dev_3c501;
unregister_netdev(dev);
release_region(dev->base_addr, EL1_IO_EXTENT);
free_netdev(dev);
}
#endif /* MODULE */
MODULE_AUTHOR("Donald Becker, Alan Cox");
MODULE_DESCRIPTION("Support for the ancient 3Com 3c501 ethernet card");
MODULE_LICENSE("GPL");

778
drivers/net/3c503.c
View File

@ -1,778 +0,0 @@
/* 3c503.c: A shared-memory NS8390 ethernet driver for linux. */
/*
Written 1992-94 by Donald Becker.
Copyright 1993 United States Government as represented by the
Director, National Security Agency. This software may be used and
distributed according to the terms of the GNU General Public License,
incorporated herein by reference.
The author may be reached as becker@scyld.com, or C/O
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
This driver should work with the 3c503 and 3c503/16. It should be used
in shared memory mode for best performance, although it may also work
in programmed-I/O mode.
Sources:
EtherLink II Technical Reference Manual,
EtherLink II/16 Technical Reference Manual Supplement,
3Com Corporation, 5400 Bayfront Plaza, Santa Clara CA 95052-8145
The Crynwr 3c503 packet driver.
Changelog:
Paul Gortmaker : add support for the 2nd 8kB of RAM on 16 bit cards.
Paul Gortmaker : multiple card support for module users.
rjohnson@analogic.com : Fix up PIO interface for efficient operation.
Jeff Garzik : ethtool support
*/
#define DRV_NAME "3c503"
#define DRV_VERSION "1.10a"
#define DRV_RELDATE "11/17/2001"
static const char version[] =
DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Donald Becker (becker@scyld.com)\n";
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ethtool.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/byteorder.h>
#include "8390.h"
#include "3c503.h"
#define WRD_COUNT 4
static int el2_pio_probe(struct net_device *dev);
static int el2_probe1(struct net_device *dev, int ioaddr);
/* A zero-terminated list of I/O addresses to be probed in PIO mode. */
static unsigned int netcard_portlist[] __initdata =
{ 0x300,0x310,0x330,0x350,0x250,0x280,0x2a0,0x2e0,0};
#define EL2_IO_EXTENT 16
static int el2_open(struct net_device *dev);
static int el2_close(struct net_device *dev);
static void el2_reset_8390(struct net_device *dev);
static void el2_init_card(struct net_device *dev);
static void el2_block_output(struct net_device *dev, int count,
const unsigned char *buf, int start_page);
static void el2_block_input(struct net_device *dev, int count, struct sk_buff *skb,
int ring_offset);
static void el2_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr,
int ring_page);
static const struct ethtool_ops netdev_ethtool_ops;
/* This routine probes for a memory-mapped 3c503 board by looking for
the "location register" at the end of the jumpered boot PROM space.
This works even if a PROM isn't there.
If the ethercard isn't found there is an optional probe for
ethercard jumpered to programmed-I/O mode.
*/
static int __init do_el2_probe(struct net_device *dev)
{
int *addr, addrs[] = { 0xddffe, 0xd9ffe, 0xcdffe, 0xc9ffe, 0};
int base_addr = dev->base_addr;
int irq = dev->irq;
if (base_addr > 0x1ff) /* Check a single specified location. */
return el2_probe1(dev, base_addr);
else if (base_addr != 0) /* Don't probe at all. */
return -ENXIO;
for (addr = addrs; *addr; addr++) {
void __iomem *p = ioremap(*addr, 1);
unsigned base_bits;
int i;
if (!p)
continue;
base_bits = readb(p);
iounmap(p);
i = ffs(base_bits) - 1;
if (i == -1 || base_bits != (1 << i))
continue;
if (el2_probe1(dev, netcard_portlist[i]) == 0)
return 0;
dev->irq = irq;
}
#if ! defined(no_probe_nonshared_memory)
return el2_pio_probe(dev);
#else
return -ENODEV;
#endif
}
/* Try all of the locations that aren't obviously empty. This touches
a lot of locations, and is much riskier than the code above. */
static int __init
el2_pio_probe(struct net_device *dev)
{
int i;
int base_addr = dev->base_addr;
int irq = dev->irq;
if (base_addr > 0x1ff) /* Check a single specified location. */
return el2_probe1(dev, base_addr);
else if (base_addr != 0) /* Don't probe at all. */
return -ENXIO;
for (i = 0; netcard_portlist[i]; i++) {
if (el2_probe1(dev, netcard_portlist[i]) == 0)
return 0;
dev->irq = irq;
}
return -ENODEV;
}
#ifndef MODULE
struct net_device * __init el2_probe(int unit)
{
struct net_device *dev = alloc_eip_netdev();
int err;
if (!dev)
return ERR_PTR(-ENOMEM);
sprintf(dev->name, "eth%d", unit);
netdev_boot_setup_check(dev);
err = do_el2_probe(dev);
if (err)
goto out;
return dev;
out:
free_netdev(dev);
return ERR_PTR(err);
}
#endif
static const struct net_device_ops el2_netdev_ops = {
.ndo_open = el2_open,
.ndo_stop = el2_close,
.ndo_start_xmit = eip_start_xmit,
.ndo_tx_timeout = eip_tx_timeout,
.ndo_get_stats = eip_get_stats,
.ndo_set_multicast_list = eip_set_multicast_list,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = eth_mac_addr,
.ndo_change_mtu = eth_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = eip_poll,
#endif
};
/* Probe for the Etherlink II card at I/O port base IOADDR,
returning non-zero on success. If found, set the station
address and memory parameters in DEVICE. */
static int __init
el2_probe1(struct net_device *dev, int ioaddr)
{
int i, iobase_reg, membase_reg, saved_406, wordlength, retval;
static unsigned version_printed;
unsigned long vendor_id;
if (!request_region(ioaddr, EL2_IO_EXTENT, DRV_NAME))
return -EBUSY;
if (!request_region(ioaddr + 0x400, 8, DRV_NAME)) {
retval = -EBUSY;
goto out;
}
/* Reset and/or avoid any lurking NE2000 */
if (inb(ioaddr + 0x408) == 0xff) {
mdelay(1);
retval = -ENODEV;
goto out1;
}
/* We verify that it's a 3C503 board by checking the first three octets
of its ethernet address. */
iobase_reg = inb(ioaddr+0x403);
membase_reg = inb(ioaddr+0x404);
/* ASIC location registers should be 0 or have only a single bit set. */
if ((iobase_reg & (iobase_reg - 1)) ||
(membase_reg & (membase_reg - 1))) {
retval = -ENODEV;
goto out1;
}
saved_406 = inb_p(ioaddr + 0x406);
outb_p(ECNTRL_RESET|ECNTRL_THIN, ioaddr + 0x406); /* Reset it... */
outb_p(ECNTRL_THIN, ioaddr + 0x406);
/* Map the station addr PROM into the lower I/O ports. We now check
for both the old and new 3Com prefix */
outb(ECNTRL_SAPROM|ECNTRL_THIN, ioaddr + 0x406);
vendor_id = inb(ioaddr)*0x10000 + inb(ioaddr + 1)*0x100 + inb(ioaddr + 2);
if ((vendor_id != OLD_3COM_ID) && (vendor_id != NEW_3COM_ID)) {
/* Restore the register we frobbed. */
outb(saved_406, ioaddr + 0x406);
retval = -ENODEV;
goto out1;
}
if (ei_debug && version_printed++ == 0)
pr_debug("%s", version);
dev->base_addr = ioaddr;
pr_info("%s: 3c503 at i/o base %#3x, node ", dev->name, ioaddr);
/* Retrieve and print the ethernet address. */
for (i = 0; i < 6; i++)
dev->dev_addr[i] = inb(ioaddr + i);
pr_cont("%pM", dev->dev_addr);
/* Map the 8390 back into the window. */
outb(ECNTRL_THIN, ioaddr + 0x406);
/* Check for EL2/16 as described in tech. man. */
outb_p(E8390_PAGE0, ioaddr + E8390_CMD);
outb_p(0, ioaddr + EN0_DCFG);
outb_p(E8390_PAGE2, ioaddr + E8390_CMD);
wordlength = inb_p(ioaddr + EN0_DCFG) & ENDCFG_WTS;
outb_p(E8390_PAGE0, ioaddr + E8390_CMD);
/* Probe for, turn on and clear the board's shared memory. */
if (ei_debug > 2)
pr_cont(" memory jumpers %2.2x ", membase_reg);
outb(EGACFR_NORM, ioaddr + 0x405); /* Enable RAM */
/* This should be probed for (or set via an ioctl()) at run-time.
Right now we use a sleazy hack to pass in the interface number
at boot-time via the low bits of the mem_end field. That value is
unused, and the low bits would be discarded even if it was used. */
#if defined(EI8390_THICK) || defined(EL2_AUI)
ei_status.interface_num = 1;
#else
ei_status.interface_num = dev->mem_end & 0xf;
#endif
pr_cont(", using %sternal xcvr.\n", ei_status.interface_num == 0 ? "in" : "ex");
if ((membase_reg & 0xf0) == 0) {
dev->mem_start = 0;
ei_status.name = "3c503-PIO";
ei_status.mem = NULL;
} else {
dev->mem_start = ((membase_reg & 0xc0) ? 0xD8000 : 0xC8000) +
((membase_reg & 0xA0) ? 0x4000 : 0);
#define EL2_MEMSIZE (EL2_MB1_STOP_PG - EL2_MB1_START_PG)*256
ei_status.mem = ioremap(dev->mem_start, EL2_MEMSIZE);
#ifdef EL2MEMTEST
/* This has never found an error, but someone might care.
Note that it only tests the 2nd 8kB on 16kB 3c503/16
cards between card addr. 0x2000 and 0x3fff. */
{ /* Check the card's memory. */
void __iomem *mem_base = ei_status.mem;
unsigned int test_val = 0xbbadf00d;
writel(0xba5eba5e, mem_base);
for (i = sizeof(test_val); i < EL2_MEMSIZE; i+=sizeof(test_val)) {
writel(test_val, mem_base + i);
if (readl(mem_base) != 0xba5eba5e ||
readl(mem_base + i) != test_val) {
pr_warning("3c503: memory failure or memory address conflict.\n");
dev->mem_start = 0;
ei_status.name = "3c503-PIO";
iounmap(mem_base);
ei_status.mem = NULL;
break;
}
test_val += 0x55555555;
writel(0, mem_base + i);
}
}
#endif /* EL2MEMTEST */
if (dev->mem_start)
dev->mem_end = dev->mem_start + EL2_MEMSIZE;
if (wordlength) { /* No Tx pages to skip over to get to Rx */
ei_status.priv = 0;
ei_status.name = "3c503/16";
} else {
ei_status.priv = TX_PAGES * 256;
ei_status.name = "3c503";
}
}
/*
Divide up the memory on the card. This is the same regardless of
whether shared-mem or PIO is used. For 16 bit cards (16kB RAM),
we use the entire 8k of bank1 for an Rx ring. We only use 3k
of the bank0 for 2 full size Tx packet slots. For 8 bit cards,
(8kB RAM) we use 3kB of bank1 for two Tx slots, and the remaining
5kB for an Rx ring. */
if (wordlength) {
ei_status.tx_start_page = EL2_MB0_START_PG;
ei_status.rx_start_page = EL2_MB1_START_PG;
} else {
ei_status.tx_start_page = EL2_MB1_START_PG;
ei_status.rx_start_page = EL2_MB1_START_PG + TX_PAGES;
}
/* Finish setting the board's parameters. */
ei_status.stop_page = EL2_MB1_STOP_PG;
ei_status.word16 = wordlength;
ei_status.reset_8390 = el2_reset_8390;
ei_status.get_8390_hdr = el2_get_8390_hdr;
ei_status.block_input = el2_block_input;
ei_status.block_output = el2_block_output;
if (dev->irq == 2)
dev->irq = 9;
else if (dev->irq > 5 && dev->irq != 9) {
pr_warning("3c503: configured interrupt %d invalid, will use autoIRQ.\n",
dev->irq);
dev->irq = 0;
}
ei_status.saved_irq = dev->irq;
dev->netdev_ops = &el2_netdev_ops;
dev->ethtool_ops = &netdev_ethtool_ops;
retval = register_netdev(dev);
if (retval)
goto out1;
if (dev->mem_start)
pr_info("%s: %s - %dkB RAM, 8kB shared mem window at %#6lx-%#6lx.\n",
dev->name, ei_status.name, (wordlength+1)<<3,
dev->mem_start, dev->mem_end-1);
else
{
ei_status.tx_start_page = EL2_MB1_START_PG;
ei_status.rx_start_page = EL2_MB1_START_PG + TX_PAGES;
pr_info("%s: %s, %dkB RAM, using programmed I/O (REJUMPER for SHARED MEMORY).\n",
dev->name, ei_status.name, (wordlength+1)<<3);
}
release_region(ioaddr + 0x400, 8);
return 0;
out1:
release_region(ioaddr + 0x400, 8);
out:
release_region(ioaddr, EL2_IO_EXTENT);
return retval;
}
static irqreturn_t el2_probe_interrupt(int irq, void *seen)
{
*(bool *)seen = true;
return IRQ_HANDLED;
}
static int
el2_open(struct net_device *dev)
{
int retval;
if (dev->irq < 2) {
static const int irqlist[] = {5, 9, 3, 4, 0};
const int *irqp = irqlist;
outb(EGACFR_NORM, E33G_GACFR); /* Enable RAM and interrupts. */
do {
bool seen;
retval = request_irq(*irqp, el2_probe_interrupt, 0,
dev->name, &seen);
if (retval == -EBUSY)
continue;
if (retval < 0)
goto err_disable;
/* Twinkle the interrupt, and check if it's seen. */
seen = false;
smp_wmb();
outb_p(0x04 << ((*irqp == 9) ? 2 : *irqp), E33G_IDCFR);
outb_p(0x00, E33G_IDCFR);
msleep(1);
free_irq(*irqp, &seen);
if (!seen)
continue;
retval = request_irq(dev->irq = *irqp, eip_interrupt, 0,
dev->name, dev);
if (retval == -EBUSY)
continue;
if (retval < 0)
goto err_disable;
break;
} while (*++irqp);
if (*irqp == 0) {
err_disable:
outb(EGACFR_IRQOFF, E33G_GACFR); /* disable interrupts. */
return -EAGAIN;
}
} else {
if ((retval = request_irq(dev->irq, eip_interrupt, 0, dev->name, dev))) {
return retval;
}
}
el2_init_card(dev);
eip_open(dev);
return 0;
}
static int
el2_close(struct net_device *dev)
{
free_irq(dev->irq, dev);
dev->irq = ei_status.saved_irq;
outb(EGACFR_IRQOFF, E33G_GACFR); /* disable interrupts. */
eip_close(dev);
return 0;
}
/* This is called whenever we have a unrecoverable failure:
transmit timeout
Bad ring buffer packet header
*/
static void
el2_reset_8390(struct net_device *dev)
{
if (ei_debug > 1) {
pr_debug("%s: Resetting the 3c503 board...", dev->name);
pr_cont(" %#lx=%#02x %#lx=%#02x %#lx=%#02x...", E33G_IDCFR, inb(E33G_IDCFR),
E33G_CNTRL, inb(E33G_CNTRL), E33G_GACFR, inb(E33G_GACFR));
}
outb_p(ECNTRL_RESET|ECNTRL_THIN, E33G_CNTRL);
ei_status.txing = 0;
outb_p(ei_status.interface_num==0 ? ECNTRL_THIN : ECNTRL_AUI, E33G_CNTRL);
el2_init_card(dev);
if (ei_debug > 1)
pr_cont("done\n");
}
/* Initialize the 3c503 GA registers after a reset. */
static void
el2_init_card(struct net_device *dev)
{
/* Unmap the station PROM and select the DIX or BNC connector. */
outb_p(ei_status.interface_num==0 ? ECNTRL_THIN : ECNTRL_AUI, E33G_CNTRL);
/* Set ASIC copy of rx's first and last+1 buffer pages */
/* These must be the same as in the 8390. */
outb(ei_status.rx_start_page, E33G_STARTPG);
outb(ei_status.stop_page, E33G_STOPPG);
/* Point the vector pointer registers somewhere ?harmless?. */
outb(0xff, E33G_VP2); /* Point at the ROM restart location 0xffff0 */
outb(0xff, E33G_VP1);
outb(0x00, E33G_VP0);
/* Turn off all interrupts until we're opened. */
outb_p(0x00, dev->base_addr + EN0_IMR);
/* Enable IRQs iff started. */
outb(EGACFR_NORM, E33G_GACFR);
/* Set the interrupt line. */
outb_p((0x04 << (dev->irq == 9 ? 2 : dev->irq)), E33G_IDCFR);
outb_p((WRD_COUNT << 1), E33G_DRQCNT); /* Set burst size to 8 */
outb_p(0x20, E33G_DMAAH); /* Put a valid addr in the GA DMA */
outb_p(0x00, E33G_DMAAL);
return; /* We always succeed */
}
/*
* Either use the shared memory (if enabled on the board) or put the packet
* out through the ASIC FIFO.
*/
static void
el2_block_output(struct net_device *dev, int count,
const unsigned char *buf, int start_page)
{
unsigned short int *wrd;
int boguscount; /* timeout counter */
unsigned short word; /* temporary for better machine code */
void __iomem *base = ei_status.mem;
if (ei_status.word16) /* Tx packets go into bank 0 on EL2/16 card */
outb(EGACFR_RSEL|EGACFR_TCM, E33G_GACFR);
else
outb(EGACFR_NORM, E33G_GACFR);
if (base) { /* Shared memory transfer */
memcpy_toio(base + ((start_page - ei_status.tx_start_page) << 8),
buf, count);
outb(EGACFR_NORM, E33G_GACFR); /* Back to bank1 in case on bank0 */
return;
}
/*
* No shared memory, put the packet out the other way.
* Set up then start the internal memory transfer to Tx Start Page
*/
word = (unsigned short)start_page;
outb(word&0xFF, E33G_DMAAH);
outb(word>>8, E33G_DMAAL);
outb_p((ei_status.interface_num ? ECNTRL_AUI : ECNTRL_THIN ) | ECNTRL_OUTPUT
| ECNTRL_START, E33G_CNTRL);
/*
* Here I am going to write data to the FIFO as quickly as possible.
* Note that E33G_FIFOH is defined incorrectly. It is really
* E33G_FIFOL, the lowest port address for both the byte and
* word write. Variable 'count' is NOT checked. Caller must supply a
* valid count. Note that I may write a harmless extra byte to the
* 8390 if the byte-count was not even.
*/
wrd = (unsigned short int *) buf;
count = (count + 1) >> 1;
for(;;)
{
boguscount = 0x1000;
while ((inb(E33G_STATUS) & ESTAT_DPRDY) == 0)
{
if(!boguscount--)
{
pr_notice("%s: FIFO blocked in el2_block_output.\n", dev->name);
el2_reset_8390(dev);
goto blocked;
}
}
if(count > WRD_COUNT)
{
outsw(E33G_FIFOH, wrd, WRD_COUNT);
wrd += WRD_COUNT;
count -= WRD_COUNT;
}
else
{
outsw(E33G_FIFOH, wrd, count);
break;
}
}
blocked:;
outb_p(ei_status.interface_num==0 ? ECNTRL_THIN : ECNTRL_AUI, E33G_CNTRL);
}
/* Read the 4 byte, page aligned 8390 specific header. */
static void
el2_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_page)
{
int boguscount;
void __iomem *base = ei_status.mem;
unsigned short word;
if (base) { /* Use the shared memory. */
void __iomem *hdr_start = base + ((ring_page - EL2_MB1_START_PG)<<8);
memcpy_fromio(hdr, hdr_start, sizeof(struct e8390_pkt_hdr));
hdr->count = le16_to_cpu(hdr->count);
return;
}
/*
* No shared memory, use programmed I/O.
*/
word = (unsigned short)ring_page;
outb(word&0xFF, E33G_DMAAH);
outb(word>>8, E33G_DMAAL);
outb_p((ei_status.interface_num == 0 ? ECNTRL_THIN : ECNTRL_AUI) | ECNTRL_INPUT
| ECNTRL_START, E33G_CNTRL);
boguscount = 0x1000;
while ((inb(E33G_STATUS) & ESTAT_DPRDY) == 0)
{
if(!boguscount--)
{
pr_notice("%s: FIFO blocked in el2_get_8390_hdr.\n", dev->name);
memset(hdr, 0x00, sizeof(struct e8390_pkt_hdr));
el2_reset_8390(dev);
goto blocked;
}
}
insw(E33G_FIFOH, hdr, (sizeof(struct e8390_pkt_hdr))>> 1);
blocked:;
outb_p(ei_status.interface_num == 0 ? ECNTRL_THIN : ECNTRL_AUI, E33G_CNTRL);
}
static void
el2_block_input(struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
{
int boguscount = 0;
void __iomem *base = ei_status.mem;
unsigned short int *buf;
unsigned short word;
/* Maybe enable shared memory just be to be safe... nahh.*/
if (base) { /* Use the shared memory. */
ring_offset -= (EL2_MB1_START_PG<<8);
if (ring_offset + count > EL2_MEMSIZE) {
/* We must wrap the input move. */
int semi_count = EL2_MEMSIZE - ring_offset;
memcpy_fromio(skb->data, base + ring_offset, semi_count);
count -= semi_count;
memcpy_fromio(skb->data + semi_count, base + ei_status.priv, count);
} else {
memcpy_fromio(skb->data, base + ring_offset, count);
}
return;
}
/*
* No shared memory, use programmed I/O.
*/
word = (unsigned short) ring_offset;
outb(word>>8, E33G_DMAAH);
outb(word&0xFF, E33G_DMAAL);
outb_p((ei_status.interface_num == 0 ? ECNTRL_THIN : ECNTRL_AUI) | ECNTRL_INPUT
| ECNTRL_START, E33G_CNTRL);
/*
* Here I also try to get data as fast as possible. I am betting that I
* can read one extra byte without clobbering anything in the kernel because
* this would only occur on an odd byte-count and allocation of skb->data
* is word-aligned. Variable 'count' is NOT checked. Caller must check
* for a valid count.
* [This is currently quite safe.... but if one day the 3c503 explodes
* you know where to come looking ;)]
*/
buf = (unsigned short int *) skb->data;
count = (count + 1) >> 1;
for(;;)
{
boguscount = 0x1000;
while ((inb(E33G_STATUS) & ESTAT_DPRDY) == 0)
{
if(!boguscount--)
{
pr_notice("%s: FIFO blocked in el2_block_input.\n", dev->name);
el2_reset_8390(dev);
goto blocked;
}
}
if(count > WRD_COUNT)
{
insw(E33G_FIFOH, buf, WRD_COUNT);
buf += WRD_COUNT;
count -= WRD_COUNT;
}
else
{
insw(E33G_FIFOH, buf, count);
break;
}
}
blocked:;
outb_p(ei_status.interface_num == 0 ? ECNTRL_THIN : ECNTRL_AUI, E33G_CNTRL);
}
static void netdev_get_drvinfo(struct net_device *dev,
struct ethtool_drvinfo *info)
{
strcpy(info->driver, DRV_NAME);
strcpy(info->version, DRV_VERSION);
sprintf(info->bus_info, "ISA 0x%lx", dev->base_addr);
}
static const struct ethtool_ops netdev_ethtool_ops = {
.get_drvinfo = netdev_get_drvinfo,
};
#ifdef MODULE
#define MAX_EL2_CARDS 4 /* Max number of EL2 cards per module */
static struct net_device *dev_el2[MAX_EL2_CARDS];
static int io[MAX_EL2_CARDS];
static int irq[MAX_EL2_CARDS];
static int xcvr[MAX_EL2_CARDS]; /* choose int. or ext. xcvr */
module_param_array(io, int, NULL, 0);
module_param_array(irq, int, NULL, 0);
module_param_array(xcvr, int, NULL, 0);
MODULE_PARM_DESC(io, "I/O base address(es)");
MODULE_PARM_DESC(irq, "IRQ number(s) (assigned)");
MODULE_PARM_DESC(xcvr, "transceiver(s) (0=internal, 1=external)");
MODULE_DESCRIPTION("3Com ISA EtherLink II, II/16 (3c503, 3c503/16) driver");
MODULE_LICENSE("GPL");
/* This is set up so that only a single autoprobe takes place per call.
ISA device autoprobes on a running machine are not recommended. */
int __init
init_module(void)
{
struct net_device *dev;
int this_dev, found = 0;
for (this_dev = 0; this_dev < MAX_EL2_CARDS; this_dev++) {
if (io[this_dev] == 0) {
if (this_dev != 0) break; /* only autoprobe 1st one */
pr_notice("3c503.c: Presently autoprobing (not recommended) for a single card.\n");
}
dev = alloc_eip_netdev();
if (!dev)
break;
dev->irq = irq[this_dev];
dev->base_addr = io[this_dev];
dev->mem_end = xcvr[this_dev]; /* low 4bits = xcvr sel. */
if (do_el2_probe(dev) == 0) {
dev_el2[found++] = dev;
continue;
}
free_netdev(dev);
pr_warning("3c503.c: No 3c503 card found (i/o = 0x%x).\n", io[this_dev]);
break;
}
if (found)
return 0;
return -ENXIO;
}
static void cleanup_card(struct net_device *dev)
{
/* NB: el2_close() handles free_irq */
release_region(dev->base_addr, EL2_IO_EXTENT);
if (ei_status.mem)
iounmap(ei_status.mem);
}
void __exit
cleanup_module(void)
{
int this_dev;
for (this_dev = 0; this_dev < MAX_EL2_CARDS; this_dev++) {
struct net_device *dev = dev_el2[this_dev];
if (dev) {
unregister_netdev(dev);
cleanup_card(dev);
free_netdev(dev);
}
}
}
#endif /* MODULE */

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drivers/net/3c505.c
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drivers/net/3c527.c
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drivers/net/3c59x.c
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drivers/net/8139cp.c
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drivers/net/8139too.c
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drivers/net/82596.c
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103
drivers/net/8390.c
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/* 8390 core for usual drivers */
static const char version[] =
"8390.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
#include "lib8390.c"
int ei_open(struct net_device *dev)
{
return __ei_open(dev);
}
EXPORT_SYMBOL(ei_open);
int ei_close(struct net_device *dev)
{
return __ei_close(dev);
}
EXPORT_SYMBOL(ei_close);
netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
return __ei_start_xmit(skb, dev);
}
EXPORT_SYMBOL(ei_start_xmit);
struct net_device_stats *ei_get_stats(struct net_device *dev)
{
return __ei_get_stats(dev);
}
EXPORT_SYMBOL(ei_get_stats);
void ei_set_multicast_list(struct net_device *dev)
{
__ei_set_multicast_list(dev);
}
EXPORT_SYMBOL(ei_set_multicast_list);
void ei_tx_timeout(struct net_device *dev)
{
__ei_tx_timeout(dev);
}
EXPORT_SYMBOL(ei_tx_timeout);
irqreturn_t ei_interrupt(int irq, void *dev_id)
{
return __ei_interrupt(irq, dev_id);
}
EXPORT_SYMBOL(ei_interrupt);
#ifdef CONFIG_NET_POLL_CONTROLLER
void ei_poll(struct net_device *dev)
{
__ei_poll(dev);
}
EXPORT_SYMBOL(ei_poll);
#endif
const struct net_device_ops ei_netdev_ops = {
.ndo_open = ei_open,
.ndo_stop = ei_close,
.ndo_start_xmit = ei_start_xmit,
.ndo_tx_timeout = ei_tx_timeout,
.ndo_get_stats = ei_get_stats,
.ndo_set_multicast_list = ei_set_multicast_list,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = eth_mac_addr,
.ndo_change_mtu = eth_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = ei_poll,
#endif
};
EXPORT_SYMBOL(ei_netdev_ops);
struct net_device *__alloc_ei_netdev(int size)
{
struct net_device *dev = ____alloc_ei_netdev(size);
if (dev)
dev->netdev_ops = &ei_netdev_ops;
return dev;
}
EXPORT_SYMBOL(__alloc_ei_netdev);
void NS8390_init(struct net_device *dev, int startp)
{
__NS8390_init(dev, startp);
}
EXPORT_SYMBOL(NS8390_init);
#if defined(MODULE)
static int __init ns8390_module_init(void)
{
return 0;
}
static void __exit ns8390_module_exit(void)
{
}
module_init(ns8390_module_init);
module_exit(ns8390_module_exit);
#endif /* MODULE */
MODULE_LICENSE("GPL");

105
drivers/net/8390p.c
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/* 8390 core for ISA devices needing bus delays */
static const char version[] =
"8390p.c:v1.10cvs 9/23/94 Donald Becker (becker@cesdis.gsfc.nasa.gov)\n";
#define ei_inb(_p) inb(_p)
#define ei_outb(_v, _p) outb(_v, _p)
#define ei_inb_p(_p) inb_p(_p)
#define ei_outb_p(_v, _p) outb_p(_v, _p)
#include "lib8390.c"
int eip_open(struct net_device *dev)
{
return __ei_open(dev);
}
EXPORT_SYMBOL(eip_open);
int eip_close(struct net_device *dev)
{
return __ei_close(dev);
}
EXPORT_SYMBOL(eip_close);
netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
return __ei_start_xmit(skb, dev);
}
EXPORT_SYMBOL(eip_start_xmit);
struct net_device_stats *eip_get_stats(struct net_device *dev)
{
return __ei_get_stats(dev);
}
EXPORT_SYMBOL(eip_get_stats);
void eip_set_multicast_list(struct net_device *dev)
{
__ei_set_multicast_list(dev);
}
EXPORT_SYMBOL(eip_set_multicast_list);
void eip_tx_timeout(struct net_device *dev)
{
__ei_tx_timeout(dev);
}
EXPORT_SYMBOL(eip_tx_timeout);
irqreturn_t eip_interrupt(int irq, void *dev_id)
{
return __ei_interrupt(irq, dev_id);
}
EXPORT_SYMBOL(eip_interrupt);
#ifdef CONFIG_NET_POLL_CONTROLLER
void eip_poll(struct net_device *dev)
{
__ei_poll(dev);
}
EXPORT_SYMBOL(eip_poll);
#endif
const struct net_device_ops eip_netdev_ops = {
.ndo_open = eip_open,
.ndo_stop = eip_close,
.ndo_start_xmit = eip_start_xmit,
.ndo_tx_timeout = eip_tx_timeout,
.ndo_get_stats = eip_get_stats,
.ndo_set_multicast_list = eip_set_multicast_list,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = eth_mac_addr,
.ndo_change_mtu = eth_change_mtu,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = eip_poll,
#endif
};
EXPORT_SYMBOL(eip_netdev_ops);
struct net_device *__alloc_eip_netdev(int size)
{
struct net_device *dev = ____alloc_ei_netdev(size);
if (dev)
dev->netdev_ops = &eip_netdev_ops;
return dev;
}
EXPORT_SYMBOL(__alloc_eip_netdev);
void NS8390p_init(struct net_device *dev, int startp)
{
__NS8390_init(dev, startp);
}
EXPORT_SYMBOL(NS8390p_init);
static int __init NS8390p_init_module(void)
{
return 0;
}
static void __exit NS8390p_cleanup_module(void)
{
}
module_init(NS8390p_init_module);
module_exit(NS8390p_cleanup_module);
MODULE_LICENSE("GPL");

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drivers/net/Kconfig
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