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Altera TSE: Fix sparse errors and warnings

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This patch fixes the many sparse errors and warnings contained in the
initial submission of the Altera Triple Speed Ethernet driver, and a
few minor cppcheck warnings. Changes are tested on ARM and NIOS2
example designs, and compile tested against multiple architectures.
Typical issues addressed were as follows:

altera_tse_ethtool.c:136:19: warning: incorrect type in argument
    1 (different address spaces)
altera_tse_ethtool.c:136:19:    expected void const volatile
    [noderef] <asn:2>*addr
altera_tse_ethtool.c:136:19:    got unsigned int *<noident>
...
altera_sgdma.c:129:31: warning: cast removes address space of
    expression

Signed-off-by: Vince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vince Bridgers 2014-05-14 14:38:36 -05:00 committed by David S. Miller
parent 200b916f35
commit 898305806a
10 changed files with 366 additions and 274 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/net/ethernet/altera/Makefile
View File

@ -5,3 +5,4 @@
obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \ altera_tse-objs := altera_tse_main.o altera_tse_ethtool.o \
altera_msgdma.o altera_sgdma.o altera_utils.o altera_msgdma.o altera_sgdma.o altera_utils.o
ccflags-y += -D__CHECK_ENDIAN__

108
drivers/net/ethernet/altera/altera_msgdma.c
View File

@ -37,18 +37,16 @@ void msgdma_start_rxdma(struct altera_tse_private *priv)
void msgdma_reset(struct altera_tse_private *priv) void msgdma_reset(struct altera_tse_private *priv)
{ {
int counter; int counter;
struct msgdma_csr *txcsr =
(struct msgdma_csr *)priv->tx_dma_csr;
struct msgdma_csr *rxcsr =
(struct msgdma_csr *)priv->rx_dma_csr;
/* Reset Rx mSGDMA */ /* Reset Rx mSGDMA */
iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
iowrite32(MSGDMA_CSR_CTL_RESET, &rxcsr->control); msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
msgdma_csroffs(control));
counter = 0; counter = 0;
while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
if (tse_bit_is_clear(&rxcsr->status, if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
MSGDMA_CSR_STAT_RESETTING)) MSGDMA_CSR_STAT_RESETTING))
break; break;
udelay(1); udelay(1);
@ -59,15 +57,18 @@ void msgdma_reset(struct altera_tse_private *priv)
"TSE Rx mSGDMA resetting bit never cleared!\n"); "TSE Rx mSGDMA resetting bit never cleared!\n");
/* clear all status bits */ /* clear all status bits */
iowrite32(MSGDMA_CSR_STAT_MASK, &rxcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
/* Reset Tx mSGDMA */ /* Reset Tx mSGDMA */
iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
iowrite32(MSGDMA_CSR_CTL_RESET, &txcsr->control); msgdma_csroffs(status));
csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
msgdma_csroffs(control));
counter = 0; counter = 0;
while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
if (tse_bit_is_clear(&txcsr->status, if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
MSGDMA_CSR_STAT_RESETTING)) MSGDMA_CSR_STAT_RESETTING))
break; break;
udelay(1); udelay(1);
@ -78,58 +79,58 @@ void msgdma_reset(struct altera_tse_private *priv)
"TSE Tx mSGDMA resetting bit never cleared!\n"); "TSE Tx mSGDMA resetting bit never cleared!\n");
/* clear all status bits */ /* clear all status bits */
iowrite32(MSGDMA_CSR_STAT_MASK, &txcsr->status); csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
} }
void msgdma_disable_rxirq(struct altera_tse_private *priv) void msgdma_disable_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_enable_rxirq(struct altera_tse_private *priv) void msgdma_enable_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_disable_txirq(struct altera_tse_private *priv) void msgdma_disable_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
tse_clear_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_enable_txirq(struct altera_tse_private *priv) void msgdma_enable_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
tse_set_bit(&csr->control, MSGDMA_CSR_CTL_GLOBAL_INTR); MSGDMA_CSR_CTL_GLOBAL_INTR);
} }
void msgdma_clear_rxirq(struct altera_tse_private *priv) void msgdma_clear_rxirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->rx_dma_csr; csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
} }
void msgdma_clear_txirq(struct altera_tse_private *priv) void msgdma_clear_txirq(struct altera_tse_private *priv)
{ {
struct msgdma_csr *csr = priv->tx_dma_csr; csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
iowrite32(MSGDMA_CSR_STAT_IRQ, &csr->status);
} }
/* return 0 to indicate transmit is pending */ /* return 0 to indicate transmit is pending */
int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
{ {
struct msgdma_extended_desc *desc = priv->tx_dma_desc; csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
msgdma_descroffs(read_addr_lo));
iowrite32(lower_32_bits(buffer->dma_addr), &desc->read_addr_lo); csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
iowrite32(upper_32_bits(buffer->dma_addr), &desc->read_addr_hi); msgdma_descroffs(read_addr_hi));
iowrite32(0, &desc->write_addr_lo); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
iowrite32(0, &desc->write_addr_hi); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
iowrite32(buffer->len, &desc->len); csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
iowrite32(0, &desc->burst_seq_num); csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
iowrite32(MSGDMA_DESC_TX_STRIDE, &desc->stride); csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
iowrite32(MSGDMA_DESC_CTL_TX_SINGLE, &desc->control); msgdma_descroffs(stride));
csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
msgdma_descroffs(control));
return 0; return 0;
} }
@ -138,17 +139,16 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
u32 ready = 0; u32 ready = 0;
u32 inuse; u32 inuse;
u32 status; u32 status;
struct msgdma_csr *txcsr =
(struct msgdma_csr *)priv->tx_dma_csr;
/* Get number of sent descriptors */ /* Get number of sent descriptors */
inuse = ioread32(&txcsr->rw_fill_level) & 0xffff; inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
& 0xffff;
if (inuse) { /* Tx FIFO is not empty */ if (inuse) { /* Tx FIFO is not empty */
ready = priv->tx_prod - priv->tx_cons - inuse - 1; ready = priv->tx_prod - priv->tx_cons - inuse - 1;
} else { } else {
/* Check for buffered last packet */ /* Check for buffered last packet */
status = ioread32(&txcsr->status); status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
if (status & MSGDMA_CSR_STAT_BUSY) if (status & MSGDMA_CSR_STAT_BUSY)
ready = priv->tx_prod - priv->tx_cons - 1; ready = priv->tx_prod - priv->tx_cons - 1;
else else
@ -162,7 +162,6 @@ u32 msgdma_tx_completions(struct altera_tse_private *priv)
void msgdma_add_rx_desc(struct altera_tse_private *priv, void msgdma_add_rx_desc(struct altera_tse_private *priv,
struct tse_buffer *rxbuffer) struct tse_buffer *rxbuffer)
{ {
struct msgdma_extended_desc *desc = priv->rx_dma_desc;
u32 len = priv->rx_dma_buf_sz; u32 len = priv->rx_dma_buf_sz;
dma_addr_t dma_addr = rxbuffer->dma_addr; dma_addr_t dma_addr = rxbuffer->dma_addr;
u32 control = (MSGDMA_DESC_CTL_END_ON_EOP u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
@ -172,14 +171,16 @@ void msgdma_add_rx_desc(struct altera_tse_private *priv,
| MSGDMA_DESC_CTL_TR_ERR_IRQ | MSGDMA_DESC_CTL_TR_ERR_IRQ
| MSGDMA_DESC_CTL_GO); | MSGDMA_DESC_CTL_GO);
iowrite32(0, &desc->read_addr_lo); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
iowrite32(0, &desc->read_addr_hi); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
iowrite32(lower_32_bits(dma_addr), &desc->write_addr_lo); csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
iowrite32(upper_32_bits(dma_addr), &desc->write_addr_hi); msgdma_descroffs(write_addr_lo));
iowrite32(len, &desc->len); csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
iowrite32(0, &desc->burst_seq_num); msgdma_descroffs(write_addr_hi));
iowrite32(0x00010001, &desc->stride); csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
iowrite32(control, &desc->control); csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
} }
/* status is returned on upper 16 bits, /* status is returned on upper 16 bits,
@ -190,14 +191,13 @@ u32 msgdma_rx_status(struct altera_tse_private *priv)
u32 rxstatus = 0; u32 rxstatus = 0;
u32 pktlength; u32 pktlength;
u32 pktstatus; u32 pktstatus;
struct msgdma_csr *rxcsr =
(struct msgdma_csr *)priv->rx_dma_csr;
struct msgdma_response *rxresp =
(struct msgdma_response *)priv->rx_dma_resp;
if (ioread32(&rxcsr->resp_fill_level) & 0xffff) { if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
pktlength = ioread32(&rxresp->bytes_transferred); & 0xffff) {
pktstatus = ioread32(&rxresp->status); pktlength = csrrd32(priv->rx_dma_resp,
msgdma_respoffs(bytes_transferred));
pktstatus = csrrd32(priv->rx_dma_resp,
msgdma_respoffs(status));
rxstatus = pktstatus; rxstatus = pktstatus;
rxstatus = rxstatus << 16; rxstatus = rxstatus << 16;
rxstatus |= (pktlength & 0xffff); rxstatus |= (pktlength & 0xffff);

13
drivers/net/ethernet/altera/altera_msgdmahw.h
View File

@ -17,15 +17,6 @@
#ifndef __ALTERA_MSGDMAHW_H__ #ifndef __ALTERA_MSGDMAHW_H__
#define __ALTERA_MSGDMAHW_H__ #define __ALTERA_MSGDMAHW_H__
/* mSGDMA standard descriptor format
*/
struct msgdma_desc {
u32 read_addr; /* data buffer source address */
u32 write_addr; /* data buffer destination address */
u32 len; /* the number of bytes to transfer per descriptor */
u32 control; /* characteristics of the transfer */
};
/* mSGDMA extended descriptor format /* mSGDMA extended descriptor format
*/ */
struct msgdma_extended_desc { struct msgdma_extended_desc {
@ -159,6 +150,10 @@ struct msgdma_response {
u32 status; u32 status;
}; };
#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))
#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))
#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))
/* mSGDMA response register bit definitions /* mSGDMA response register bit definitions
*/ */
#define MSGDMA_RESP_EARLY_TERM BIT(8) #define MSGDMA_RESP_EARLY_TERM BIT(8)

181
drivers/net/ethernet/altera/altera_sgdma.c
View File

@ -20,8 +20,8 @@
#include "altera_sgdmahw.h" #include "altera_sgdmahw.h"
#include "altera_sgdma.h" #include "altera_sgdma.h"
static void sgdma_setup_descrip(struct sgdma_descrip *desc, static void sgdma_setup_descrip(struct sgdma_descrip __iomem *desc,
struct sgdma_descrip *ndesc, struct sgdma_descrip __iomem *ndesc,
dma_addr_t ndesc_phys, dma_addr_t ndesc_phys,
dma_addr_t raddr, dma_addr_t raddr,
dma_addr_t waddr, dma_addr_t waddr,
@ -31,17 +31,17 @@ static void sgdma_setup_descrip(struct sgdma_descrip *desc,
int wfixed); int wfixed);
static int sgdma_async_write(struct altera_tse_private *priv, static int sgdma_async_write(struct altera_tse_private *priv,
struct sgdma_descrip *desc); struct sgdma_descrip __iomem *desc);
static int sgdma_async_read(struct altera_tse_private *priv); static int sgdma_async_read(struct altera_tse_private *priv);
static dma_addr_t static dma_addr_t
sgdma_txphysaddr(struct altera_tse_private *priv, sgdma_txphysaddr(struct altera_tse_private *priv,
struct sgdma_descrip *desc); struct sgdma_descrip __iomem *desc);
static dma_addr_t static dma_addr_t
sgdma_rxphysaddr(struct altera_tse_private *priv, sgdma_rxphysaddr(struct altera_tse_private *priv,
struct sgdma_descrip *desc); struct sgdma_descrip __iomem *desc);
static int sgdma_txbusy(struct altera_tse_private *priv); static int sgdma_txbusy(struct altera_tse_private *priv);
@ -79,7 +79,8 @@ int sgdma_initialize(struct altera_tse_private *priv)
priv->rxdescphys = (dma_addr_t) 0; priv->rxdescphys = (dma_addr_t) 0;
priv->txdescphys = (dma_addr_t) 0; priv->txdescphys = (dma_addr_t) 0;
priv->rxdescphys = dma_map_single(priv->device, priv->rx_dma_desc, priv->rxdescphys = dma_map_single(priv->device,
(void __force *)priv->rx_dma_desc,
priv->rxdescmem, DMA_BIDIRECTIONAL); priv->rxdescmem, DMA_BIDIRECTIONAL);
if (dma_mapping_error(priv->device, priv->rxdescphys)) { if (dma_mapping_error(priv->device, priv->rxdescphys)) {
@ -88,7 +89,8 @@ int sgdma_initialize(struct altera_tse_private *priv)
return -EINVAL; return -EINVAL;
} }
priv->txdescphys = dma_map_single(priv->device, priv->tx_dma_desc, priv->txdescphys = dma_map_single(priv->device,
(void __force *)priv->tx_dma_desc,
priv->txdescmem, DMA_TO_DEVICE); priv->txdescmem, DMA_TO_DEVICE);
if (dma_mapping_error(priv->device, priv->txdescphys)) { if (dma_mapping_error(priv->device, priv->txdescphys)) {
@ -98,8 +100,8 @@ int sgdma_initialize(struct altera_tse_private *priv)
} }
/* Initialize descriptor memory to all 0's, sync memory to cache */ /* Initialize descriptor memory to all 0's, sync memory to cache */
memset(priv->tx_dma_desc, 0, priv->txdescmem); memset_io(priv->tx_dma_desc, 0, priv->txdescmem);
memset(priv->rx_dma_desc, 0, priv->rxdescmem); memset_io(priv->rx_dma_desc, 0, priv->rxdescmem);
dma_sync_single_for_device(priv->device, priv->txdescphys, dma_sync_single_for_device(priv->device, priv->txdescphys,
priv->txdescmem, DMA_TO_DEVICE); priv->txdescmem, DMA_TO_DEVICE);
@ -126,22 +128,15 @@ void sgdma_uninitialize(struct altera_tse_private *priv)
*/ */
void sgdma_reset(struct altera_tse_private *priv) void sgdma_reset(struct altera_tse_private *priv)
{ {
u32 *ptxdescripmem = (u32 *)priv->tx_dma_desc;
u32 txdescriplen = priv->txdescmem;
u32 *prxdescripmem = (u32 *)priv->rx_dma_desc;
u32 rxdescriplen = priv->rxdescmem;
struct sgdma_csr *ptxsgdma = (struct sgdma_csr *)priv->tx_dma_csr;
struct sgdma_csr *prxsgdma = (struct sgdma_csr *)priv->rx_dma_csr;
/* Initialize descriptor memory to 0 */ /* Initialize descriptor memory to 0 */
memset(ptxdescripmem, 0, txdescriplen); memset_io(priv->tx_dma_desc, 0, priv->txdescmem);
memset(prxdescripmem, 0, rxdescriplen); memset_io(priv->rx_dma_desc, 0, priv->rxdescmem);
iowrite32(SGDMA_CTRLREG_RESET, &ptxsgdma->control); csrwr32(SGDMA_CTRLREG_RESET, priv->tx_dma_csr, sgdma_csroffs(control));
iowrite32(0, &ptxsgdma->control); csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
iowrite32(SGDMA_CTRLREG_RESET, &prxsgdma->control); csrwr32(SGDMA_CTRLREG_RESET, priv->rx_dma_csr, sgdma_csroffs(control));
iowrite32(0, &prxsgdma->control); csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
} }
/* For SGDMA, interrupts remain enabled after initially enabling, /* For SGDMA, interrupts remain enabled after initially enabling,
@ -167,14 +162,14 @@ void sgdma_disable_txirq(struct altera_tse_private *priv)
void sgdma_clear_rxirq(struct altera_tse_private *priv) void sgdma_clear_rxirq(struct altera_tse_private *priv)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr; tse_set_bit(priv->rx_dma_csr, sgdma_csroffs(control),
tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT); SGDMA_CTRLREG_CLRINT);
} }
void sgdma_clear_txirq(struct altera_tse_private *priv) void sgdma_clear_txirq(struct altera_tse_private *priv)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr; tse_set_bit(priv->tx_dma_csr, sgdma_csroffs(control),
tse_set_bit(&csr->control, SGDMA_CTRLREG_CLRINT); SGDMA_CTRLREG_CLRINT);
} }
/* transmits buffer through SGDMA. Returns number of buffers /* transmits buffer through SGDMA. Returns number of buffers
@ -184,12 +179,11 @@ void sgdma_clear_txirq(struct altera_tse_private *priv)
*/ */
int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer) int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
{ {
int pktstx = 0; struct sgdma_descrip __iomem *descbase =
struct sgdma_descrip *descbase = (struct sgdma_descrip __iomem *)priv->tx_dma_desc;
(struct sgdma_descrip *)priv->tx_dma_desc;
struct sgdma_descrip *cdesc = &descbase[0]; struct sgdma_descrip __iomem *cdesc = &descbase[0];
struct sgdma_descrip *ndesc = &descbase[1]; struct sgdma_descrip __iomem *ndesc = &descbase[1];
/* wait 'til the tx sgdma is ready for the next transmit request */ /* wait 'til the tx sgdma is ready for the next transmit request */
if (sgdma_txbusy(priv)) if (sgdma_txbusy(priv))
@ -205,7 +199,7 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
0, /* read fixed */ 0, /* read fixed */
SGDMA_CONTROL_WR_FIXED); /* Generate SOP */ SGDMA_CONTROL_WR_FIXED); /* Generate SOP */
pktstx = sgdma_async_write(priv, cdesc); sgdma_async_write(priv, cdesc);
/* enqueue the request to the pending transmit queue */ /* enqueue the request to the pending transmit queue */
queue_tx(priv, buffer); queue_tx(priv, buffer);
@ -219,10 +213,10 @@ int sgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
u32 sgdma_tx_completions(struct altera_tse_private *priv) u32 sgdma_tx_completions(struct altera_tse_private *priv)
{ {
u32 ready = 0; u32 ready = 0;
struct sgdma_descrip *desc = (struct sgdma_descrip *)priv->tx_dma_desc;
if (!sgdma_txbusy(priv) && if (!sgdma_txbusy(priv) &&
((desc->control & SGDMA_CONTROL_HW_OWNED) == 0) && ((csrrd8(priv->tx_dma_desc, sgdma_descroffs(control))
& SGDMA_CONTROL_HW_OWNED) == 0) &&
(dequeue_tx(priv))) { (dequeue_tx(priv))) {
ready = 1; ready = 1;
} }
@ -246,32 +240,31 @@ void sgdma_add_rx_desc(struct altera_tse_private *priv,
*/ */
u32 sgdma_rx_status(struct altera_tse_private *priv) u32 sgdma_rx_status(struct altera_tse_private *priv)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr; struct sgdma_descrip __iomem *base =
struct sgdma_descrip *base = (struct sgdma_descrip *)priv->rx_dma_desc; (struct sgdma_descrip __iomem *)priv->rx_dma_desc;
struct sgdma_descrip *desc = NULL; struct sgdma_descrip __iomem *desc = NULL;
int pktsrx;
unsigned int rxstatus = 0;
unsigned int pktlength = 0;
unsigned int pktstatus = 0;
struct tse_buffer *rxbuffer = NULL; struct tse_buffer *rxbuffer = NULL;
unsigned int rxstatus = 0;
u32 sts = ioread32(&csr->status); u32 sts = csrrd32(priv->rx_dma_csr, sgdma_csroffs(status));
desc = &base[0]; desc = &base[0];
if (sts & SGDMA_STSREG_EOP) { if (sts & SGDMA_STSREG_EOP) {
unsigned int pktlength = 0;
unsigned int pktstatus = 0;
dma_sync_single_for_cpu(priv->device, dma_sync_single_for_cpu(priv->device,
priv->rxdescphys, priv->rxdescphys,
priv->sgdmadesclen, priv->sgdmadesclen,
DMA_FROM_DEVICE); DMA_FROM_DEVICE);
pktlength = desc->bytes_xferred; pktlength = csrrd16(desc, sgdma_descroffs(bytes_xferred));
pktstatus = desc->status & 0x3f; pktstatus = csrrd8(desc, sgdma_descroffs(status));
rxstatus = pktstatus; rxstatus = pktstatus & ~SGDMA_STATUS_EOP;
rxstatus = rxstatus << 16; rxstatus = rxstatus << 16;
rxstatus |= (pktlength & 0xffff); rxstatus |= (pktlength & 0xffff);
if (rxstatus) { if (rxstatus) {
desc->status = 0; csrwr8(0, desc, sgdma_descroffs(status));
rxbuffer = dequeue_rx(priv); rxbuffer = dequeue_rx(priv);
if (rxbuffer == NULL) if (rxbuffer == NULL)
@ -279,12 +272,12 @@ u32 sgdma_rx_status(struct altera_tse_private *priv)
"sgdma rx and rx queue empty!\n"); "sgdma rx and rx queue empty!\n");
/* Clear control */ /* Clear control */
iowrite32(0, &csr->control); csrwr32(0, priv->rx_dma_csr, sgdma_csroffs(control));
/* clear status */ /* clear status */
iowrite32(0xf, &csr->status); csrwr32(0xf, priv->rx_dma_csr, sgdma_csroffs(status));
/* kick the rx sgdma after reaping this descriptor */ /* kick the rx sgdma after reaping this descriptor */
pktsrx = sgdma_async_read(priv); sgdma_async_read(priv);
} else { } else {
/* If the SGDMA indicated an end of packet on recv, /* If the SGDMA indicated an end of packet on recv,
@ -298,10 +291,11 @@ u32 sgdma_rx_status(struct altera_tse_private *priv)
*/ */
netdev_err(priv->dev, netdev_err(priv->dev,
"SGDMA RX Error Info: %x, %x, %x\n", "SGDMA RX Error Info: %x, %x, %x\n",
sts, desc->status, rxstatus); sts, csrrd8(desc, sgdma_descroffs(status)),
rxstatus);
} }
} else if (sts == 0) { } else if (sts == 0) {
pktsrx = sgdma_async_read(priv); sgdma_async_read(priv);
} }
return rxstatus; return rxstatus;
@ -309,8 +303,8 @@ u32 sgdma_rx_status(struct altera_tse_private *priv)
/* Private functions */ /* Private functions */
static void sgdma_setup_descrip(struct sgdma_descrip *desc, static void sgdma_setup_descrip(struct sgdma_descrip __iomem *desc,
struct sgdma_descrip *ndesc, struct sgdma_descrip __iomem *ndesc,
dma_addr_t ndesc_phys, dma_addr_t ndesc_phys,
dma_addr_t raddr, dma_addr_t raddr,
dma_addr_t waddr, dma_addr_t waddr,
@ -320,27 +314,30 @@ static void sgdma_setup_descrip(struct sgdma_descrip *desc,
int wfixed) int wfixed)
{ {
/* Clear the next descriptor as not owned by hardware */ /* Clear the next descriptor as not owned by hardware */
u32 ctrl = ndesc->control;
ctrl &= ~SGDMA_CONTROL_HW_OWNED;
ndesc->control = ctrl;
ctrl = 0; u32 ctrl = csrrd8(ndesc, sgdma_descroffs(control));
ctrl &= ~SGDMA_CONTROL_HW_OWNED;
csrwr8(ctrl, ndesc, sgdma_descroffs(control));
ctrl = SGDMA_CONTROL_HW_OWNED; ctrl = SGDMA_CONTROL_HW_OWNED;
ctrl |= generate_eop; ctrl |= generate_eop;
ctrl |= rfixed; ctrl |= rfixed;
ctrl |= wfixed; ctrl |= wfixed;
/* Channel is implicitly zero, initialized to 0 by default */ /* Channel is implicitly zero, initialized to 0 by default */
csrwr32(lower_32_bits(raddr), desc, sgdma_descroffs(raddr));
csrwr32(lower_32_bits(waddr), desc, sgdma_descroffs(waddr));
desc->raddr = raddr; csrwr32(0, desc, sgdma_descroffs(pad1));
desc->waddr = waddr; csrwr32(0, desc, sgdma_descroffs(pad2));
desc->next = lower_32_bits(ndesc_phys); csrwr32(lower_32_bits(ndesc_phys), desc, sgdma_descroffs(next));
desc->control = ctrl;
desc->status = 0; csrwr8(ctrl, desc, sgdma_descroffs(control));
desc->rburst = 0; csrwr8(0, desc, sgdma_descroffs(status));
desc->wburst = 0; csrwr8(0, desc, sgdma_descroffs(wburst));
desc->bytes = length; csrwr8(0, desc, sgdma_descroffs(rburst));
desc->bytes_xferred = 0; csrwr16(length, desc, sgdma_descroffs(bytes));
csrwr16(0, desc, sgdma_descroffs(bytes_xferred));
} }
/* If hardware is busy, don't restart async read. /* If hardware is busy, don't restart async read.
@ -351,12 +348,11 @@ static void sgdma_setup_descrip(struct sgdma_descrip *desc,
*/ */
static int sgdma_async_read(struct altera_tse_private *priv) static int sgdma_async_read(struct altera_tse_private *priv)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr; struct sgdma_descrip __iomem *descbase =
struct sgdma_descrip *descbase = (struct sgdma_descrip __iomem *)priv->rx_dma_desc;
(struct sgdma_descrip *)priv->rx_dma_desc;
struct sgdma_descrip *cdesc = &descbase[0]; struct sgdma_descrip __iomem *cdesc = &descbase[0];
struct sgdma_descrip *ndesc = &descbase[1]; struct sgdma_descrip __iomem *ndesc = &descbase[1];
struct tse_buffer *rxbuffer = NULL; struct tse_buffer *rxbuffer = NULL;
@ -382,11 +378,13 @@ static int sgdma_async_read(struct altera_tse_private *priv)
priv->sgdmadesclen, priv->sgdmadesclen,
DMA_TO_DEVICE); DMA_TO_DEVICE);
iowrite32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)), csrwr32(lower_32_bits(sgdma_rxphysaddr(priv, cdesc)),
&csr->next_descrip); priv->rx_dma_csr,
sgdma_csroffs(next_descrip));
iowrite32((priv->rxctrlreg | SGDMA_CTRLREG_START), csrwr32((priv->rxctrlreg | SGDMA_CTRLREG_START),
&csr->control); priv->rx_dma_csr,
sgdma_csroffs(control));
return 1; return 1;
} }
@ -395,32 +393,32 @@ static int sgdma_async_read(struct altera_tse_private *priv)
} }
static int sgdma_async_write(struct altera_tse_private *priv, static int sgdma_async_write(struct altera_tse_private *priv,
struct sgdma_descrip *desc) struct sgdma_descrip __iomem *desc)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
if (sgdma_txbusy(priv)) if (sgdma_txbusy(priv))
return 0; return 0;
/* clear control and status */ /* clear control and status */
iowrite32(0, &csr->control); csrwr32(0, priv->tx_dma_csr, sgdma_csroffs(control));
iowrite32(0x1f, &csr->status); csrwr32(0x1f, priv->tx_dma_csr, sgdma_csroffs(status));
dma_sync_single_for_device(priv->device, priv->txdescphys, dma_sync_single_for_device(priv->device, priv->txdescphys,
priv->sgdmadesclen, DMA_TO_DEVICE); priv->sgdmadesclen, DMA_TO_DEVICE);
iowrite32(lower_32_bits(sgdma_txphysaddr(priv, desc)), csrwr32(lower_32_bits(sgdma_txphysaddr(priv, desc)),
&csr->next_descrip); priv->tx_dma_csr,
sgdma_csroffs(next_descrip));
iowrite32((priv->txctrlreg | SGDMA_CTRLREG_START), csrwr32((priv->txctrlreg | SGDMA_CTRLREG_START),
&csr->control); priv->tx_dma_csr,
sgdma_csroffs(control));
return 1; return 1;
} }
static dma_addr_t static dma_addr_t
sgdma_txphysaddr(struct altera_tse_private *priv, sgdma_txphysaddr(struct altera_tse_private *priv,
struct sgdma_descrip *desc) struct sgdma_descrip __iomem *desc)
{ {
dma_addr_t paddr = priv->txdescmem_busaddr; dma_addr_t paddr = priv->txdescmem_busaddr;
uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->tx_dma_desc; uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->tx_dma_desc;
@ -429,7 +427,7 @@ sgdma_txphysaddr(struct altera_tse_private *priv,
static dma_addr_t static dma_addr_t
sgdma_rxphysaddr(struct altera_tse_private *priv, sgdma_rxphysaddr(struct altera_tse_private *priv,
struct sgdma_descrip *desc) struct sgdma_descrip __iomem *desc)
{ {
dma_addr_t paddr = priv->rxdescmem_busaddr; dma_addr_t paddr = priv->rxdescmem_busaddr;
uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->rx_dma_desc; uintptr_t offs = (uintptr_t)desc - (uintptr_t)priv->rx_dma_desc;
@ -518,8 +516,8 @@ queue_rx_peekhead(struct altera_tse_private *priv)
*/ */
static int sgdma_rxbusy(struct altera_tse_private *priv) static int sgdma_rxbusy(struct altera_tse_private *priv)
{ {
struct sgdma_csr *csr = (struct sgdma_csr *)priv->rx_dma_csr; return csrrd32(priv->rx_dma_csr, sgdma_csroffs(status))
return ioread32(&csr->status) & SGDMA_STSREG_BUSY; & SGDMA_STSREG_BUSY;
} }
/* waits for the tx sgdma to finish it's current operation, returns 0 /* waits for the tx sgdma to finish it's current operation, returns 0
@ -528,13 +526,14 @@ static int sgdma_rxbusy(struct altera_tse_private *priv)
static int sgdma_txbusy(struct altera_tse_private *priv) static int sgdma_txbusy(struct altera_tse_private *priv)
{ {
int delay = 0; int delay = 0;
struct sgdma_csr *csr = (struct sgdma_csr *)priv->tx_dma_csr;
/* if DMA is busy, wait for current transactino to finish */ /* if DMA is busy, wait for current transactino to finish */
while ((ioread32(&csr->status) & SGDMA_STSREG_BUSY) && (delay++ < 100)) while ((csrrd32(priv->tx_dma_csr, sgdma_csroffs(status))
& SGDMA_STSREG_BUSY) && (delay++ < 100))
udelay(1); udelay(1);
if (ioread32(&csr->status) & SGDMA_STSREG_BUSY) { if (csrrd32(priv->tx_dma_csr, sgdma_csroffs(status))
& SGDMA_STSREG_BUSY) {
netdev_err(priv->dev, "timeout waiting for tx dma\n"); netdev_err(priv->dev, "timeout waiting for tx dma\n");
return 1; return 1;
} }

26
drivers/net/ethernet/altera/altera_sgdmahw.h
View File

@ -19,16 +19,16 @@
/* SGDMA descriptor structure */ /* SGDMA descriptor structure */
struct sgdma_descrip { struct sgdma_descrip {
unsigned int raddr; /* address of data to be read */ u32 raddr; /* address of data to be read */
unsigned int pad1; u32 pad1;
unsigned int waddr; u32 waddr;
unsigned int pad2; u32 pad2;
unsigned int next; u32 next;
unsigned int pad3; u32 pad3;
unsigned short bytes; u16 bytes;
unsigned char rburst; u8 rburst;
unsigned char wburst; u8 wburst;
unsigned short bytes_xferred; /* 16 bits, bytes xferred */ u16 bytes_xferred; /* 16 bits, bytes xferred */
/* bit 0: error /* bit 0: error
* bit 1: length error * bit 1: length error
@ -39,7 +39,7 @@ struct sgdma_descrip {
* bit 6: reserved * bit 6: reserved
* bit 7: status eop for recv case * bit 7: status eop for recv case
*/ */
unsigned char status; u8 status;
/* bit 0: eop /* bit 0: eop
* bit 1: read_fixed * bit 1: read_fixed
@ -47,7 +47,7 @@ struct sgdma_descrip {
* bits 3,4,5,6: Channel (always 0) * bits 3,4,5,6: Channel (always 0)
* bit 7: hardware owned * bit 7: hardware owned
*/ */
unsigned char control; u8 control;
} __packed; } __packed;
@ -101,6 +101,8 @@ struct sgdma_csr {
u32 pad3[3]; u32 pad3[3];
}; };
#define sgdma_csroffs(a) (offsetof(struct sgdma_csr, a))
#define sgdma_descroffs(a) (offsetof(struct sgdma_descrip, a))
#define SGDMA_STSREG_ERR BIT(0) /* Error */ #define SGDMA_STSREG_ERR BIT(0) /* Error */
#define SGDMA_STSREG_EOP BIT(1) /* EOP */ #define SGDMA_STSREG_EOP BIT(1) /* EOP */

47
drivers/net/ethernet/altera/altera_tse.h
View File

@ -357,6 +357,8 @@ struct altera_tse_mac {
u32 reserved5[42]; u32 reserved5[42];
}; };
#define tse_csroffs(a) (offsetof(struct altera_tse_mac, a))
/* Transmit and Receive Command Registers Bit Definitions /* Transmit and Receive Command Registers Bit Definitions
*/ */
#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17)
@ -487,4 +489,49 @@ struct altera_tse_private {
*/ */
void altera_tse_set_ethtool_ops(struct net_device *); void altera_tse_set_ethtool_ops(struct net_device *);
static inline
u32 csrrd32(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readl(paddr);
}
static inline
u16 csrrd16(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readw(paddr);
}
static inline
u8 csrrd8(void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
return readb(paddr);
}
static inline
void csrwr32(u32 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writel(val, paddr);
}
static inline
void csrwr16(u16 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writew(val, paddr);
}
static inline
void csrwr8(u8 val, void __iomem *mac, size_t offs)
{
void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
writeb(val, paddr);
}
#endif /* __ALTERA_TSE_H__ */ #endif /* __ALTERA_TSE_H__ */

108
drivers/net/ethernet/altera/altera_tse_ethtool.c
View File

@ -96,54 +96,89 @@ static void tse_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
u64 *buf) u64 *buf)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
u64 ext; u64 ext;
buf[0] = ioread32(&mac->frames_transmitted_ok); buf[0] = csrrd32(priv->mac_dev,
buf[1] = ioread32(&mac->frames_received_ok); tse_csroffs(frames_transmitted_ok));
buf[2] = ioread32(&mac->frames_check_sequence_errors); buf[1] = csrrd32(priv->mac_dev,
buf[3] = ioread32(&mac->alignment_errors); tse_csroffs(frames_received_ok));
buf[2] = csrrd32(priv->mac_dev,
tse_csroffs(frames_check_sequence_errors));
buf[3] = csrrd32(priv->mac_dev,
tse_csroffs(alignment_errors));
/* Extended aOctetsTransmittedOK counter */ /* Extended aOctetsTransmittedOK counter */
ext = (u64) ioread32(&mac->msb_octets_transmitted_ok) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->octets_transmitted_ok); tse_csroffs(msb_octets_transmitted_ok)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(octets_transmitted_ok));
buf[4] = ext; buf[4] = ext;
/* Extended aOctetsReceivedOK counter */ /* Extended aOctetsReceivedOK counter */
ext = (u64) ioread32(&mac->msb_octets_received_ok) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->octets_received_ok); tse_csroffs(msb_octets_received_ok)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(octets_received_ok));
buf[5] = ext; buf[5] = ext;
buf[6] = ioread32(&mac->tx_pause_mac_ctrl_frames); buf[6] = csrrd32(priv->mac_dev,
buf[7] = ioread32(&mac->rx_pause_mac_ctrl_frames); tse_csroffs(tx_pause_mac_ctrl_frames));
buf[8] = ioread32(&mac->if_in_errors); buf[7] = csrrd32(priv->mac_dev,
buf[9] = ioread32(&mac->if_out_errors); tse_csroffs(rx_pause_mac_ctrl_frames));
buf[10] = ioread32(&mac->if_in_ucast_pkts); buf[8] = csrrd32(priv->mac_dev,
buf[11] = ioread32(&mac->if_in_multicast_pkts); tse_csroffs(if_in_errors));
buf[12] = ioread32(&mac->if_in_broadcast_pkts); buf[9] = csrrd32(priv->mac_dev,
buf[13] = ioread32(&mac->if_out_discards); tse_csroffs(if_out_errors));
buf[14] = ioread32(&mac->if_out_ucast_pkts); buf[10] = csrrd32(priv->mac_dev,
buf[15] = ioread32(&mac->if_out_multicast_pkts); tse_csroffs(if_in_ucast_pkts));
buf[16] = ioread32(&mac->if_out_broadcast_pkts); buf[11] = csrrd32(priv->mac_dev,
buf[17] = ioread32(&mac->ether_stats_drop_events); tse_csroffs(if_in_multicast_pkts));
buf[12] = csrrd32(priv->mac_dev,
tse_csroffs(if_in_broadcast_pkts));
buf[13] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_discards));
buf[14] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_ucast_pkts));
buf[15] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_multicast_pkts));
buf[16] = csrrd32(priv->mac_dev,
tse_csroffs(if_out_broadcast_pkts));
buf[17] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_drop_events));
/* Extended etherStatsOctets counter */ /* Extended etherStatsOctets counter */
ext = (u64) ioread32(&mac->msb_ether_stats_octets) << 32; ext = (u64) csrrd32(priv->mac_dev,
ext |= ioread32(&mac->ether_stats_octets); tse_csroffs(msb_ether_stats_octets)) << 32;
ext |= csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_octets));
buf[18] = ext; buf[18] = ext;
buf[19] = ioread32(&mac->ether_stats_pkts); buf[19] = csrrd32(priv->mac_dev,
buf[20] = ioread32(&mac->ether_stats_undersize_pkts); tse_csroffs(ether_stats_pkts));
buf[21] = ioread32(&mac->ether_stats_oversize_pkts); buf[20] = csrrd32(priv->mac_dev,
buf[22] = ioread32(&mac->ether_stats_pkts_64_octets); tse_csroffs(ether_stats_undersize_pkts));
buf[23] = ioread32(&mac->ether_stats_pkts_65to127_octets); buf[21] = csrrd32(priv->mac_dev,
buf[24] = ioread32(&mac->ether_stats_pkts_128to255_octets); tse_csroffs(ether_stats_oversize_pkts));
buf[25] = ioread32(&mac->ether_stats_pkts_256to511_octets); buf[22] = csrrd32(priv->mac_dev,
buf[26] = ioread32(&mac->ether_stats_pkts_512to1023_octets); tse_csroffs(ether_stats_pkts_64_octets));
buf[27] = ioread32(&mac->ether_stats_pkts_1024to1518_octets); buf[23] = csrrd32(priv->mac_dev,
buf[28] = ioread32(&mac->ether_stats_pkts_1519tox_octets); tse_csroffs(ether_stats_pkts_65to127_octets));
buf[29] = ioread32(&mac->ether_stats_jabbers); buf[24] = csrrd32(priv->mac_dev,
buf[30] = ioread32(&mac->ether_stats_fragments); tse_csroffs(ether_stats_pkts_128to255_octets));
buf[25] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_256to511_octets));
buf[26] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_512to1023_octets));
buf[27] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_1024to1518_octets));
buf[28] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_pkts_1519tox_octets));
buf[29] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_jabbers));
buf[30] = csrrd32(priv->mac_dev,
tse_csroffs(ether_stats_fragments));
} }
static int tse_sset_count(struct net_device *dev, int sset) static int tse_sset_count(struct net_device *dev, int sset)
@ -178,7 +213,6 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs,
{ {
int i; int i;
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
u32 *tse_mac_regs = (u32 *)priv->mac_dev;
u32 *buf = regbuf; u32 *buf = regbuf;
/* Set version to a known value, so ethtool knows /* Set version to a known value, so ethtool knows
@ -196,7 +230,7 @@ static void tse_get_regs(struct net_device *dev, struct ethtool_regs *regs,
regs->version = 1; regs->version = 1;
for (i = 0; i < TSE_NUM_REGS; i++) for (i = 0; i < TSE_NUM_REGS; i++)
buf[i] = ioread32(&tse_mac_regs[i]); buf[i] = csrrd32(priv->mac_dev, i * 4);
} }
static int tse_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) static int tse_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)

128
drivers/net/ethernet/altera/altera_tse_main.c
View File

@ -100,29 +100,30 @@ static inline u32 tse_tx_avail(struct altera_tse_private *priv)
*/ */
static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum) static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{ {
struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv; struct net_device *ndev = bus->priv;
unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0; struct altera_tse_private *priv = netdev_priv(ndev);
u32 data;
/* set MDIO address */ /* set MDIO address */
iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr); csrwr32((mii_id & 0x1f), priv->mac_dev,
tse_csroffs(mdio_phy0_addr));
/* get the data */ /* get the data */
data = ioread32(&mdio_regs[regnum]) & 0xffff; return csrrd32(priv->mac_dev,
return data; tse_csroffs(mdio_phy0) + regnum * 4) & 0xffff;
} }
static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum, static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
u16 value) u16 value)
{ {
struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv; struct net_device *ndev = bus->priv;
unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0; struct altera_tse_private *priv = netdev_priv(ndev);
/* set MDIO address */ /* set MDIO address */
iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr); csrwr32((mii_id & 0x1f), priv->mac_dev,
tse_csroffs(mdio_phy0_addr));
/* write the data */ /* write the data */
iowrite32((u32) value, &mdio_regs[regnum]); csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy0) + regnum * 4);
return 0; return 0;
} }
@ -168,7 +169,7 @@ static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
for (i = 0; i < PHY_MAX_ADDR; i++) for (i = 0; i < PHY_MAX_ADDR; i++)
mdio->irq[i] = PHY_POLL; mdio->irq[i] = PHY_POLL;
mdio->priv = priv->mac_dev; mdio->priv = dev;
mdio->parent = priv->device; mdio->parent = priv->device;
ret = of_mdiobus_register(mdio, mdio_node); ret = of_mdiobus_register(mdio, mdio_node);
@ -563,7 +564,6 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
unsigned int nopaged_len = skb_headlen(skb); unsigned int nopaged_len = skb_headlen(skb);
enum netdev_tx ret = NETDEV_TX_OK; enum netdev_tx ret = NETDEV_TX_OK;
dma_addr_t dma_addr; dma_addr_t dma_addr;
int txcomplete = 0;
spin_lock_bh(&priv->tx_lock); spin_lock_bh(&priv->tx_lock);
@ -599,7 +599,7 @@ static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
dma_sync_single_for_device(priv->device, buffer->dma_addr, dma_sync_single_for_device(priv->device, buffer->dma_addr,
buffer->len, DMA_TO_DEVICE); buffer->len, DMA_TO_DEVICE);
txcomplete = priv->dmaops->tx_buffer(priv, buffer); priv->dmaops->tx_buffer(priv, buffer);
skb_tx_timestamp(skb); skb_tx_timestamp(skb);
@ -698,7 +698,6 @@ static struct phy_device *connect_local_phy(struct net_device *dev)
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct phy_device *phydev = NULL; struct phy_device *phydev = NULL;
char phy_id_fmt[MII_BUS_ID_SIZE + 3]; char phy_id_fmt[MII_BUS_ID_SIZE + 3];
int ret;
if (priv->phy_addr != POLL_PHY) { if (priv->phy_addr != POLL_PHY) {
snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
@ -712,6 +711,7 @@ static struct phy_device *connect_local_phy(struct net_device *dev)
netdev_err(dev, "Could not attach to PHY\n"); netdev_err(dev, "Could not attach to PHY\n");
} else { } else {
int ret;
phydev = phy_find_first(priv->mdio); phydev = phy_find_first(priv->mdio);
if (phydev == NULL) { if (phydev == NULL) {
netdev_err(dev, "No PHY found\n"); netdev_err(dev, "No PHY found\n");
@ -791,7 +791,6 @@ static int init_phy(struct net_device *dev)
static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr) static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
{ {
struct altera_tse_mac *mac = priv->mac_dev;
u32 msb; u32 msb;
u32 lsb; u32 lsb;
@ -799,8 +798,8 @@ static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
lsb = ((addr[5] << 8) | addr[4]) & 0xffff; lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
/* Set primary MAC address */ /* Set primary MAC address */
iowrite32(msb, &mac->mac_addr_0); csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0));
iowrite32(lsb, &mac->mac_addr_1); csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1));
} }
/* MAC software reset. /* MAC software reset.
@ -811,26 +810,26 @@ static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
*/ */
static int reset_mac(struct altera_tse_private *priv) static int reset_mac(struct altera_tse_private *priv)
{ {
void __iomem *cmd_cfg_reg = &priv->mac_dev->command_config;
int counter; int counter;
u32 dat; u32 dat;
dat = ioread32(cmd_cfg_reg); dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET; dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
iowrite32(dat, cmd_cfg_reg); csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
counter = 0; counter = 0;
while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
if (tse_bit_is_clear(cmd_cfg_reg, MAC_CMDCFG_SW_RESET)) if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config),
MAC_CMDCFG_SW_RESET))
break; break;
udelay(1); udelay(1);
} }
if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
dat = ioread32(cmd_cfg_reg); dat = csrrd32(priv->mac_dev, tse_csroffs(command_config));
dat &= ~MAC_CMDCFG_SW_RESET; dat &= ~MAC_CMDCFG_SW_RESET;
iowrite32(dat, cmd_cfg_reg); csrwr32(dat, priv->mac_dev, tse_csroffs(command_config));
return -1; return -1;
} }
return 0; return 0;
@ -840,41 +839,57 @@ static int reset_mac(struct altera_tse_private *priv)
*/ */
static int init_mac(struct altera_tse_private *priv) static int init_mac(struct altera_tse_private *priv)
{ {
struct altera_tse_mac *mac = priv->mac_dev;
unsigned int cmd = 0; unsigned int cmd = 0;
u32 frm_length; u32 frm_length;
/* Setup Rx FIFO */ /* Setup Rx FIFO */
iowrite32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY, csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
&mac->rx_section_empty); priv->mac_dev, tse_csroffs(rx_section_empty));
iowrite32(ALTERA_TSE_RX_SECTION_FULL, &mac->rx_section_full);
iowrite32(ALTERA_TSE_RX_ALMOST_EMPTY, &mac->rx_almost_empty); csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev,
iowrite32(ALTERA_TSE_RX_ALMOST_FULL, &mac->rx_almost_full); tse_csroffs(rx_section_full));
csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev,
tse_csroffs(rx_almost_empty));
csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev,
tse_csroffs(rx_almost_full));
/* Setup Tx FIFO */ /* Setup Tx FIFO */
iowrite32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY, csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
&mac->tx_section_empty); priv->mac_dev, tse_csroffs(tx_section_empty));
iowrite32(ALTERA_TSE_TX_SECTION_FULL, &mac->tx_section_full);
iowrite32(ALTERA_TSE_TX_ALMOST_EMPTY, &mac->tx_almost_empty); csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev,
iowrite32(ALTERA_TSE_TX_ALMOST_FULL, &mac->tx_almost_full); tse_csroffs(tx_section_full));
csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev,
tse_csroffs(tx_almost_empty));
csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev,
tse_csroffs(tx_almost_full));
/* MAC Address Configuration */ /* MAC Address Configuration */
tse_update_mac_addr(priv, priv->dev->dev_addr); tse_update_mac_addr(priv, priv->dev->dev_addr);
/* MAC Function Configuration */ /* MAC Function Configuration */
frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN; frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
iowrite32(frm_length, &mac->frm_length); csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length));
iowrite32(ALTERA_TSE_TX_IPG_LENGTH, &mac->tx_ipg_length);
csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev,
tse_csroffs(tx_ipg_length));
/* Disable RX/TX shift 16 for alignment of all received frames on 16-bit /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
* start address * start address
*/ */
tse_set_bit(&mac->rx_cmd_stat, ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16); tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat),
tse_clear_bit(&mac->tx_cmd_stat, ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 | ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat),
ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
/* Set the MAC options */ /* Set the MAC options */
cmd = ioread32(&mac->command_config); cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config));
cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */ cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */ cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
@ -889,9 +904,10 @@ static int init_mac(struct altera_tse_private *priv)
cmd &= ~MAC_CMDCFG_ETH_SPEED; cmd &= ~MAC_CMDCFG_ETH_SPEED;
cmd &= ~MAC_CMDCFG_ENA_10; cmd &= ~MAC_CMDCFG_ENA_10;
iowrite32(cmd, &mac->command_config); csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config));
iowrite32(ALTERA_TSE_PAUSE_QUANTA, &mac->pause_quanta); csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev,
tse_csroffs(pause_quanta));
if (netif_msg_hw(priv)) if (netif_msg_hw(priv))
dev_dbg(priv->device, dev_dbg(priv->device,
@ -904,15 +920,14 @@ static int init_mac(struct altera_tse_private *priv)
*/ */
static void tse_set_mac(struct altera_tse_private *priv, bool enable) static void tse_set_mac(struct altera_tse_private *priv, bool enable)
{ {
struct altera_tse_mac *mac = priv->mac_dev; u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config));
u32 value = ioread32(&mac->command_config);
if (enable) if (enable)
value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA; value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
else else
value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
iowrite32(value, &mac->command_config); csrwr32(value, priv->mac_dev, tse_csroffs(command_config));
} }
/* Change the MTU /* Change the MTU
@ -942,13 +957,12 @@ static int tse_change_mtu(struct net_device *dev, int new_mtu)
static void altera_tse_set_mcfilter(struct net_device *dev) static void altera_tse_set_mcfilter(struct net_device *dev)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
int i; int i;
struct netdev_hw_addr *ha; struct netdev_hw_addr *ha;
/* clear the hash filter */ /* clear the hash filter */
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
iowrite32(0, &(mac->hash_table[i])); csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
netdev_for_each_mc_addr(ha, dev) { netdev_for_each_mc_addr(ha, dev) {
unsigned int hash = 0; unsigned int hash = 0;
@ -964,7 +978,7 @@ static void altera_tse_set_mcfilter(struct net_device *dev)
hash = (hash << 1) | xor_bit; hash = (hash << 1) | xor_bit;
} }
iowrite32(1, &(mac->hash_table[hash])); csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4);
} }
} }
@ -972,12 +986,11 @@ static void altera_tse_set_mcfilter(struct net_device *dev)
static void altera_tse_set_mcfilterall(struct net_device *dev) static void altera_tse_set_mcfilterall(struct net_device *dev)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
int i; int i;
/* set the hash filter */ /* set the hash filter */
for (i = 0; i < 64; i++) for (i = 0; i < 64; i++)
iowrite32(1, &(mac->hash_table[i])); csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4);
} }
/* Set or clear the multicast filter for this adaptor /* Set or clear the multicast filter for this adaptor
@ -985,12 +998,12 @@ static void altera_tse_set_mcfilterall(struct net_device *dev)
static void tse_set_rx_mode_hashfilter(struct net_device *dev) static void tse_set_rx_mode_hashfilter(struct net_device *dev)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
spin_lock(&priv->mac_cfg_lock); spin_lock(&priv->mac_cfg_lock);
if (dev->flags & IFF_PROMISC) if (dev->flags & IFF_PROMISC)
tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN); tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
MAC_CMDCFG_PROMIS_EN);
if (dev->flags & IFF_ALLMULTI) if (dev->flags & IFF_ALLMULTI)
altera_tse_set_mcfilterall(dev); altera_tse_set_mcfilterall(dev);
@ -1005,15 +1018,16 @@ static void tse_set_rx_mode_hashfilter(struct net_device *dev)
static void tse_set_rx_mode(struct net_device *dev) static void tse_set_rx_mode(struct net_device *dev)
{ {
struct altera_tse_private *priv = netdev_priv(dev); struct altera_tse_private *priv = netdev_priv(dev);
struct altera_tse_mac *mac = priv->mac_dev;
spin_lock(&priv->mac_cfg_lock); spin_lock(&priv->mac_cfg_lock);
if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) || if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
!netdev_mc_empty(dev) || !netdev_uc_empty(dev)) !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN); tse_set_bit(priv->mac_dev, tse_csroffs(command_config),
MAC_CMDCFG_PROMIS_EN);
else else
tse_clear_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN); tse_clear_bit(priv->mac_dev, tse_csroffs(command_config),
MAC_CMDCFG_PROMIS_EN);
spin_unlock(&priv->mac_cfg_lock); spin_unlock(&priv->mac_cfg_lock);
} }
@ -1493,7 +1507,7 @@ static int altera_tse_remove(struct platform_device *pdev)
return 0; return 0;
} }
struct altera_dmaops altera_dtype_sgdma = { static const struct altera_dmaops altera_dtype_sgdma = {
.altera_dtype = ALTERA_DTYPE_SGDMA, .altera_dtype = ALTERA_DTYPE_SGDMA,
.dmamask = 32, .dmamask = 32,
.reset_dma = sgdma_reset, .reset_dma = sgdma_reset,
@ -1512,7 +1526,7 @@ struct altera_dmaops altera_dtype_sgdma = {
.start_rxdma = sgdma_start_rxdma, .start_rxdma = sgdma_start_rxdma,
}; };
struct altera_dmaops altera_dtype_msgdma = { static const struct altera_dmaops altera_dtype_msgdma = {
.altera_dtype = ALTERA_DTYPE_MSGDMA, .altera_dtype = ALTERA_DTYPE_MSGDMA,
.dmamask = 64, .dmamask = 64,
.reset_dma = msgdma_reset, .reset_dma = msgdma_reset,

20
drivers/net/ethernet/altera/altera_utils.c
View File

@ -17,28 +17,28 @@
#include "altera_tse.h" #include "altera_tse.h"
#include "altera_utils.h" #include "altera_utils.h"
void tse_set_bit(void __iomem *ioaddr, u32 bit_mask) void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
value |= bit_mask; value |= bit_mask;
iowrite32(value, ioaddr); csrwr32(value, ioaddr, offs);
} }
void tse_clear_bit(void __iomem *ioaddr, u32 bit_mask) void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
value &= ~bit_mask; value &= ~bit_mask;
iowrite32(value, ioaddr); csrwr32(value, ioaddr, offs);
} }
int tse_bit_is_set(void __iomem *ioaddr, u32 bit_mask) int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
return (value & bit_mask) ? 1 : 0; return (value & bit_mask) ? 1 : 0;
} }
int tse_bit_is_clear(void __iomem *ioaddr, u32 bit_mask) int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask)
{ {
u32 value = ioread32(ioaddr); u32 value = csrrd32(ioaddr, offs);
return (value & bit_mask) ? 0 : 1; return (value & bit_mask) ? 0 : 1;
} }

8
drivers/net/ethernet/altera/altera_utils.h
View File

@ -19,9 +19,9 @@
#ifndef __ALTERA_UTILS_H__ #ifndef __ALTERA_UTILS_H__
#define __ALTERA_UTILS_H__ #define __ALTERA_UTILS_H__
void tse_set_bit(void __iomem *ioaddr, u32 bit_mask); void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
void tse_clear_bit(void __iomem *ioaddr, u32 bit_mask); void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask);
int tse_bit_is_set(void __iomem *ioaddr, u32 bit_mask); int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask);
int tse_bit_is_clear(void __iomem *ioaddr, u32 bit_mask); int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask);
#endif /* __ALTERA_UTILS_H__*/ #endif /* __ALTERA_UTILS_H__*/