forked from Minki/linux
V4L/DVB (11865): cx18: Tweak color burst gate delay and initial color sub-carrier freq
Fix the burst gate delays to use a crystal value of 28636360 as assumed by the rest of the driver. Also have the initial color sub-carrier freq paramter use the src decimation ratio per the documentation, instead of the actual crystal/pixel clock ratio. The tracking circuit will find the correct color subcarrier in any case, as long as we're close. Also fix up some debug print statements. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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929a3ad152
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@ -277,8 +277,15 @@ void cx18_av_std_setup(struct cx18 *cx)
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struct cx18_av_state *state = &cx->av_state;
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struct v4l2_subdev *sd = &state->sd;
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v4l2_std_id std = state->std;
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/*
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* Video ADC crystal clock to pixel clock SRC decimation ratio
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* 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
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*/
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const int src_decimation = 0x21f;
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int hblank, hactive, burst, vblank, vactive, sc;
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int vblank656, src_decimation;
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int vblank656;
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int luma_lpf, uv_lpf, comb;
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u32 pll_int, pll_frac, pll_post;
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@ -342,21 +349,31 @@ void cx18_av_std_setup(struct cx18 *cx)
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hblank = 132;
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hactive = 720;
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/*
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* Burst gate delay (for 625 line systems)
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* Hsync leading edge to color burst rise = 5.6 us
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* Color burst width = 2.25 us
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* Gate width = 4 pixel clocks
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* (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
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*/
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burst = 93;
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luma_lpf = 2;
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src_decimation = 0x21f;
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if (std & V4L2_STD_PAL) {
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uv_lpf = 1;
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comb = 0x20;
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sc = 688739;
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/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
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sc = 688700;
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} else if (std == V4L2_STD_PAL_Nc) {
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uv_lpf = 1;
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comb = 0x20;
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sc = 556453;
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/* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
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sc = 556422;
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} else { /* SECAM */
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uv_lpf = 0;
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comb = 0;
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sc = 672351;
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/* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
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/* sc = 4328130 * src_decimation/28636360 * 2^13 */
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sc = 672314;
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}
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} else {
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/*
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@ -394,20 +411,30 @@ void cx18_av_std_setup(struct cx18 *cx)
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luma_lpf = 1;
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uv_lpf = 1;
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src_decimation = 0x21f;
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/*
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* Burst gate delay (for 525 line systems)
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* Hsync leading edge to color burst rise = 5.3 us
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* Color burst width = 2.5 us
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* Gate width = 4 pixel clocks
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* (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
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*/
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if (std == V4L2_STD_PAL_60) {
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burst = 0x5b;
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burst = 90;
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luma_lpf = 2;
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comb = 0x20;
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sc = 688739;
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/* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
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sc = 688700;
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} else if (std == V4L2_STD_PAL_M) {
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burst = 0x61;
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/* The 97 needs to be verified against PAL-M timings */
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burst = 97;
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comb = 0x20;
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sc = 555452;
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/* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
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sc = 555421;
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} else {
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burst = 0x5b;
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burst = 90;
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comb = 0x66;
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sc = 556063;
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/* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
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sc = 556032;
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}
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}
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@ -419,23 +446,23 @@ void cx18_av_std_setup(struct cx18 *cx)
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pll_int, pll_frac, pll_post);
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if (pll_post) {
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int fin, fsc, pll;
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int fsc, pll;
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pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
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pll /= pll_post;
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CX18_DEBUG_INFO_DEV(sd, "PLL = %d.%06d MHz\n",
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CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
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pll / 1000000, pll % 1000000);
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CX18_DEBUG_INFO_DEV(sd, "PLL/8 = %d.%06d MHz\n",
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CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
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pll / 8000000, (pll / 8) % 1000000);
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fin = ((u64)src_decimation * pll) >> 12;
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CX18_DEBUG_INFO_DEV(sd, "ADC Sampling freq = %d.%06d MHz\n",
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fin / 1000000, fin % 1000000);
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CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio "
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"= %d.%03d\n", src_decimation / 256,
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((src_decimation % 256) * 1000) / 256);
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fsc = (((u64)sc) * pll) >> 24L;
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fsc = ((((u64)sc) * 28636360)/src_decimation) >> 13L;
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CX18_DEBUG_INFO_DEV(sd,
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"Chroma sub-carrier freq = %d.%06d MHz\n",
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fsc / 1000000, fsc % 1000000);
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"Chroma sub-carrier initial freq = %d.%06d "
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"MHz\n", fsc / 1000000, fsc % 1000000);
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CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
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"vactive %i, vblank656 %i, src_dec %i, "
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