drm/amdgpu/psp: move TMR to cpu invisible vram region
so that more visible vram can be available for umd. Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -246,8 +246,9 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
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bp.size = size;
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bp.size = size;
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bp.byte_align = align;
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bp.byte_align = align;
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bp.domain = domain;
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bp.domain = domain;
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bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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: AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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bp.type = ttm_bo_type_kernel;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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bp.resv = NULL;
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@@ -263,7 +263,7 @@ static int psp_tmr_init(struct psp_context *psp)
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ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
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ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_DOMAIN_VRAM,
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&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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&psp->tmr_bo, &psp->tmr_mc_addr, NULL);
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return ret;
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return ret;
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}
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}
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@@ -1216,7 +1216,7 @@ static int psp_hw_fini(void *handle)
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psp_ring_destroy(psp, PSP_RING_TYPE__KM);
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psp_ring_destroy(psp, PSP_RING_TYPE__KM);
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amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
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amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, NULL);
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amdgpu_bo_free_kernel(&psp->fw_pri_bo,
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amdgpu_bo_free_kernel(&psp->fw_pri_bo,
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&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
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&psp->fw_pri_mc_addr, &psp->fw_pri_buf);
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amdgpu_bo_free_kernel(&psp->fence_buf_bo,
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amdgpu_bo_free_kernel(&psp->fence_buf_bo,
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@@ -171,7 +171,6 @@ struct psp_context
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/* tmr buffer */
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/* tmr buffer */
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struct amdgpu_bo *tmr_bo;
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struct amdgpu_bo *tmr_bo;
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uint64_t tmr_mc_addr;
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uint64_t tmr_mc_addr;
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void *tmr_buf;
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/* asd firmware and buffer */
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/* asd firmware and buffer */
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const struct firmware *asd_fw;
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const struct firmware *asd_fw;
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