forked from Minki/linux
Clean up to make it easier to add support for new SoCs.
Note that these have a merge dependency to omap-devel-hwmod-for-v3.5 branch for the Makefile changes. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJPq/EJAAoJEBvUPslcq6VzYQ8P/06IfUodVZD1d+hUoE6Ptkfc EeXrEZkbSn7TmY3dgVzVldQHbjIzaU7nK3Bo7GbNbrOKomSCPgvCNTPbmz+6S0fp nrB9dukmvGVlG5EN935PVdF/1CRmMdWdGD7BsGqUTezORX4IkC6KqoorHtxhZ5jt hhQm3fxDfo3+ORSqcKYOF9p+ojFuchTXr3Jn78yp4gVFLQzH8V1tCaYkMwQDbAh9 gH7Bnmnk/WNemGlWyud3L6ccFM/cPSp94/54Uo3XEPYOrxi6KZG4jOlh67RailKd 8MROCJpHENhagjM4XISkcjLjdE6emQ/cAMxYPWr05D9wXUPWrLPCubHbF+oWNwe0 cUT15qF8jxfbxb+IQwoQVfcEVc4AjUJVlgZ3abuu+wku3CpDbJnMjyNoYeEBMy4L bOXiuFm0q4Ku0Yc/mrSgD6O06GA8uG/DgPEF59iFf7uBeGjWLG9pN5G3ndPmHE9R 90CKrj3Zxt1DBP4vEzaH1+SnHmpJ1MGQstLduYxW59CT7DZKJICXI8EAl4y+4juR 8Flog1KuH3J/LM1s4uM4rtop2nyh42e2Ns0/KWny6cbFtSrUXkiiIe1uSxyLRBmI H8BnOuq3SszBxSb7ATmTZfttxVOm6puqg6VqE8q4lvV0+9Cs07TGnDP63nvOOnbD 9PLBwBut+tsUW1WBKyM9 =V/Lo -----END PGP SIGNATURE----- Merge tag 'omap-cleanup-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup2 Clean up to make it easier to add support for new SoCs. Note that these have a merge dependency to omap-devel-hwmod-for-v3.5 branch for the Makefile changes. By Paul Walmsley (37) and others via Tony Lindgren * tag 'omap-cleanup-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (55 commits) GPMC: add ECC control definitions ARM: OMAP2+: dmtimer: remove redundant sysconfig context restore ARM: OMAP: AM35xx: convert 3517 detection/flags to AM35xx ARM: OMAP: AM35xx: remove redunant cpu_is checks for AM3505 ARM: OMAP2+: dma: Define dma capabilities register bitfields and use them. ARM: OMAP4: Reduce the static IO mapping ARM: All OMAP2PLUS machines use omap2 directory so just add one entry ARM: OMAP: dma: Make use of cpu_class_is_omap2() to avoid future patching. ARM: OMAP4: Remove un-used WakeupGen register defines. ARM: OMAP2+: Clean up wrapping multiple objects in Makefile ARM: OMAP4: Don't compile cm2xxx_3xxx.c for OMAP4 only builds. ARM: OMAP4: hwmod data: add DEBUGSS skeleton ARM: OMAP4: hwmod data: add PRCM and related IP blocks ARM: OMAP4: hwmod data: add System Control Module ARM: OMAP4: hwmod data: add the OCP-WP IP block ARM: OMAP4: hwmod data: add OCM RAM IP block ARM: OMAP4: hwmod data: add remaining USB-related IP blocks ARM: OMAP4: hwmod data: add some interconnect-related IP blocks ARM: OMAP4: hwmod data: add McASP ARM: OMAP4: hwmod data: add the Slimbus IP blocks ...
This commit is contained in:
Olof Johansson
commit
812655e9c1
@ -164,9 +164,7 @@ machine-$(CONFIG_ARCH_MXS) := mxs
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machine-$(CONFIG_ARCH_NETX) := netx
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machine-$(CONFIG_ARCH_NOMADIK) := nomadik
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machine-$(CONFIG_ARCH_OMAP1) := omap1
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machine-$(CONFIG_ARCH_OMAP2) := omap2
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machine-$(CONFIG_ARCH_OMAP3) := omap2
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machine-$(CONFIG_ARCH_OMAP4) := omap2
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machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2
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machine-$(CONFIG_ARCH_ORION5X) := orion5x
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machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
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machine-$(CONFIG_ARCH_PNX4008) := pnx4008
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@ -24,10 +24,11 @@ endif
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obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
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# SMP support ONLY available for OMAP4
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obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
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obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o \
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sleep44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
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obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
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plus_sec := $(call as-instr,.arch_extension sec,+sec)
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AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
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@ -64,10 +65,10 @@ endif
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ifeq ($(CONFIG_PM),y)
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obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
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obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
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obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
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cpuidle34xx.o
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obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o \
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cpuidle44xx.o
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obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
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obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
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obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
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obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
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obj-$(CONFIG_PM_DEBUG) += pm-debug.o
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obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o
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obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o
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@ -84,88 +85,86 @@ endif
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# PRCM
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obj-y += prm_common.o
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obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
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vc3xxx_data.o vp3xxx_data.o
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# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
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# will be removed once the OMAP4 part of the codebase is converted to
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# use OMAP4-specific PRCM functions.
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obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cminst44xx.o \
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cm44xx.o prcm_mpu44xx.o \
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prminst44xx.o vc44xx_data.o \
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vp44xx_data.o prm44xx.o
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obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
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# OMAP voltage domains
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voltagedomain-common := voltage.o vc.o vp.o
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obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) \
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voltagedomains2xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) \
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voltagedomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) \
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voltagedomains44xx_data.o
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obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
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obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
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obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
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# OMAP powerdomain framework
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powerdomain-common += powerdomain.o powerdomain-common.o
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obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) \
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powerdomain2xxx_3xxx.o \
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powerdomains2xxx_data.o \
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powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) \
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powerdomain2xxx_3xxx.o \
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powerdomains3xxx_data.o \
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powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) \
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powerdomain44xx.o \
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powerdomains44xx_data.o
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obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
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obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
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obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
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obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
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# PRCM clockdomain control
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obj-$(CONFIG_ARCH_OMAP2) += clockdomain.o \
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clockdomain2xxx_3xxx.o \
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clockdomains2xxx_3xxx_data.o
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clockdomain-common += clockdomain.o
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clockdomain-common += clockdomains_common_data.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
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obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += clockdomain.o \
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clockdomain2xxx_3xxx.o \
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clockdomains2xxx_3xxx_data.o \
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clockdomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += clockdomain.o \
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clockdomain44xx.o \
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clockdomains44xx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
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obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
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obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
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# Clock framework
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obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
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clkt2xxx_sys.o \
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clkt2xxx_dpllcore.o \
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clkt2xxx_virt_prcm_set.o \
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clkt2xxx_apll.o clkt2xxx_osc.o \
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clkt2xxx_dpll.o clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
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obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
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obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
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clock34xx.o clkt34xx_dpll3m2.o \
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clock3517.o clock36xx.o \
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dpll3xxx.o clock3xxx_data.o \
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clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
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dpll3xxx.o dpll44xx.o
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obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
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obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
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obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
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obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
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obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
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# OMAP2 clock rate set data (old "OPP" data)
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obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
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# hwmod data
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_interconnect_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
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omap_hwmod_2xxx_3xxx_interconnect_data.o \
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omap_hwmod_3xxx_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_interconnect_data.o
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obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
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obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
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# EMU peripherals
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@ -203,23 +202,19 @@ obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
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obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
|
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obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
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obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
|
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obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o \
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sdram-nokia.o
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obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
|
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sdram-nokia.o \
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board-rx51-peripherals.o \
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board-rx51-video.o
|
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obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \
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board-zoom-peripherals.o \
|
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board-zoom-display.o \
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board-zoom-debugboard.o
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obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \
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board-zoom-peripherals.o \
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||||
board-zoom-display.o \
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||||
board-zoom-debugboard.o
|
||||
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o \
|
||||
board-zoom-peripherals.o \
|
||||
board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RM680) += board-rm680.o sdram-nokia.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
|
||||
obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-video.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o board-zoom-peripherals.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom-debugboard.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o board-zoom-peripherals.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom-debugboard.o
|
||||
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-3630sdp.o
|
||||
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-peripherals.o
|
||||
obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o
|
||||
obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o
|
||||
obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o
|
||||
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o
|
||||
|
||||
@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
|
||||
struct clkdm_dep *cd;
|
||||
u32 mask = 0;
|
||||
|
||||
if (!clkdm->prcm_partition)
|
||||
return 0;
|
||||
|
||||
for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
|
||||
if (!cd->clkdm)
|
||||
continue; /* only happens if data is erroneous */
|
||||
@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
|
||||
{
|
||||
bool hwsup = false;
|
||||
|
||||
if (!clkdm->prcm_partition)
|
||||
return 0;
|
||||
|
||||
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
|
||||
clkdm->cm_inst, clkdm->clkdm_offs);
|
||||
|
||||
|
||||
@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
|
||||
.pwrdm = { .name = "wkup_pwrdm" },
|
||||
.dep_bit = OMAP_EN_WKUP_SHIFT,
|
||||
};
|
||||
|
||||
struct clockdomain prm_common_clkdm = {
|
||||
.name = "prm_clkdm",
|
||||
.pwrdm = { .name = "wkup_pwrdm" },
|
||||
};
|
||||
|
||||
struct clockdomain cm_common_clkdm = {
|
||||
.name = "cm_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
};
|
||||
|
||||
@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
|
||||
&l4_wkup_44xx_clkdm,
|
||||
&emu_sys_44xx_clkdm,
|
||||
&l3_dma_44xx_clkdm,
|
||||
&prm_common_clkdm,
|
||||
&cm_common_clkdm,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
24
arch/arm/mach-omap2/clockdomains_common_data.c
Normal file
24
arch/arm/mach-omap2/clockdomains_common_data.c
Normal file
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* OMAP2+-common clockdomain data
|
||||
*
|
||||
* Copyright (C) 2008-2012 Texas Instruments, Inc.
|
||||
* Copyright (C) 2008-2010 Nokia Corporation
|
||||
*
|
||||
* Paul Walmsley, Jouni Högander
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "clockdomain.h"
|
||||
|
||||
/* These are implicit clockdomains - they are never defined as such in TRM */
|
||||
struct clockdomain prm_common_clkdm = {
|
||||
.name = "prm_clkdm",
|
||||
.pwrdm = { .name = "wkup_pwrdm" },
|
||||
};
|
||||
|
||||
struct clockdomain cm_common_clkdm = {
|
||||
.name = "cm_clkdm",
|
||||
.pwrdm = { .name = "core_pwrdm" },
|
||||
};
|
||||
@ -227,10 +227,6 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
|
||||
dma_stride = OMAP2_DMA_STRIDE;
|
||||
dma_common_ch_start = CSDP;
|
||||
if (cpu_is_omap3630() || cpu_is_omap44xx())
|
||||
dma_common_ch_end = CCDN;
|
||||
else
|
||||
dma_common_ch_end = CCFN;
|
||||
|
||||
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
|
||||
if (!p) {
|
||||
@ -277,6 +273,13 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
|
||||
dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Check the capabilities register for descriptor loading feature */
|
||||
if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
|
||||
dma_common_ch_end = CCDN;
|
||||
else
|
||||
dma_common_ch_end = CCFN;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -50,6 +50,19 @@
|
||||
#define GPMC_ECC_SIZE_CONFIG 0x1fc
|
||||
#define GPMC_ECC1_RESULT 0x200
|
||||
|
||||
/* GPMC ECC control settings */
|
||||
#define GPMC_ECC_CTRL_ECCCLEAR 0x100
|
||||
#define GPMC_ECC_CTRL_ECCDISABLE 0x000
|
||||
#define GPMC_ECC_CTRL_ECCREG1 0x001
|
||||
#define GPMC_ECC_CTRL_ECCREG2 0x002
|
||||
#define GPMC_ECC_CTRL_ECCREG3 0x003
|
||||
#define GPMC_ECC_CTRL_ECCREG4 0x004
|
||||
#define GPMC_ECC_CTRL_ECCREG5 0x005
|
||||
#define GPMC_ECC_CTRL_ECCREG6 0x006
|
||||
#define GPMC_ECC_CTRL_ECCREG7 0x007
|
||||
#define GPMC_ECC_CTRL_ECCREG8 0x008
|
||||
#define GPMC_ECC_CTRL_ECCREG9 0x009
|
||||
|
||||
#define GPMC_CS0_OFFSET 0x60
|
||||
#define GPMC_CS_SIZE 0x30
|
||||
|
||||
@ -861,8 +874,9 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
|
||||
gpmc_ecc_used = cs;
|
||||
|
||||
/* clear ecc and enable bits */
|
||||
val = ((0x00000001<<8) | 0x00000001);
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL, val);
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL,
|
||||
GPMC_ECC_CTRL_ECCCLEAR |
|
||||
GPMC_ECC_CTRL_ECCREG1);
|
||||
|
||||
/* program ecc and result sizes */
|
||||
val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
|
||||
@ -870,13 +884,15 @@ int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
|
||||
|
||||
switch (mode) {
|
||||
case GPMC_ECC_READ:
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
|
||||
case GPMC_ECC_WRITE:
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL,
|
||||
GPMC_ECC_CTRL_ECCCLEAR |
|
||||
GPMC_ECC_CTRL_ECCREG1);
|
||||
break;
|
||||
case GPMC_ECC_READSYN:
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL, 0x100);
|
||||
break;
|
||||
case GPMC_ECC_WRITE:
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
|
||||
gpmc_write_reg(GPMC_ECC_CONTROL,
|
||||
GPMC_ECC_CTRL_ECCCLEAR |
|
||||
GPMC_ECC_CTRL_ECCDISABLE);
|
||||
break;
|
||||
default:
|
||||
printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
|
||||
|
||||
@ -355,7 +355,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
*
|
||||
* temporary HACK: ocr_mask instead of fixed supply
|
||||
*/
|
||||
if (cpu_is_omap3505() || cpu_is_omap3517())
|
||||
if (soc_is_am35xx())
|
||||
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
|
||||
MMC_VDD_26_27 |
|
||||
MMC_VDD_27_28 |
|
||||
@ -365,7 +365,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
else
|
||||
mmc->slots[0].ocr_mask = c->ocr_mask;
|
||||
|
||||
if (!cpu_is_omap3517() && !cpu_is_omap3505())
|
||||
if (!soc_is_am35xx())
|
||||
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
|
||||
|
||||
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
|
||||
@ -388,7 +388,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505())
|
||||
if (soc_is_am35xx())
|
||||
mmc->slots[0].set_power = nop_mmc_set_power;
|
||||
|
||||
/* OMAP3630 HSMMC1 supports only 4-bit */
|
||||
@ -400,7 +400,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505())
|
||||
if (soc_is_am35xx())
|
||||
mmc->slots[0].set_power = am35x_hsmmc2_set_power;
|
||||
|
||||
if (c->ext_clock)
|
||||
|
||||
@ -185,8 +185,7 @@ static void __init omap3_cpuinfo(void)
|
||||
*/
|
||||
if (cpu_is_omap3630()) {
|
||||
cpu_name = "OMAP3630";
|
||||
} else if (cpu_is_omap3517()) {
|
||||
/* AM35xx devices */
|
||||
} else if (soc_is_am35xx()) {
|
||||
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
|
||||
} else if (cpu_is_ti816x()) {
|
||||
cpu_name = "TI816X";
|
||||
@ -352,13 +351,13 @@ void __init omap3xxx_check_revision(void)
|
||||
*/
|
||||
switch (rev) {
|
||||
case 0:
|
||||
omap_revision = OMAP3517_REV_ES1_0;
|
||||
omap_revision = AM35XX_REV_ES1_0;
|
||||
cpu_rev = "1.0";
|
||||
break;
|
||||
case 1:
|
||||
/* FALLTHROUGH */
|
||||
default:
|
||||
omap_revision = OMAP3517_REV_ES1_1;
|
||||
omap_revision = AM35XX_REV_ES1_1;
|
||||
cpu_rev = "1.1";
|
||||
}
|
||||
break;
|
||||
|
||||
@ -16,18 +16,10 @@
|
||||
#define OMAP_WKG_ENB_B_0 0x14
|
||||
#define OMAP_WKG_ENB_C_0 0x18
|
||||
#define OMAP_WKG_ENB_D_0 0x1c
|
||||
#define OMAP_WKG_ENB_SECURE_A_0 0x20
|
||||
#define OMAP_WKG_ENB_SECURE_B_0 0x24
|
||||
#define OMAP_WKG_ENB_SECURE_C_0 0x28
|
||||
#define OMAP_WKG_ENB_SECURE_D_0 0x2c
|
||||
#define OMAP_WKG_ENB_A_1 0x410
|
||||
#define OMAP_WKG_ENB_B_1 0x414
|
||||
#define OMAP_WKG_ENB_C_1 0x418
|
||||
#define OMAP_WKG_ENB_D_1 0x41c
|
||||
#define OMAP_WKG_ENB_SECURE_A_1 0x420
|
||||
#define OMAP_WKG_ENB_SECURE_B_1 0x424
|
||||
#define OMAP_WKG_ENB_SECURE_C_1 0x428
|
||||
#define OMAP_WKG_ENB_SECURE_D_1 0x42c
|
||||
#define OMAP_AUX_CORE_BOOT_0 0x800
|
||||
#define OMAP_AUX_CORE_BOOT_1 0x804
|
||||
#define OMAP_PTMSYNCREQ_MASK 0xc00
|
||||
|
||||
@ -214,42 +214,12 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
|
||||
.length = L4_44XX_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = OMAP44XX_GPMC_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
|
||||
.length = OMAP44XX_GPMC_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = OMAP44XX_EMIF1_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
|
||||
.length = OMAP44XX_EMIF1_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = OMAP44XX_EMIF2_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
|
||||
.length = OMAP44XX_EMIF2_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = OMAP44XX_DMM_VIRT,
|
||||
.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
|
||||
.length = OMAP44XX_DMM_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = L4_PER_44XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
|
||||
.length = L4_PER_44XX_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
{
|
||||
.virtual = L4_EMU_44XX_VIRT,
|
||||
.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
|
||||
.length = L4_EMU_44XX_SIZE,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
#ifdef CONFIG_OMAP4_ERRATA_I688
|
||||
{
|
||||
.virtual = OMAP4_SRAM_VA,
|
||||
|
||||
@ -37,9 +37,6 @@
|
||||
#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
|
||||
#define OMAP4_L3_PER_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
|
||||
|
||||
#define OMAP4_GPMC_IO_OFFSET 0xa9000000
|
||||
#define OMAP4_GPMC_IO_ADDRESS(pa) IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
|
||||
|
||||
#define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
|
||||
#define OMAP2_EMU_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
|
||||
|
||||
@ -170,28 +167,3 @@
|
||||
#define L4_ABE_44XX_VIRT (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
|
||||
#define L4_ABE_44XX_SIZE SZ_1M
|
||||
|
||||
#define L4_EMU_44XX_PHYS L4_EMU_44XX_BASE
|
||||
/* 0x54000000 --> 0xfe800000 */
|
||||
#define L4_EMU_44XX_VIRT (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
|
||||
#define L4_EMU_44XX_SIZE SZ_8M
|
||||
|
||||
#define OMAP44XX_GPMC_PHYS OMAP44XX_GPMC_BASE
|
||||
/* 0x50000000 --> 0xf9000000 */
|
||||
#define OMAP44XX_GPMC_VIRT (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
|
||||
#define OMAP44XX_GPMC_SIZE SZ_1M
|
||||
|
||||
|
||||
#define OMAP44XX_EMIF1_PHYS OMAP44XX_EMIF1_BASE
|
||||
/* 0x4c000000 --> 0xfd100000 */
|
||||
#define OMAP44XX_EMIF1_VIRT (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
|
||||
#define OMAP44XX_EMIF1_SIZE SZ_1M
|
||||
|
||||
#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
|
||||
/* 0x4d000000 --> 0xfd200000 */
|
||||
#define OMAP44XX_EMIF2_SIZE SZ_1M
|
||||
#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
|
||||
|
||||
#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
|
||||
/* 0x4e000000 --> 0xfd300000 */
|
||||
#define OMAP44XX_DMM_SIZE SZ_1M
|
||||
#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -15,10 +15,12 @@
|
||||
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/l3_2xxx.h>
|
||||
#include <plat/l4_2xxx.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART1_BASE,
|
||||
.pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
|
||||
@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART2_BASE,
|
||||
.pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
|
||||
@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
|
||||
{
|
||||
.pa_start = OMAP2_UART3_BASE,
|
||||
.pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
|
||||
@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4802a000,
|
||||
.pa_end = 0x4802a000 + SZ_1K - 1,
|
||||
@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48078000,
|
||||
.pa_end = 0x48078000 + SZ_1K - 1,
|
||||
@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807a000,
|
||||
.pa_end = 0x4807a000 + SZ_1K - 1,
|
||||
@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807c000,
|
||||
.pa_end = 0x4807c000 + SZ_1K - 1,
|
||||
@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x4807e000,
|
||||
.pa_end = 0x4807e000 + SZ_1K - 1,
|
||||
@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48080000,
|
||||
.pa_end = 0x48080000 + SZ_1K - 1,
|
||||
@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48082000,
|
||||
.pa_end = 0x48082000 + SZ_1K - 1,
|
||||
@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
|
||||
static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
|
||||
{
|
||||
.pa_start = 0x48084000,
|
||||
.pa_end = 0x48084000 + SZ_1K - 1,
|
||||
@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
/*
|
||||
* Common interconnect data
|
||||
*/
|
||||
|
||||
/* L3 -> L4_CORE interface */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
|
||||
.master = &omap2xxx_l3_main_hwmod,
|
||||
.slave = &omap2xxx_l4_core_hwmod,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* MPU -> L3 interface */
|
||||
struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
|
||||
.master = &omap2xxx_mpu_hwmod,
|
||||
.slave = &omap2xxx_l3_main_hwmod,
|
||||
.user = OCP_USER_MPU,
|
||||
};
|
||||
|
||||
/* DSS -> l3 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
|
||||
.master = &omap2xxx_dss_core_hwmod,
|
||||
.slave = &omap2xxx_l3_main_hwmod,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
|
||||
.flags = OMAP_FIREWALL_L3,
|
||||
}
|
||||
},
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4_CORE -> L4_WKUP interface */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_l4_wkup_hwmod,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 CORE -> UART1 interface */
|
||||
struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_uart1_hwmod,
|
||||
.clk = "uart1_ick",
|
||||
.addr = omap2xxx_uart1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 CORE -> UART2 interface */
|
||||
struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_uart2_hwmod,
|
||||
.clk = "uart2_ick",
|
||||
.addr = omap2xxx_uart2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* L4 PER -> UART3 interface */
|
||||
struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_uart3_hwmod,
|
||||
.clk = "uart3_ick",
|
||||
.addr = omap2xxx_uart3_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi1 interface */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_mcspi1_hwmod,
|
||||
.clk = "mcspi1_ick",
|
||||
.addr = omap2_mcspi1_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4 core -> mcspi2 interface */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_mcspi2_hwmod,
|
||||
.clk = "mcspi2_ick",
|
||||
.addr = omap2_mcspi2_addr_space,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer2 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer2_hwmod,
|
||||
.clk = "gpt2_ick",
|
||||
.addr = omap2xxx_timer2_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer3 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer3_hwmod,
|
||||
.clk = "gpt3_ick",
|
||||
.addr = omap2xxx_timer3_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer4 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer4_hwmod,
|
||||
.clk = "gpt4_ick",
|
||||
.addr = omap2xxx_timer4_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer5 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer5_hwmod,
|
||||
.clk = "gpt5_ick",
|
||||
.addr = omap2xxx_timer5_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer6 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer6_hwmod,
|
||||
.clk = "gpt6_ick",
|
||||
.addr = omap2xxx_timer6_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer7 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer7_hwmod,
|
||||
.clk = "gpt7_ick",
|
||||
.addr = omap2xxx_timer7_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer8 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer8_hwmod,
|
||||
.clk = "gpt8_ick",
|
||||
.addr = omap2xxx_timer8_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer9 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer9_hwmod,
|
||||
.clk = "gpt9_ick",
|
||||
.addr = omap2xxx_timer9_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer10 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer10_hwmod,
|
||||
.clk = "gpt10_ick",
|
||||
.addr = omap2_timer10_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer11 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer11_hwmod,
|
||||
.clk = "gpt11_ick",
|
||||
.addr = omap2_timer11_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> timer12 */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_timer12_hwmod,
|
||||
.clk = "gpt12_ick",
|
||||
.addr = omap2xxx_timer12_addrs,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> dss */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_dss_core_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> dss_dispc */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_dss_dispc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_dispc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> dss_rfbi */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_dss_rfbi_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_rfbi_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
/* l4_core -> dss_venc */
|
||||
struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
|
||||
.master = &omap2xxx_l4_core_hwmod,
|
||||
.slave = &omap2xxx_dss_venc_hwmod,
|
||||
.clk = "dss_ick",
|
||||
.addr = omap2_dss_venc_addrs,
|
||||
.fw = {
|
||||
.omap2 = {
|
||||
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
|
||||
.flags = OMAP_FIREWALL_L4,
|
||||
}
|
||||
},
|
||||
.flags = OCPIF_SWSUP_IDLE,
|
||||
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
||||
};
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
*/
|
||||
#include <plat/omap_hwmod.h>
|
||||
#include <plat/serial.h>
|
||||
#include <plat/gpio.h>
|
||||
#include <plat/dma.h>
|
||||
#include <plat/dmtimer.h>
|
||||
#include <plat/mcspi.h>
|
||||
@ -17,6 +18,8 @@
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include "omap_hwmod_common_data.h"
|
||||
#include "cm-regbits-24xx.h"
|
||||
#include "prm-regbits-24xx.h"
|
||||
#include "wd_timer.h"
|
||||
|
||||
struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
|
||||
@ -170,3 +173,562 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
|
||||
.sysc = &omap2xxx_mcspi_sysc,
|
||||
.rev = OMAP2_MCSPI_REV,
|
||||
};
|
||||
|
||||
/*
|
||||
* IP blocks
|
||||
*/
|
||||
|
||||
/* L3 */
|
||||
struct omap_hwmod omap2xxx_l3_main_hwmod = {
|
||||
.name = "l3_main",
|
||||
.class = &l3_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* L4 CORE */
|
||||
struct omap_hwmod omap2xxx_l4_core_hwmod = {
|
||||
.name = "l4_core",
|
||||
.class = &l4_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* L4 WKUP */
|
||||
struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
|
||||
.name = "l4_wkup",
|
||||
.class = &l4_hwmod_class,
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* MPU */
|
||||
struct omap_hwmod omap2xxx_mpu_hwmod = {
|
||||
.name = "mpu",
|
||||
.class = &mpu_hwmod_class,
|
||||
.main_clk = "mpu_ck",
|
||||
};
|
||||
|
||||
/* IVA2 */
|
||||
struct omap_hwmod omap2xxx_iva_hwmod = {
|
||||
.name = "iva",
|
||||
.class = &iva_hwmod_class,
|
||||
};
|
||||
|
||||
/* always-on timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_ALWON,
|
||||
};
|
||||
|
||||
/* pwm timers dev attribute */
|
||||
static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
|
||||
.timer_capability = OMAP_TIMER_HAS_PWM,
|
||||
};
|
||||
|
||||
/* timer1 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer1_hwmod = {
|
||||
.name = "timer1",
|
||||
.mpu_irqs = omap2_timer1_mpu_irqs,
|
||||
.main_clk = "gpt1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT1_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer2 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer2_hwmod = {
|
||||
.name = "timer2",
|
||||
.mpu_irqs = omap2_timer2_mpu_irqs,
|
||||
.main_clk = "gpt2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT2_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer3 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer3_hwmod = {
|
||||
.name = "timer3",
|
||||
.mpu_irqs = omap2_timer3_mpu_irqs,
|
||||
.main_clk = "gpt3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT3_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer4 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer4_hwmod = {
|
||||
.name = "timer4",
|
||||
.mpu_irqs = omap2_timer4_mpu_irqs,
|
||||
.main_clk = "gpt4_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT4_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer5 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer5_hwmod = {
|
||||
.name = "timer5",
|
||||
.mpu_irqs = omap2_timer5_mpu_irqs,
|
||||
.main_clk = "gpt5_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT5_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer6 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer6_hwmod = {
|
||||
.name = "timer6",
|
||||
.mpu_irqs = omap2_timer6_mpu_irqs,
|
||||
.main_clk = "gpt6_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT6_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer7 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer7_hwmod = {
|
||||
.name = "timer7",
|
||||
.mpu_irqs = omap2_timer7_mpu_irqs,
|
||||
.main_clk = "gpt7_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT7_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer8 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer8_hwmod = {
|
||||
.name = "timer8",
|
||||
.mpu_irqs = omap2_timer8_mpu_irqs,
|
||||
.main_clk = "gpt8_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT8_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_alwon_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer9 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer9_hwmod = {
|
||||
.name = "timer9",
|
||||
.mpu_irqs = omap2_timer9_mpu_irqs,
|
||||
.main_clk = "gpt9_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT9_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer10 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer10_hwmod = {
|
||||
.name = "timer10",
|
||||
.mpu_irqs = omap2_timer10_mpu_irqs,
|
||||
.main_clk = "gpt10_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT10_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer11 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer11_hwmod = {
|
||||
.name = "timer11",
|
||||
.mpu_irqs = omap2_timer11_mpu_irqs,
|
||||
.main_clk = "gpt11_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT11_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* timer12 */
|
||||
|
||||
struct omap_hwmod omap2xxx_timer12_hwmod = {
|
||||
.name = "timer12",
|
||||
.mpu_irqs = omap2xxx_timer12_mpu_irqs,
|
||||
.main_clk = "gpt12_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPT12_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
|
||||
},
|
||||
},
|
||||
.dev_attr = &capability_pwm_dev_attr,
|
||||
.class = &omap2xxx_timer_hwmod_class,
|
||||
};
|
||||
|
||||
/* wd_timer2 */
|
||||
struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
|
||||
.name = "wd_timer2",
|
||||
.class = &omap2xxx_wd_timer_hwmod_class,
|
||||
.main_clk = "mpu_wdt_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart1_hwmod = {
|
||||
.name = "uart1",
|
||||
.mpu_irqs = omap2_uart1_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart1_sdma_reqs,
|
||||
.main_clk = "uart1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_UART1_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* UART2 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart2_hwmod = {
|
||||
.name = "uart2",
|
||||
.mpu_irqs = omap2_uart2_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart2_sdma_reqs,
|
||||
.main_clk = "uart2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_UART2_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* UART3 */
|
||||
|
||||
struct omap_hwmod omap2xxx_uart3_hwmod = {
|
||||
.name = "uart3",
|
||||
.mpu_irqs = omap2_uart3_mpu_irqs,
|
||||
.sdma_reqs = omap2_uart3_sdma_reqs,
|
||||
.main_clk = "uart3_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 2,
|
||||
.module_bit = OMAP24XX_EN_UART3_SHIFT,
|
||||
.idlest_reg_id = 2,
|
||||
.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2_uart_class,
|
||||
};
|
||||
|
||||
/* dss */
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_opt_clks[] = {
|
||||
/*
|
||||
* The DSS HW needs all DSS clocks enabled during reset. The dss_core
|
||||
* driver does not use these clocks.
|
||||
*/
|
||||
{ .role = "tv_clk", .clk = "dss_54m_fck" },
|
||||
{ .role = "sys_clk", .clk = "dss2_fck" },
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_core_hwmod = {
|
||||
.name = "dss_core",
|
||||
.class = &omap2_dss_hwmod_class,
|
||||
.main_clk = "dss1_fck", /* instead of dss_fck */
|
||||
.sdma_reqs = omap2xxx_dss_sdma_chs,
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
|
||||
.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
|
||||
.name = "dss_dispc",
|
||||
.class = &omap2_dispc_hwmod_class,
|
||||
.mpu_irqs = omap2_dispc_irqs,
|
||||
.main_clk = "dss1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
|
||||
},
|
||||
},
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
.dev_attr = &omap2_3_dss_dispc_dev_attr
|
||||
};
|
||||
|
||||
static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
|
||||
{ .role = "ick", .clk = "dss_ick" },
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
|
||||
.name = "dss_rfbi",
|
||||
.class = &omap2_rfbi_hwmod_class,
|
||||
.main_clk = "dss1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
},
|
||||
},
|
||||
.opt_clks = dss_rfbi_opt_clks,
|
||||
.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_dss_venc_hwmod = {
|
||||
.name = "dss_venc",
|
||||
.class = &omap2_venc_hwmod_class,
|
||||
.main_clk = "dss_54m_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_DSS1_SHIFT,
|
||||
.module_offs = CORE_MOD,
|
||||
},
|
||||
},
|
||||
.flags = HWMOD_NO_IDLEST,
|
||||
};
|
||||
|
||||
/* gpio dev_attr */
|
||||
struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
|
||||
.bank_width = 32,
|
||||
.dbck_flag = false,
|
||||
};
|
||||
|
||||
/* gpio1 */
|
||||
struct omap_hwmod omap2xxx_gpio1_hwmod = {
|
||||
.name = "gpio1",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio1_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio2 */
|
||||
struct omap_hwmod omap2xxx_gpio2_hwmod = {
|
||||
.name = "gpio2",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio2_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio3 */
|
||||
struct omap_hwmod omap2xxx_gpio3_hwmod = {
|
||||
.name = "gpio3",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio3_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* gpio4 */
|
||||
struct omap_hwmod omap2xxx_gpio4_hwmod = {
|
||||
.name = "gpio4",
|
||||
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
|
||||
.mpu_irqs = omap2_gpio4_irqs,
|
||||
.main_clk = "gpios_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_GPIOS_SHIFT,
|
||||
.module_offs = WKUP_MOD,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_gpio_hwmod_class,
|
||||
.dev_attr = &omap2xxx_gpio_dev_attr,
|
||||
};
|
||||
|
||||
/* mcspi1 */
|
||||
static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
|
||||
.num_chipselect = 4,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_mcspi1_hwmod = {
|
||||
.name = "mcspi1",
|
||||
.mpu_irqs = omap2_mcspi1_mpu_irqs,
|
||||
.sdma_reqs = omap2_mcspi1_sdma_reqs,
|
||||
.main_clk = "mcspi1_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi1_dev_attr,
|
||||
};
|
||||
|
||||
/* mcspi2 */
|
||||
static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
|
||||
.num_chipselect = 2,
|
||||
};
|
||||
|
||||
struct omap_hwmod omap2xxx_mcspi2_hwmod = {
|
||||
.name = "mcspi2",
|
||||
.mpu_irqs = omap2_mcspi2_mpu_irqs,
|
||||
.sdma_reqs = omap2_mcspi2_sdma_reqs,
|
||||
.main_clk = "mcspi2_fck",
|
||||
.prcm = {
|
||||
.omap2 = {
|
||||
.module_offs = CORE_MOD,
|
||||
.prcm_reg_id = 1,
|
||||
.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
|
||||
.idlest_reg_id = 1,
|
||||
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
|
||||
},
|
||||
},
|
||||
.class = &omap2xxx_mcspi_class,
|
||||
.dev_attr = &omap_mcspi2_dev_attr,
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -19,18 +19,6 @@
|
||||
#include "display.h"
|
||||
|
||||
/* Common address space across OMAP2xxx */
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
|
||||
|
||||
/* Common address space across OMAP2xxx/3xxx */
|
||||
@ -54,6 +42,64 @@ extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
|
||||
/* Common IP block data across OMAP2xxx */
|
||||
extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
|
||||
extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
|
||||
extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
|
||||
extern struct omap_hwmod omap2xxx_l3_main_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_l4_core_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mpu_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_iva_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer4_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer5_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer6_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer7_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer8_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer9_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer10_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer11_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_timer12_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_uart3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_core_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio2_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio3_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_gpio4_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
|
||||
extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
|
||||
|
||||
/* Common interface data across OMAP2xxx */
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
|
||||
extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
|
||||
extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
|
||||
|
||||
/* Common IP block data */
|
||||
extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
|
||||
@ -94,6 +140,7 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
|
||||
extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
|
||||
extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
|
||||
|
||||
/* OMAP hwmod classes - forward declarations */
|
||||
extern struct omap_hwmod_class l3_hwmod_class;
|
||||
|
||||
@ -311,7 +311,7 @@ void __init omap3xxx_powerdomains_init(void)
|
||||
rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
|
||||
else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
|
||||
rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
|
||||
rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 ||
|
||||
rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
|
||||
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
|
||||
else
|
||||
|
||||
@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
||||
{
|
||||
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
|
||||
struct omap_hwmod *oh;
|
||||
struct resource irq_rsrc, mem_rsrc;
|
||||
size_t size;
|
||||
int res = 0;
|
||||
int r;
|
||||
|
||||
sprintf(name, "timer%d", gptimer_id);
|
||||
omap_hwmod_setup_one(name);
|
||||
@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
|
||||
if (!oh)
|
||||
return -ENODEV;
|
||||
|
||||
timer->irq = oh->mpu_irqs[0].irq;
|
||||
timer->phys_base = oh->slaves[0]->addr->pa_start;
|
||||
size = oh->slaves[0]->addr->pa_end - timer->phys_base;
|
||||
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
|
||||
if (r)
|
||||
return -ENXIO;
|
||||
timer->irq = irq_rsrc.start;
|
||||
|
||||
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
|
||||
if (r)
|
||||
return -ENXIO;
|
||||
timer->phys_base = mem_rsrc.start;
|
||||
size = mem_rsrc.end - mem_rsrc.start;
|
||||
|
||||
/* Static mapping, never released */
|
||||
timer->io_base = ioremap(timer->phys_base, size);
|
||||
|
||||
@ -90,7 +90,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
|
||||
musb_plat.mode = board_data->mode;
|
||||
musb_plat.extvbus = board_data->extvbus;
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505()) {
|
||||
if (soc_is_am35xx()) {
|
||||
oh_name = "am35x_otg_hs";
|
||||
name = "musb-am35x";
|
||||
} else if (cpu_is_ti81xx()) {
|
||||
|
||||
@ -118,7 +118,7 @@ void __init omap3xxx_voltagedomains_init(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
if (cpu_is_omap3517() || cpu_is_omap3505())
|
||||
if (soc_is_am35xx())
|
||||
voltdms = voltagedomains_am35xx;
|
||||
else
|
||||
voltdms = voltagedomains_omap3;
|
||||
|
||||
@ -843,7 +843,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
|
||||
}
|
||||
l = p->dma_read(CCR, lch);
|
||||
l &= ~((1 << 6) | (1 << 26));
|
||||
if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
|
||||
if (cpu_class_is_omap2() && !cpu_is_omap242x())
|
||||
l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
|
||||
else
|
||||
l |= ((read_prio & 0x1) << 6);
|
||||
@ -2071,7 +2071,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
|
||||
if (cpu_class_is_omap2() && !cpu_is_omap242x())
|
||||
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
|
||||
DMA_DEFAULT_FIFO_DEPTH, 0);
|
||||
|
||||
|
||||
@ -82,8 +82,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
|
||||
|
||||
static void omap_timer_restore_context(struct omap_dm_timer *timer)
|
||||
{
|
||||
__raw_writel(timer->context.tiocp_cfg,
|
||||
timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
|
||||
if (timer->revision == 1)
|
||||
__raw_writel(timer->context.tistat, timer->sys_stat);
|
||||
|
||||
|
||||
@ -121,6 +121,7 @@ IS_OMAP_CLASS(16xx, 0x16)
|
||||
IS_OMAP_CLASS(24xx, 0x24)
|
||||
IS_OMAP_CLASS(34xx, 0x34)
|
||||
IS_OMAP_CLASS(44xx, 0x44)
|
||||
IS_AM_CLASS(35xx, 0x35)
|
||||
IS_AM_CLASS(33xx, 0x33)
|
||||
|
||||
IS_TI_CLASS(81xx, 0x81)
|
||||
@ -148,6 +149,7 @@ IS_AM_SUBCLASS(335x, 0x335)
|
||||
#define cpu_is_ti81xx() 0
|
||||
#define cpu_is_ti816x() 0
|
||||
#define cpu_is_ti814x() 0
|
||||
#define soc_is_am35xx() 0
|
||||
#define cpu_is_am33xx() 0
|
||||
#define cpu_is_am335x() 0
|
||||
#define cpu_is_omap44xx() 0
|
||||
@ -357,6 +359,7 @@ IS_OMAP_TYPE(3517, 0x3517)
|
||||
# undef cpu_is_ti81xx
|
||||
# undef cpu_is_ti816x
|
||||
# undef cpu_is_ti814x
|
||||
# undef soc_is_am35xx
|
||||
# undef cpu_is_am33xx
|
||||
# undef cpu_is_am335x
|
||||
# define cpu_is_omap3430() is_omap3430()
|
||||
@ -378,6 +381,7 @@ IS_OMAP_TYPE(3517, 0x3517)
|
||||
# define cpu_is_ti81xx() is_ti81xx()
|
||||
# define cpu_is_ti816x() is_ti816x()
|
||||
# define cpu_is_ti814x() is_ti814x()
|
||||
# define soc_is_am35xx() is_am35xx()
|
||||
# define cpu_is_am33xx() is_am33xx()
|
||||
# define cpu_is_am335x() is_am335x()
|
||||
#endif
|
||||
@ -433,6 +437,10 @@ IS_OMAP_TYPE(3517, 0x3517)
|
||||
#define TI8148_REV_ES2_0 (TI814X_CLASS | (0x1 << 8))
|
||||
#define TI8148_REV_ES2_1 (TI814X_CLASS | (0x2 << 8))
|
||||
|
||||
#define AM35XX_CLASS 0x35170034
|
||||
#define AM35XX_REV_ES1_0 AM35XX_CLASS
|
||||
#define AM35XX_REV_ES1_1 (AM35XX_CLASS | (0x1 << 8))
|
||||
|
||||
#define AM335X_CLASS 0x33500034
|
||||
#define AM335X_REV_ES1_0 AM335X_CLASS
|
||||
|
||||
|
||||
@ -312,6 +312,11 @@
|
||||
#define CLEAR_CSR_ON_READ BIT(0xC)
|
||||
#define IS_WORD_16 BIT(0xD)
|
||||
|
||||
/* Defines for DMA Capabilities */
|
||||
#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
|
||||
#define DMA_HAS_CONSTANT_FILL_CAPS (0x1 << 19)
|
||||
#define DMA_HAS_DESCRIPTOR_CAPS (0x3 << 20)
|
||||
|
||||
enum omap_reg_offsets {
|
||||
|
||||
GCR, GSCR, GRST1, HW_ID,
|
||||
|
||||
@ -75,7 +75,6 @@ struct clk;
|
||||
|
||||
struct timer_regs {
|
||||
u32 tidr;
|
||||
u32 tiocp_cfg;
|
||||
u32 tistat;
|
||||
u32 tisr;
|
||||
u32 tier;
|
||||
|
||||
@ -213,11 +213,17 @@ struct omap_hwmod_addr_space {
|
||||
*/
|
||||
#define OCP_USER_MPU (1 << 0)
|
||||
#define OCP_USER_SDMA (1 << 1)
|
||||
#define OCP_USER_DSP (1 << 2)
|
||||
#define OCP_USER_IVA (1 << 3)
|
||||
|
||||
/* omap_hwmod_ocp_if.flags bits */
|
||||
#define OCPIF_SWSUP_IDLE (1 << 0)
|
||||
#define OCPIF_CAN_BURST (1 << 1)
|
||||
|
||||
/* omap_hwmod_ocp_if._int_flags possibilities */
|
||||
#define _OCPIF_INT_FLAGS_REGISTERED (1 << 0)
|
||||
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_ocp_if - OCP interface data
|
||||
* @master: struct omap_hwmod that initiates OCP transactions on this link
|
||||
@ -229,6 +235,7 @@ struct omap_hwmod_addr_space {
|
||||
* @width: OCP data width
|
||||
* @user: initiators using this interface (see OCP_USER_* macros above)
|
||||
* @flags: OCP interface flags (see OCPIF_* macros above)
|
||||
* @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
|
||||
*
|
||||
* It may also be useful to add a tag_cnt field for OCP2.x devices.
|
||||
*
|
||||
@ -247,6 +254,7 @@ struct omap_hwmod_ocp_if {
|
||||
u8 width;
|
||||
u8 user;
|
||||
u8 flags;
|
||||
u8 _int_flags;
|
||||
};
|
||||
|
||||
|
||||
@ -327,9 +335,9 @@ struct omap_hwmod_sysc_fields {
|
||||
* then this field has to be populated with the correct offset structure.
|
||||
*/
|
||||
struct omap_hwmod_class_sysconfig {
|
||||
u16 rev_offs;
|
||||
u16 sysc_offs;
|
||||
u16 syss_offs;
|
||||
u32 rev_offs;
|
||||
u32 sysc_offs;
|
||||
u32 syss_offs;
|
||||
u16 sysc_flags;
|
||||
struct omap_hwmod_sysc_fields *sysc_fields;
|
||||
u8 srst_udelay;
|
||||
@ -475,6 +483,16 @@ struct omap_hwmod_class {
|
||||
int (*reset)(struct omap_hwmod *oh);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
|
||||
* @ocp_if: OCP interface structure record pointer
|
||||
* @node: list_head pointing to next struct omap_hwmod_link in a list
|
||||
*/
|
||||
struct omap_hwmod_link {
|
||||
struct omap_hwmod_ocp_if *ocp_if;
|
||||
struct list_head node;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
|
||||
* @name: name of the hwmod
|
||||
@ -487,12 +505,10 @@ struct omap_hwmod_class {
|
||||
* @_clk: pointer to the main struct clk (filled in at runtime)
|
||||
* @opt_clks: other device clocks that drivers can request (0..*)
|
||||
* @voltdm: pointer to voltage domain (filled in at runtime)
|
||||
* @masters: ptr to array of OCP ifs that this hwmod can initiate on
|
||||
* @slaves: ptr to array of OCP ifs that this hwmod can respond on
|
||||
* @dev_attr: arbitrary device attributes that can be passed to the driver
|
||||
* @_sysc_cache: internal-use hwmod flags
|
||||
* @_mpu_rt_va: cached register target start address (internal use)
|
||||
* @_mpu_port_index: cached MPU register target slave ID (internal use)
|
||||
* @_mpu_port: cached MPU register target slave (internal use)
|
||||
* @opt_clks_cnt: number of @opt_clks
|
||||
* @master_cnt: number of @master entries
|
||||
* @slaves_cnt: number of @slave entries
|
||||
@ -511,6 +527,8 @@ struct omap_hwmod_class {
|
||||
*
|
||||
* Parameter names beginning with an underscore are managed internally by
|
||||
* the omap_hwmod code and should not be set during initialization.
|
||||
*
|
||||
* @masters and @slaves are now deprecated.
|
||||
*/
|
||||
struct omap_hwmod {
|
||||
const char *name;
|
||||
@ -529,15 +547,15 @@ struct omap_hwmod {
|
||||
struct omap_hwmod_opt_clk *opt_clks;
|
||||
char *clkdm_name;
|
||||
struct clockdomain *clkdm;
|
||||
struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
|
||||
struct omap_hwmod_ocp_if **slaves; /* connect to *_TA */
|
||||
struct list_head master_ports; /* connect to *_IA */
|
||||
struct list_head slave_ports; /* connect to *_TA */
|
||||
void *dev_attr;
|
||||
u32 _sysc_cache;
|
||||
void __iomem *_mpu_rt_va;
|
||||
spinlock_t _lock;
|
||||
struct list_head node;
|
||||
struct omap_hwmod_ocp_if *_mpu_port;
|
||||
u16 flags;
|
||||
u8 _mpu_port_index;
|
||||
u8 response_lat;
|
||||
u8 rst_lines_cnt;
|
||||
u8 opt_clks_cnt;
|
||||
@ -549,7 +567,6 @@ struct omap_hwmod {
|
||||
u8 _postsetup_state;
|
||||
};
|
||||
|
||||
int omap_hwmod_register(struct omap_hwmod **ohs);
|
||||
struct omap_hwmod *omap_hwmod_lookup(const char *name);
|
||||
int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
|
||||
void *data);
|
||||
@ -581,6 +598,8 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
|
||||
|
||||
int omap_hwmod_count_resources(struct omap_hwmod *oh);
|
||||
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
|
||||
int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
|
||||
const char *name, struct resource *res);
|
||||
|
||||
struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
|
||||
void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
|
||||
@ -619,4 +638,6 @@ extern int omap2430_hwmod_init(void);
|
||||
extern int omap3xxx_hwmod_init(void);
|
||||
extern int omap44xx_hwmod_init(void);
|
||||
|
||||
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user