PCI: Replace http:// links with https://
Replace http:// links with https:// links. This reduces the likelihood of man-in-the-middle attacks when developers open these links. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. [bhelgaas: also update samsung.com links, drop sourceforge link] Link: https://lore.kernel.org/r/20200627103050.71712-1-grandmaster@al2klimov.de Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -17,7 +17,7 @@ PCI device drivers.
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A more complete resource is the third edition of "Linux Device Drivers"
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by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
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LDD3 is available for free (under Creative Commons License) from:
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http://lwn.net/Kernel/LDD3/.
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https://lwn.net/Kernel/LDD3/.
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However, keep in mind that all documents are subject to "bit rot".
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Refer to the source code if things are not working as described here.
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@ -514,9 +514,8 @@ your driver if they're helpful, or just use plain hex constants.
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The device IDs are arbitrary hex numbers (vendor controlled) and normally used
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only in a single location, the pci_device_id table.
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Please DO submit new vendor/device IDs to http://pci-ids.ucw.cz/.
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There are mirrors of the pci.ids file at http://pciids.sourceforge.net/
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and https://github.com/pciutils/pciids.
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Please DO submit new vendor/device IDs to https://pci-ids.ucw.cz/.
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There's a mirror of the pci.ids file at https://github.com/pciutils/pciids.
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Obsolete functions
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@ -1,12 +1,12 @@
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PCI bus bridges have standardized Device Tree bindings:
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PCI Bus Binding to: IEEE Std 1275-1994
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http://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
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https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
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And for the interrupt mapping part:
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Open Firmware Recommended Practice: Interrupt Mapping
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http://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
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https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
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Additionally to the properties specified in the above standards a host bridge
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driver implementation may support the following properties:
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@ -557,12 +557,12 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_z
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* Device [8086:2fc0]
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* Erratum HSE43
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* CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
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* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
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* https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
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*
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* Devices [8086:6f60,6fa0,6fc0]
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* Erratum BDF2
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* PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
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* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
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* https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
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*/
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static void pci_invalid_bar(struct pci_dev *dev)
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{
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@ -2,7 +2,7 @@
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/*
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* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
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*
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* Authors: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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@ -3,7 +3,7 @@
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* PCIe host controller driver for Samsung Exynos SoCs
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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@ -3,7 +3,7 @@
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* PCIe host controller driver for Freescale i.MX6 SoCs
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*
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* Copyright (C) 2013 Kosagi
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* http://www.kosagi.com
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* https://www.kosagi.com
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*
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* Author: Sean Cross <xobs@kosagi.com>
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*/
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@ -3,7 +3,7 @@
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* PCIe host controller driver for Texas Instruments Keystone SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments., Ltd.
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* http://www.ti.com
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* https://www.ti.com
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*
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* Author: Murali Karicheri <m-karicheri2@ti.com>
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* Implementation based on pci-exynos.c and pcie-designware.c
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@ -3,7 +3,7 @@
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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@ -3,7 +3,7 @@
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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@ -3,7 +3,7 @@
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* Synopsys DesignWare PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* https://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*/
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@ -3,7 +3,7 @@
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* PCIe host controller driver for Kirin Phone SoCs
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*
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* Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
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* http://www.huawei.com
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* https://www.huawei.com
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*
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* Author: Xiaowei Song <songxiaowei@huawei.com>
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*/
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@ -18,7 +18,7 @@
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* the instance number and string from the type 41 record and exports
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* it to sysfs.
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*
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* Please see http://linux.dell.com/files/biosdevname/ for more
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* Please see https://linux.dell.com/files/biosdevname/ for more
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* information.
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*/
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@ -43,7 +43,7 @@ config PCIEAER_INJECT
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error injection can fake almost all kinds of errors with the
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help of a user space helper tool aer-inject, which can be
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gotten from:
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http://www.kernel.org/pub/linux/utils/pci/aer-inject/
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https://www.kernel.org/pub/linux/utils/pci/aer-inject/
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#
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# PCI Express ECRC
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@ -6,7 +6,7 @@
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* trigger various real hardware errors. Software based error
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* injection can fake almost all kinds of errors with the help of a
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* user space helper tool aer-inject, which can be gotten from:
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* http://www.kernel.org/pub/linux/utils/pci/aer-inject/
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* https://www.kernel.org/pub/linux/utils/pci/aer-inject/
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*
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* Copyright 2009 Intel Corporation.
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* Huang Ying <ying.huang@intel.com>
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@ -4620,11 +4620,11 @@ static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
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*
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* 0x9d10-0x9d1b PCI Express Root port #{1-12}
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*
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* [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
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* [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
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* [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
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* [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
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* [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
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* [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
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* [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
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* [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
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* [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
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* [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
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* [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
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* [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
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*/
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