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dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property

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The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add documentation for it.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Andrea Merello 2018-11-20 16:31:47 +01:00 committed by Vinod Koul
parent 5c094d4cac
commit 7df54dbeb0
1 changed files with 4 additions and 0 deletions
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Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
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@ -41,6 +41,10 @@ Optional properties:
- xlnx,include-sg: Tells configured for Scatter-mode in
the hardware.
Optional properties for AXI DMA:
- xlnx,sg-length-width: Should be set to the width in bits of the length
register as configured in h/w. Takes values {8...26}. If the property
is missing or invalid then the default value 23 is used. This is the
maximum value that is supported by all IP versions.
- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.