forked from Minki/linux
ARM: SPEAr: DT: Update pinctrl list
This patch updates pinctrl configuration for SPEAr SoC's. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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@ -30,10 +30,14 @@
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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i2c0-pmx {
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i2c0 {
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st,pins = "i2c0_grp";
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st,function = "i2c0";
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};
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i2s0 {
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st,pins = "i2s0_grp";
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st,function = "i2s0";
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};
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i2s1 {
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st,pins = "i2s1_grp";
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st,function = "i2s1";
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@ -42,6 +46,10 @@
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st,pins = "arm_gpio_grp";
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st,function = "arm_gpio";
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};
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clcd {
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st,pins = "clcd_grp" , "clcd_high_res";
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st,function = "clcd";
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};
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eth {
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st,pins = "gmii_grp";
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st,function = "gmii";
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@ -74,11 +82,6 @@
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st,pins = "i2c_1_2_grp";
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st,function = "i2c_1_2";
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};
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pci {
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st,pins = "pcie0_grp","pcie1_grp",
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"pcie2_grp";
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st,function = "pci";
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};
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smii {
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st,pins = "smii_0_1_2_grp";
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st,function = "smii_0_1_2";
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@ -88,6 +91,14 @@
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"nand_16bit_grp";
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st,function = "nand";
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};
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sata {
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st,pins = "sata0_grp";
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st,function = "sata";
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};
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pcie {
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st,pins = "pcie1_grp", "pcie2_grp";
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st,function = "pci_express";
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};
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};
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};
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@ -38,20 +38,15 @@
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st,pins = "fsmc_8bit_grp";
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st,function = "fsmc";
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};
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kbd {
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st,pins = "keyboard_row_col_grp",
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"keyboard_col5_grp";
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st,function = "keyboard";
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};
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uart0 {
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st,pins = "uart0_grp", "uart0_enh_grp";
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st,pins = "uart0_grp";
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st,function = "uart0";
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};
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i2c0-pmx {
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i2c0 {
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st,pins = "i2c0_grp";
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st,function = "i2c0";
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};
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i2c1-pmx {
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i2c1 {
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st,pins = "i2c1_grp";
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st,function = "i2c1";
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};
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@ -64,14 +59,9 @@
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st,function = "spdif_out";
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};
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ssp0 {
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st,pins = "ssp0_grp", "ssp0_cs1_grp",
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"ssp0_cs3_grp";
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st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
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st,function = "ssp0";
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};
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pwm {
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st,pins = "pwm2_grp", "pwm3_grp";
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st,function = "pwm";
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};
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smi-pmx {
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st,pins = "smi_grp";
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st,function = "smi";
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@ -84,6 +74,18 @@
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st,pins = "gmii_grp", "rgmii_grp";
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st,function = "gmac";
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};
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cam0 {
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st,pins = "cam0_grp";
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st,function = "cam0";
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};
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cam1 {
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st,pins = "cam1_grp";
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st,function = "cam1";
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};
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cam2 {
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st,pins = "cam2_grp";
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st,function = "cam2";
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};
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cam3 {
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st,pins = "cam3_grp";
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st,function = "cam3";
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@ -108,6 +110,11 @@
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st,pins = "sata_grp";
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st,function = "sata";
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};
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pcie {
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st,pins = "pcie_grp";
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st,function = "pcie";
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};
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};
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};
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@ -76,13 +76,9 @@
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st,function = "mii2";
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};
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pwm0_1 {
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st,pins = "pwm0_1_pin_14_15_grp";
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st,pins = "pwm0_1_pin_37_38_grp";
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st,function = "pwm0_1";
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};
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pwm2 {
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st,pins = "pwm2_pin_13_grp";
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st,function = "pwm2";
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};
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};
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};
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