nand/denali: use dev_xx debug function to replace nand_dbg_print and some printk
Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
parent
8ae61ebddb
commit
7cfffac06c
@ -119,9 +119,6 @@ static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
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INTR_STATUS2__RST_COMP,
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INTR_STATUS3__RST_COMP};
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/* specifies the debug level of the driver */
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static int nand_debug_level;
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/* forward declarations */
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static void clear_interrupts(struct denali_nand_info *denali);
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static uint32_t wait_for_irq(struct denali_nand_info *denali,
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@ -130,8 +127,6 @@ static void denali_irq_enable(struct denali_nand_info *denali,
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uint32_t int_mask);
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static uint32_t read_interrupt_status(struct denali_nand_info *denali);
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#define DEBUG_DENALI 0
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/* Certain operations for the denali NAND controller use
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* an indexed mode to read/write data. The operation is
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* performed by writing the address value of the command
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@ -181,11 +176,6 @@ static void read_status(struct denali_nand_info *denali)
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/* update buffer with status value */
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write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
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#if DEBUG_DENALI
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printk(KERN_INFO "device reporting status value of 0x%2x\n",
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denali->buf.buf[0]);
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#endif
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}
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/* resets a specific device connected to the core */
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@ -204,7 +194,7 @@ static void reset_bank(struct denali_nand_info *denali)
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status & operation_timeout[denali->flash_bank])
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printk(KERN_ERR "reset bank failed.\n");
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dev_err(&denali->dev->dev, "reset bank failed.\n");
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}
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/* Reset the flash controller */
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@ -212,7 +202,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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{
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uint32_t i;
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nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
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dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
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@ -228,7 +218,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
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;
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if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
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operation_timeout[i])
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nand_dbg_print(NAND_DBG_WARN,
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dev_dbg(&denali->dev->dev,
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"NAND Reset operation timed out on bank %d\n", i);
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}
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@ -266,7 +256,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
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uint16_t acc_clks;
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uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
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nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
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dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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en_lo = CEIL_DIV(Trp[mode], CLK_X);
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@ -303,7 +293,7 @@ static void nand_onfi_timing_set(struct denali_nand_info *denali,
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acc_clks++;
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if ((data_invalid - acc_clks * CLK_X) < 2)
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nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
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dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n",
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__FILE__, __LINE__);
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addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
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@ -431,7 +421,7 @@ static void get_hynix_nand_para(struct denali_nand_info *denali,
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#endif
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break;
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default:
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nand_dbg_print(NAND_DBG_WARN,
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dev_warn(&denali->dev->dev,
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"Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
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"Will use default parameter values instead.\n",
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device_id);
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@ -453,7 +443,7 @@ static void find_valid_banks(struct denali_nand_info *denali)
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index_addr_read_data(denali,
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(uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
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nand_dbg_print(NAND_DBG_DEBUG,
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dev_dbg(&denali->dev->dev,
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"Return 1st ID for bank[%d]: %x\n", i, id[i]);
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if (i == 0) {
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@ -473,12 +463,13 @@ static void find_valid_banks(struct denali_nand_info *denali)
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* Multichip support is not enabled.
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*/
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if (denali->total_used_banks != 1) {
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printk(KERN_ERR "Sorry, Intel CE4100 only supports "
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dev_err(&denali->dev->dev,
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"Sorry, Intel CE4100 only supports "
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"a single NAND device.\n");
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BUG();
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}
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}
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nand_dbg_print(NAND_DBG_DEBUG,
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dev_dbg(&denali->dev->dev,
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"denali->total_used_banks: %d\n", denali->total_used_banks);
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}
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@ -512,8 +503,9 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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uint32_t id_bytes[5], addr;
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uint8_t i, maf_id, device_id;
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nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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dev_dbg(&denali->dev->dev,
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"%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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/* Use read id method to get device ID and other
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* params. For some NAND chips, controller can't
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@ -540,12 +532,14 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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get_hynix_nand_para(denali, device_id);
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}
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nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
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"acc_clks: %d, re_2_we: %d, we_2_re: %d,"
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"addr_2_data: %d, rdwr_en_lo_cnt: %d, "
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dev_info(&denali->dev->dev,
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"Dump timing register values:"
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"acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
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"we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
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"rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
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ioread32(denali->flash_reg + ACC_CLKS),
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ioread32(denali->flash_reg + RE_2_WE),
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ioread32(denali->flash_reg + RE_2_RE),
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ioread32(denali->flash_reg + WE_2_RE),
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ioread32(denali->flash_reg + ADDR_2_DATA),
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ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
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@ -568,7 +562,7 @@ static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
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static void denali_set_intr_modes(struct denali_nand_info *denali,
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uint16_t INT_ENABLE)
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{
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nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
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dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
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__FILE__, __LINE__, __func__);
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if (INT_ENABLE)
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@ -645,11 +639,6 @@ static void clear_interrupts(struct denali_nand_info *denali)
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status = read_interrupt_status(denali);
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clear_interrupt(denali, status);
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#if DEBUG_DENALI
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denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
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denali->idx %= 32;
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#endif
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denali->irq_status = 0x0;
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spin_unlock_irq(&denali->irq_lock);
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}
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@ -663,17 +652,6 @@ static uint32_t read_interrupt_status(struct denali_nand_info *denali)
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return ioread32(denali->flash_reg + intr_status_reg);
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}
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#if DEBUG_DENALI
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static void print_irq_log(struct denali_nand_info *denali)
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{
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int i = 0;
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printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
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for (i = 0; i < 32; i++)
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printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
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}
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#endif
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/* This is the interrupt service routine. It handles all interrupts
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* sent to this device. Note that on CE4100, this is a shared
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* interrupt.
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@ -694,13 +672,6 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
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* the interrupt, since this is a shared interrupt */
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irq_status = denali_irq_detected(denali);
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if (irq_status != 0) {
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#if DEBUG_DENALI
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denali->irq_debug_array[denali->idx++] =
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0x10000000 | irq_status;
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denali->idx %= 32;
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printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
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#endif
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/* handle interrupt */
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/* first acknowledge it */
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clear_interrupt(denali, irq_status);
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@ -726,41 +697,20 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
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unsigned long timeout = msecs_to_jiffies(1000);
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do {
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#if DEBUG_DENALI
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printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
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#endif
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comp_res =
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wait_for_completion_timeout(&denali->complete, timeout);
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spin_lock_irq(&denali->irq_lock);
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intr_status = denali->irq_status;
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#if DEBUG_DENALI
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denali->irq_debug_array[denali->idx++] =
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0x20000000 | (irq_mask << 16) | intr_status;
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denali->idx %= 32;
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#endif
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if (intr_status & irq_mask) {
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denali->irq_status &= ~irq_mask;
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spin_unlock_irq(&denali->irq_lock);
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#if DEBUG_DENALI
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if (retry)
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printk(KERN_INFO "status on retry = 0x%x\n",
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intr_status);
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#endif
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/* our interrupt was detected */
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break;
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} else {
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/* these are not the interrupts you are looking for -
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* need to wait again */
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spin_unlock_irq(&denali->irq_lock);
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#if DEBUG_DENALI
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print_irq_log(denali);
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printk(KERN_INFO "received irq nobody cared:"
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" irq_status = 0x%x, irq_mask = 0x%x,"
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" timeout = %ld\n", intr_status,
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irq_mask, comp_res);
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#endif
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retry = true;
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}
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} while (comp_res != 0);
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@ -814,16 +764,6 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
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#if DEBUG_DENALI
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spin_lock_irq(&denali->irq_lock);
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denali->irq_debug_array[denali->idx++] =
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0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
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(access_type << 4);
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denali->idx %= 32;
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spin_unlock_irq(&denali->irq_lock);
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#endif
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/* clear interrupts */
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clear_interrupts(denali);
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@ -862,9 +802,10 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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printk(KERN_ERR "cmd, page, addr on timeout "
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"(0x%x, 0x%x, 0x%x)\n", cmd,
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denali->page, addr);
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dev_err(&denali->dev->dev,
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"cmd, page, addr on timeout "
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"(0x%x, 0x%x, 0x%x)\n",
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cmd, denali->page, addr);
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status = FAIL;
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} else {
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cmd = MODE_01 | addr;
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@ -932,24 +873,15 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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DENALI_WRITE) == PASS) {
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write_data_to_flash_mem(denali, buf, mtd->oobsize);
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#if DEBUG_DENALI
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spin_lock_irq(&denali->irq_lock);
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denali->irq_debug_array[denali->idx++] =
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0x80000000 | mtd->oobsize;
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denali->idx %= 32;
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spin_unlock_irq(&denali->irq_lock);
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#endif
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/* wait for operation to complete */
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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printk(KERN_ERR "OOB write failed\n");
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dev_err(&denali->dev->dev, "OOB write failed\n");
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status = -EIO;
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}
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} else {
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printk(KERN_ERR "unable to send pipeline command\n");
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dev_err(&denali->dev->dev, "unable to send pipeline command\n");
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status = -EIO;
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}
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return status;
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@ -964,9 +896,6 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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denali->page = page;
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#if DEBUG_DENALI
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printk(KERN_INFO "read_oob %d\n", page);
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#endif
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if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
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DENALI_READ) == PASS) {
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read_data_from_flash_mem(denali, buf, mtd->oobsize);
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@ -977,7 +906,7 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0)
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printk(KERN_ERR "page on OOB timeout %d\n",
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dev_err(&denali->dev->dev, "page on OOB timeout %d\n",
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denali->page);
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/* We set the device back to MAIN_ACCESS here as I observed
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@ -989,14 +918,6 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
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addr = BANK(denali->flash_bank) | denali->page;
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cmd = MODE_10 | addr;
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index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
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#if DEBUG_DENALI
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spin_lock_irq(&denali->irq_lock);
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denali->irq_debug_array[denali->idx++] =
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0x60000000 | mtd->oobsize;
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denali->idx %= 32;
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spin_unlock_irq(&denali->irq_lock);
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#endif
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}
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}
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@ -1070,13 +991,6 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
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* */
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check_erased_page = true;
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}
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#if DEBUG_DENALI
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printk(KERN_INFO "Detected ECC error in page %d:"
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" err_addr = 0x%08x, info to fix is"
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" 0x%08x\n", denali->page, err_address,
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err_correction_info);
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#endif
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} while (!ECC_LAST_ERR(err_correction_info));
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/* Once handle all ecc errors, controller will triger
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* a ECC_TRANSACTION_DONE interrupt, so here just wait
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@ -1170,8 +1084,9 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
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irq_status = wait_for_irq(denali, irq_mask);
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if (irq_status == 0) {
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printk(KERN_ERR "timeout on write_page"
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" (type = %d)\n", raw_xfer);
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dev_err(&denali->dev->dev,
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"timeout on write_page (type = %d)\n",
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raw_xfer);
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denali->status =
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(irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
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NAND_STATUS_FAIL : PASS;
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@ -1308,18 +1223,13 @@ static uint8_t denali_read_byte(struct mtd_info *mtd)
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if (denali->buf.head < denali->buf.tail)
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result = denali->buf.buf[denali->buf.head++];
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#if DEBUG_DENALI
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printk(KERN_INFO "read byte -> 0x%02x\n", result);
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#endif
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return result;
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}
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static void denali_select_chip(struct mtd_info *mtd, int chip)
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{
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struct denali_nand_info *denali = mtd_to_denali(mtd);
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#if DEBUG_DENALI
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printk(KERN_INFO "denali select chip %d\n", chip);
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#endif
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spin_lock_irq(&denali->irq_lock);
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denali->flash_bank = chip;
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spin_unlock_irq(&denali->irq_lock);
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@ -1331,9 +1241,6 @@ static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
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int status = denali->status;
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denali->status = 0;
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#if DEBUG_DENALI
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printk(KERN_INFO "waitfunc %d\n", status);
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#endif
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return status;
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}
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@ -1343,9 +1250,6 @@ static void denali_erase(struct mtd_info *mtd, int page)
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uint32_t cmd = 0x0, irq_status = 0;
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#if DEBUG_DENALI
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printk(KERN_INFO "erase page: %d\n", page);
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#endif
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/* clear interrupts */
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clear_interrupts(denali);
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@ -1368,9 +1272,6 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
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uint32_t addr, id;
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int i;
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#if DEBUG_DENALI
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printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
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#endif
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switch (cmd) {
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case NAND_CMD_PAGEPROG:
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break;
|
||||
@ -1414,7 +1315,9 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
|
||||
static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
|
||||
uint8_t *ecc_code)
|
||||
{
|
||||
printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
dev_err(&denali->dev->dev,
|
||||
"denali_ecc_calculate called unexpectedly\n");
|
||||
BUG();
|
||||
return -EIO;
|
||||
}
|
||||
@ -1422,14 +1325,18 @@ static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
|
||||
static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
|
||||
uint8_t *read_ecc, uint8_t *calc_ecc)
|
||||
{
|
||||
printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
dev_err(&denali->dev->dev,
|
||||
"denali_ecc_correct called unexpectedly\n");
|
||||
BUG();
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
|
||||
{
|
||||
printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
|
||||
struct denali_nand_info *denali = mtd_to_denali(mtd);
|
||||
dev_err(&denali->dev->dev,
|
||||
"denali_ecc_hwctl called unexpectedly\n");
|
||||
BUG();
|
||||
}
|
||||
/* end NAND core entry points */
|
||||
@ -1525,9 +1432,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
unsigned long csr_len, mem_len;
|
||||
struct denali_nand_info *denali;
|
||||
|
||||
nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
|
||||
__FILE__, __LINE__, __func__);
|
||||
|
||||
denali = kzalloc(sizeof(*denali), GFP_KERNEL);
|
||||
if (!denali)
|
||||
return -ENOMEM;
|
||||
@ -1562,11 +1466,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
if (!mem_len) {
|
||||
mem_base = csr_base + csr_len;
|
||||
mem_len = csr_len;
|
||||
nand_dbg_print(NAND_DBG_WARN,
|
||||
"Spectra: No second"
|
||||
" BAR for PCI device;"
|
||||
" assuming %08Lx\n",
|
||||
(uint64_t)csr_base);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1583,7 +1482,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
PCI_DMA_BIDIRECTIONAL);
|
||||
|
||||
if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
|
||||
printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
|
||||
dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
|
||||
goto failed_enable_dev;
|
||||
}
|
||||
|
||||
@ -1602,8 +1501,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
ret = -ENOMEM;
|
||||
goto failed_req_regions;
|
||||
}
|
||||
nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
|
||||
(uint64_t)csr_base, denali->flash_reg, csr_len);
|
||||
|
||||
denali->flash_mem = ioremap_nocache(mem_base, mem_len);
|
||||
if (!denali->flash_mem) {
|
||||
@ -1612,15 +1509,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
goto failed_remap_reg;
|
||||
}
|
||||
|
||||
nand_dbg_print(NAND_DBG_WARN,
|
||||
"Spectra: Remapped flash base address: "
|
||||
"0x%p, len: %ld\n",
|
||||
denali->flash_mem, csr_len);
|
||||
|
||||
denali_hw_init(denali);
|
||||
denali_drv_init(denali);
|
||||
|
||||
nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
|
||||
if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
|
||||
DENALI_NAND_NAME, denali)) {
|
||||
printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
|
||||
@ -1635,18 +1526,6 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
|
||||
denali_nand_timing_set(denali);
|
||||
|
||||
nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
|
||||
"acc_clks: %d, re_2_we: %d, we_2_re: %d,"
|
||||
"addr_2_data: %d, rdwr_en_lo_cnt: %d, "
|
||||
"rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
|
||||
ioread32(denali->flash_reg + ACC_CLKS),
|
||||
ioread32(denali->flash_reg + RE_2_WE),
|
||||
ioread32(denali->flash_reg + WE_2_RE),
|
||||
ioread32(denali->flash_reg + ADDR_2_DATA),
|
||||
ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
|
||||
ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
|
||||
ioread32(denali->flash_reg + CS_SETUP_CNT));
|
||||
|
||||
denali->mtd.name = "Denali NAND";
|
||||
denali->mtd.owner = THIS_MODULE;
|
||||
denali->mtd.priv = &denali->nand;
|
||||
@ -1772,8 +1651,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
|
||||
ret = add_mtd_device(&denali->mtd);
|
||||
if (ret) {
|
||||
printk(KERN_ERR "Spectra: Failed to register"
|
||||
" MTD device: %d\n", ret);
|
||||
dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
|
||||
ret);
|
||||
goto failed_req_irq;
|
||||
}
|
||||
return 0;
|
||||
@ -1801,9 +1680,6 @@ static void denali_pci_remove(struct pci_dev *dev)
|
||||
{
|
||||
struct denali_nand_info *denali = pci_get_drvdata(dev);
|
||||
|
||||
nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
|
||||
__FILE__, __LINE__, __func__);
|
||||
|
||||
nand_release(&denali->mtd);
|
||||
del_mtd_device(&denali->mtd);
|
||||
|
||||
|
@ -635,24 +635,6 @@
|
||||
#define CLK_X 5
|
||||
#define CLK_MULTI 4
|
||||
|
||||
/* ffsport.h */
|
||||
#define VERBOSE 1
|
||||
|
||||
#define NAND_DBG_WARN 1
|
||||
#define NAND_DBG_DEBUG 2
|
||||
#define NAND_DBG_TRACE 3
|
||||
|
||||
#ifdef VERBOSE
|
||||
#define nand_dbg_print(level, args...) \
|
||||
do { \
|
||||
if (level <= nand_debug_level) \
|
||||
printk(KERN_ALERT args); \
|
||||
} while (0)
|
||||
#else
|
||||
#define nand_dbg_print(level, args...)
|
||||
#endif
|
||||
|
||||
|
||||
/* spectraswconfig.h */
|
||||
#define CMD_DMA 0
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user