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ARM/ks8695/time: Migrate to new 'set-state' interface

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Migrate ks8695 driver to the new 'set-state' interface provided by
clockevents core, the earlier 'set-mode' interface is marked obsolete
now.

This also enables us to implement callbacks for new states of clockevent
devices, for example: ONESHOT_STOPPED.

There is nothing to be done for oneshot or shutdown states and so are
not implemented.

Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Viresh Kumar 2015-02-27 13:39:52 +05:30
parent cea50eeef1
commit 7cfa3c69ca
1 changed files with 21 additions and 22 deletions
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43
arch/arm/mach-ks8695/time.c
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@ -54,28 +54,25 @@
/* Timer0 Timeout Counter Register */ /* Timer0 Timeout Counter Register */
#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
static void ks8695_set_mode(enum clock_event_mode mode, static int ks8695_set_periodic(struct clock_event_device *evt)
struct clock_event_device *evt)
{ {
u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
u32 half = DIV_ROUND_CLOSEST(rate, 2);
u32 tmcon; u32 tmcon;
if (mode == CLOCK_EVT_FEAT_PERIODIC) { /* Disable timer 1 */
u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
u32 half = DIV_ROUND_CLOSEST(rate, 2); tmcon &= ~TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
/* Disable timer 1 */ /* Both registers need to count down */
tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
tmcon &= ~TMCON_T1EN; writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
/* Both registers need to count down */ /* Re-enable timer1 */
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); tmcon |= TMCON_T1EN;
writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
return 0;
/* Re-enable timer1 */
tmcon |= TMCON_T1EN;
writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
}
} }
static int ks8695_set_next_event(unsigned long cycles, static int ks8695_set_next_event(unsigned long cycles,
@ -102,11 +99,13 @@ static int ks8695_set_next_event(unsigned long cycles,
} }
static struct clock_event_device clockevent_ks8695 = { static struct clock_event_device clockevent_ks8695 = {
.name = "ks8695_t1tc", .name = "ks8695_t1tc",
.rating = 300, /* Reasonably fast and accurate clock event */ /* Reasonably fast and accurate clock event */
.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .rating = 300,
.set_next_event = ks8695_set_next_event, .features = CLOCK_EVT_FEAT_ONESHOT |
.set_mode = ks8695_set_mode, CLOCK_EVT_FEAT_PERIODIC,
.set_next_event = ks8695_set_next_event,
.set_state_periodic = ks8695_set_periodic,
}; };
/* /*