leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/i915/dg2: Add Wa_14010547955

Browse Source 
This workaround is documented a bit strangely in the bspec; it's listed
as an A0 workaround, but the description clarifies that the workaround
is implicitly handled by the hardware and what the driver really needs
to do is program a chicken bit to reenable some internal behavior.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-3-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper
2021-11-16 09:48:15 -08:00
parent c02343249c
commit 7cbea1b617
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/i915/display/intel_display.c
View File

@@ -991,6 +991,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
else if (DISPLAY_VER(dev_priv) >= 13) else if (DISPLAY_VER(dev_priv) >= 13)
tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP; tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
/* Wa_14010547955:dg2 */
if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
tmp |= DG2_RENDER_CCSTAG_4_3_EN;
intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
} }

5
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -8483,8 +8483,9 @@ enum {
_PIPEB_CHICKEN) _PIPEB_CHICKEN)
#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) #define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) #define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
#define FF_MODE2 _MMIO(0x6604) #define FF_MODE2 _MMIO(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)