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Merge tag 'drm-intel-next-fixes-2019-04-25' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

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- Use after free fix during GEM_CREATE when reporting back object size
- Icelake DP register programming order fix

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190425061312.GA2919@jlahtine-desk.ger.corp.intel.com
This commit is contained in:
Dave Airlie
2019-04-26 11:35:58 +10:00
parent 5a67928651 447811a686
commit 7c13e5cc23
2 changed files with 9 additions and 11 deletions
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2
drivers/gpu/drm/i915/i915_gem.c
View File

@@ -647,7 +647,7 @@ i915_gem_create(struct drm_file *file,
return ret; return ret;
*handle_p = handle; *handle_p = handle;
*size_p = obj->base.size; *size_p = size;
return 0; return 0;
} }

18
drivers/gpu/drm/i915/intel_ddi.c
View File

@@ -2905,21 +2905,20 @@ static void icl_enable_phy_clock_gating(struct intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port; enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port); enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
i915_reg_t mg_regs[2] = { MG_DP_MODE(0, port), MG_DP_MODE(1, port) };
u32 val; u32 val;
int i; int ln;
if (tc_port == PORT_TC_NONE) if (tc_port == PORT_TC_NONE)
return; return;
for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { for (ln = 0; ln < 2; ln++) {
val = I915_READ(mg_regs[i]); val = I915_READ(MG_DP_MODE(ln, port));
val |= MG_DP_MODE_CFG_TR2PWR_GATING | val |= MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING; MG_DP_MODE_CFG_GAONPWR_GATING;
I915_WRITE(mg_regs[i], val); I915_WRITE(MG_DP_MODE(ln, port), val);
} }
val = I915_READ(MG_MISC_SUS0(tc_port)); val = I915_READ(MG_MISC_SUS0(tc_port));
@@ -2938,21 +2937,20 @@ static void icl_disable_phy_clock_gating(struct intel_digital_port *dig_port)
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port; enum port port = dig_port->base.port;
enum tc_port tc_port = intel_port_to_tc(dev_priv, port); enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
i915_reg_t mg_regs[2] = { MG_DP_MODE(port, 0), MG_DP_MODE(port, 1) };
u32 val; u32 val;
int i; int ln;
if (tc_port == PORT_TC_NONE) if (tc_port == PORT_TC_NONE)
return; return;
for (i = 0; i < ARRAY_SIZE(mg_regs); i++) { for (ln = 0; ln < 2; ln++) {
val = I915_READ(mg_regs[i]); val = I915_READ(MG_DP_MODE(ln, port));
val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING |
MG_DP_MODE_CFG_TRPWR_GATING | MG_DP_MODE_CFG_TRPWR_GATING |
MG_DP_MODE_CFG_CLNPWR_GATING | MG_DP_MODE_CFG_CLNPWR_GATING |
MG_DP_MODE_CFG_DIGPWR_GATING | MG_DP_MODE_CFG_DIGPWR_GATING |
MG_DP_MODE_CFG_GAONPWR_GATING); MG_DP_MODE_CFG_GAONPWR_GATING);
I915_WRITE(mg_regs[i], val); I915_WRITE(MG_DP_MODE(ln, port), val);
} }
val = I915_READ(MG_MISC_SUS0(tc_port)); val = I915_READ(MG_MISC_SUS0(tc_port));