staging: rtl8192u: rename general variables in r819xU_phy.c
This patch renames the following variables: - dwRegAddr and RegAddr into reg_addr - dwData and Data into data - BitShift into bitshift - Offset into offset - NewOffset into new_offset - Bandwidth into bandwidth The renaming was done to remove camel case and unnecessary 'dw' prefix from the above variable names. Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Xenia Ragiadakou
Greg Kroah-Hartman
parent
9f66ddb5f7
commit
7993163901
@ -73,100 +73,100 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
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/******************************************************************************
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*function: This function set specific bits to BB register
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* input: net_device dev
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* u32 dwRegAddr //target addr to be modified
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* u32 reg_addr //target addr to be modified
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* u32 bitmask //taget bit pos in the addr to be modified
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* u32 dwData //value to be write
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* u32 data //value to be write
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* output: none
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* return: none
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* notice:
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* ****************************************************************************/
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void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 bitmask,
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u32 dwData)
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void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
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u32 data)
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{
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u32 reg, BitShift;
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u32 reg, bitshift;
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if (bitmask != bMaskDWord) { //if not "double word" write
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read_nic_dword(dev, dwRegAddr, ®);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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read_nic_dword(dev, reg_addr, ®);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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reg &= ~bitmask;
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reg |= dwData << BitShift;
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write_nic_dword(dev, dwRegAddr, reg);
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reg |= data << bitshift;
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write_nic_dword(dev, reg_addr, reg);
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} else {
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write_nic_dword(dev, dwRegAddr, dwData);
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write_nic_dword(dev, reg_addr, data);
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}
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return;
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}
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/******************************************************************************
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*function: This function reads specific bits from BB register
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* input: net_device dev
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* u32 dwRegAddr //target addr to be readback
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* u32 reg_addr //target addr to be readback
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* u32 bitmask //taget bit pos in the addr to be readback
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* output: none
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* return: u32 Data //the readback register value
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* return: u32 data //the readback register value
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* notice:
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* ****************************************************************************/
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u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 bitmask)
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u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
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{
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u32 Ret = 0, reg, BitShift;
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u32 Ret = 0, reg, bitshift;
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read_nic_dword(dev, dwRegAddr, ®);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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Ret = (reg & bitmask) >> BitShift;
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read_nic_dword(dev, reg_addr, ®);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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Ret = (reg & bitmask) >> bitshift;
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return Ret;
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}
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static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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u32 Offset);
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u32 offset);
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static void phy_FwRFSerialWrite(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 Offset,
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u32 Data);
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RF90_RADIO_PATH_E eRFPath, u32 offset,
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u32 data);
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/******************************************************************************
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*function: This function read register from RF chip
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* input: net_device dev
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* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
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* u32 Offset //target address to be read
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* u32 offset //target address to be read
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* output: none
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* return: u32 readback value
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* notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
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* ****************************************************************************/
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u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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u32 Offset)
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u32 offset)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 ret = 0;
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u32 NewOffset = 0;
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u32 new_offset = 0;
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BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
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rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
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//make sure RF register offset is correct
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Offset &= 0x3f;
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offset &= 0x3f;
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//switch page for 8256 RF IC
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if (priv->rf_chip == RF_8256) {
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if (Offset >= 31) {
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if (offset >= 31) {
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priv->RfReg0Value[eRFPath] |= 0x140;
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//Switch to Reg_Mode2 for Reg 31-45
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
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//modify offset
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NewOffset = Offset -30;
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} else if (Offset >= 16) {
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new_offset = offset - 30;
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} else if (offset >= 16) {
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priv->RfReg0Value[eRFPath] |= 0x100;
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priv->RfReg0Value[eRFPath] &= (~0x40);
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//Switch to Reg_Mode 1 for Reg16-30
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
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NewOffset = Offset - 15;
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new_offset = offset - 15;
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} else {
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NewOffset = Offset;
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new_offset = offset;
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}
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} else {
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RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
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NewOffset = Offset;
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new_offset = offset;
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}
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//put desired read addr to LSSI control Register
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, new_offset);
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//Issue a posedge trigger
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//
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
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@ -198,8 +198,8 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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*function: This function write data to RF register
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* input: net_device dev
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* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
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* u32 Offset //target address to be written
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* u32 Data //The new register data to be written
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* u32 offset //target address to be written
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* u32 data //The new register data to be written
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* output: none
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* return: none
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* notice: For RF8256 only.
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@ -215,45 +215,45 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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*------------------------------------------------------------------
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* ****************************************************************************/
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void rtl8192_phy_RFSerialWrite(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
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RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 DataAndAddr = 0, NewOffset = 0;
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u32 DataAndAddr = 0, new_offset = 0;
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BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
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Offset &= 0x3f;
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offset &= 0x3f;
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if (priv->rf_chip == RF_8256) {
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if (Offset >= 31) {
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if (offset >= 31) {
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priv->RfReg0Value[eRFPath] |= 0x140;
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
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NewOffset = Offset - 30;
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} else if (Offset >= 16) {
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new_offset = offset - 30;
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} else if (offset >= 16) {
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priv->RfReg0Value[eRFPath] |= 0x100;
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priv->RfReg0Value[eRFPath] &= (~0x40);
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
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NewOffset = Offset - 15;
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new_offset = offset - 15;
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} else {
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NewOffset = Offset;
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new_offset = offset;
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}
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} else {
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RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
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NewOffset = Offset;
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new_offset = offset;
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}
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// Put write addr in [5:0] and write data in [31:16]
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DataAndAddr = (Data<<16) | (NewOffset&0x3f);
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DataAndAddr = (data<<16) | (new_offset&0x3f);
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// Write Operation
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rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
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if (Offset == 0x0)
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priv->RfReg0Value[eRFPath] = Data;
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if (offset == 0x0)
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priv->RfReg0Value[eRFPath] = data;
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// Switch back to Reg_Mode0;
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if (priv->rf_chip == RF_8256) {
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if (Offset != 0) {
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if (offset != 0) {
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priv->RfReg0Value[eRFPath] &= 0xebf;
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rtl8192_setBBreg(
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dev,
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@ -269,46 +269,46 @@ void rtl8192_phy_RFSerialWrite(struct net_device *dev,
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*function: This function set specific bits to RF register
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* input: net_device dev
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* RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
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* u32 RegAddr //target addr to be modified
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* u32 reg_addr //target addr to be modified
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* u32 bitmask //taget bit pos in the addr to be modified
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* u32 Data //value to be write
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* u32 data //value to be write
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* output: none
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* return: none
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* notice:
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* ****************************************************************************/
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void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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u32 RegAddr, u32 bitmask, u32 Data)
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u32 reg_addr, u32 bitmask, u32 data)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 reg, BitShift;
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u32 reg, bitshift;
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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return;
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if (priv->Rf_Mode == RF_OP_By_FW) {
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if (bitmask != bMask12Bits) { // RF data is 12 bits only
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reg = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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reg &= ~bitmask;
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reg |= Data << BitShift;
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reg |= data << bitshift;
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phy_FwRFSerialWrite(dev, eRFPath, RegAddr, reg);
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phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
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} else {
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phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
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phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
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}
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udelay(200);
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} else {
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if (bitmask != bMask12Bits) { // RF data is 12 bits only
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reg = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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reg &= ~bitmask;
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reg |= Data << BitShift;
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reg |= data << bitshift;
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rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, reg);
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rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
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} else {
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rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
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rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
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}
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}
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return;
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@ -317,31 +317,31 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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/******************************************************************************
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*function: This function reads specific bits from RF register
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* input: net_device dev
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* u32 RegAddr //target addr to be readback
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* u32 reg_addr //target addr to be readback
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* u32 bitmask //taget bit pos in the addr to be readback
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* output: none
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* return: u32 Data //the readback register value
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* return: u32 data //the readback register value
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* notice:
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* ****************************************************************************/
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u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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u32 RegAddr, u32 bitmask)
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u32 reg_addr, u32 bitmask)
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{
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u32 reg, BitShift;
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u32 reg, bitshift;
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struct r8192_priv *priv = ieee80211_priv(dev);
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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return 0;
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if (priv->Rf_Mode == RF_OP_By_FW) {
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reg = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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reg = (reg & bitmask) >> BitShift;
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reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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reg = (reg & bitmask) >> bitshift;
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udelay(200);
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return reg;
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} else {
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reg = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
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BitShift = rtl8192_CalculateBitShift(bitmask);
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reg = (reg & bitmask) >> BitShift;
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reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
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bitshift = rtl8192_CalculateBitShift(bitmask);
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reg = (reg & bitmask) >> bitshift;
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return reg;
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}
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}
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@ -353,10 +353,10 @@ u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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* notice:
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* ***************************************************************************/
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static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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u32 Offset)
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u32 offset)
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{
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u32 reg = 0;
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u32 Data = 0;
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u32 data = 0;
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u8 time = 0;
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u32 tmp;
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/* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
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@ -364,12 +364,12 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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much time. This is only for site survey. */
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// 1. Read operation need not insert data. bit 0-11
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// 2. Write RF register address. Bit 12-19
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Data |= ((Offset&0xFF)<<12);
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data |= ((offset&0xFF)<<12);
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// 3. Write RF path. bit 20-21
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Data |= ((eRFPath&0x3)<<20);
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data |= ((eRFPath&0x3)<<20);
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// 4. Set RF read indicator. bit 22=0
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// 5. Trigger Fw to operate the command. bit 31
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Data |= 0x80000000;
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data |= 0x80000000;
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// 6. We can not execute read operation if bit 31 is 1.
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read_nic_dword(dev, QPNR, &tmp);
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while (tmp & 0x80000000) {
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@ -382,7 +382,7 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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}
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}
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// 7. Execute read operation.
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write_nic_dword(dev, QPNR, Data);
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write_nic_dword(dev, QPNR, data);
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// 8. Check if firmawre send back RF content.
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read_nic_dword(dev, QPNR, &tmp);
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while (tmp & 0x80000000) {
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@ -408,7 +408,7 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
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* notice:
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* ***************************************************************************/
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static void phy_FwRFSerialWrite(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
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RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
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{
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u8 time = 0;
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u32 tmp;
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@ -419,13 +419,13 @@ static void phy_FwRFSerialWrite(struct net_device *dev,
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// 1. Set driver write bit and 12 bit data. bit 0-11
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// 2. Write RF register address. bit 12-19
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Data |= ((Offset&0xFF)<<12);
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data |= ((offset&0xFF)<<12);
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// 3. Write RF path. bit 20-21
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Data |= ((eRFPath&0x3)<<20);
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data |= ((eRFPath&0x3)<<20);
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// 4. Set RF write indicator. bit 22=1
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Data |= 0x400000;
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data |= 0x400000;
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// 5. Trigger Fw to operate the command. bit 31=1
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Data |= 0x80000000;
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data |= 0x80000000;
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// 6. Write operation. We can not write if bit 31 is 1.
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read_nic_dword(dev, QPNR, &tmp);
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@ -440,7 +440,7 @@ static void phy_FwRFSerialWrite(struct net_device *dev,
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}
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// 7. No matter check bit. We always force the write. Because FW will
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// not accept the command.
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write_nic_dword(dev, QPNR, Data);
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write_nic_dword(dev, QPNR, data);
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/* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
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to finish RF write operation. */
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/* 2008/01/17 MH We support delay in firmware side now. */
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@ -1517,15 +1517,15 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
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/******************************************************************************
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*function: This function schedules bandwidth switch work.
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* input: struct net_device *dev
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* HT_CHANNEL_WIDTH Bandwidth //20M or 40M
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* HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
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* HT_CHANNEL_WIDTH bandwidth //20M or 40M
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* HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
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* output: none
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* return: none
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* Note: I doubt whether SetBWModeInProgress flag is necessary as we can
|
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* test whether current work in the queue or not.//do I?
|
||||
* ***************************************************************************/
|
||||
void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth,
|
||||
HT_EXTCHNL_OFFSET Offset)
|
||||
void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
|
||||
HT_EXTCHNL_OFFSET offset)
|
||||
{
|
||||
struct r8192_priv *priv = ieee80211_priv(dev);
|
||||
|
||||
@ -1533,11 +1533,11 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth,
|
||||
return;
|
||||
priv->SetBWModeInProgress = true;
|
||||
|
||||
priv->CurrentChannelBW = Bandwidth;
|
||||
priv->CurrentChannelBW = bandwidth;
|
||||
|
||||
if (Offset == HT_EXTCHNL_OFFSET_LOWER)
|
||||
if (offset == HT_EXTCHNL_OFFSET_LOWER)
|
||||
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
|
||||
else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
|
||||
else if (offset == HT_EXTCHNL_OFFSET_UPPER)
|
||||
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
|
||||
else
|
||||
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user