x86, msi: Introduce x86_msi.compose_msi_msg call-back
This call-back points to the right function for initializing the msi_msg structure. The old code for msi_msg generation was split up into the irq-remapped and the default case. The irq-remapped case just calls into the specific Intel or AMD implementation when the device is behind an IOMMU. Otherwise the default function is called. Signed-off-by: Joerg Roedel <joro@8bytes.org> Acked-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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2976fd8417
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@ -158,6 +158,9 @@ extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
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struct io_apic_irq_attr *);
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struct io_apic_irq_attr *);
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extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
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extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
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extern void native_compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id);
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int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
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int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
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extern int save_ioapic_entries(void);
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extern int save_ioapic_entries(void);
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@ -242,6 +245,7 @@ static inline void disable_ioapic_support(void) { }
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#define native_io_apic_print_entries NULL
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#define native_io_apic_print_entries NULL
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#define native_ioapic_set_affinity NULL
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#define native_ioapic_set_affinity NULL
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#define native_setup_ioapic_entry NULL
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#define native_setup_ioapic_entry NULL
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#define native_compose_msi_msg NULL
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#endif
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#endif
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#endif /* _ASM_X86_IO_APIC_H */
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#endif /* _ASM_X86_IO_APIC_H */
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@ -181,9 +181,13 @@ struct x86_platform_ops {
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};
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};
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struct pci_dev;
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struct pci_dev;
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struct msi_msg;
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struct x86_msi_ops {
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struct x86_msi_ops {
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int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
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int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
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void (*compose_msi_msg)(struct pci_dev *dev, unsigned int irq,
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unsigned int dest, struct msi_msg *msg,
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u8 hpet_id);
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void (*teardown_msi_irq)(unsigned int irq);
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void (*teardown_msi_irq)(unsigned int irq);
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void (*teardown_msi_irqs)(struct pci_dev *dev);
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void (*teardown_msi_irqs)(struct pci_dev *dev);
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void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
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void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
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@ -3019,6 +3019,36 @@ void destroy_irqs(unsigned int irq, unsigned int count)
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/*
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/*
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* MSI message composition
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* MSI message composition
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*/
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*/
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void native_compose_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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msg->address_hi = MSI_ADDR_BASE_HI;
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if (x2apic_enabled())
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msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest);
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msg->address_lo =
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MSI_ADDR_BASE_LO |
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((apic->irq_dest_mode == 0) ?
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MSI_ADDR_DEST_MODE_PHYSICAL:
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MSI_ADDR_DEST_MODE_LOGICAL) |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_ADDR_REDIRECTION_CPU:
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MSI_ADDR_REDIRECTION_LOWPRI) |
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MSI_ADDR_DEST_ID(dest);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_DATA_DELIVERY_FIXED:
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MSI_DATA_DELIVERY_LOWPRI) |
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MSI_DATA_VECTOR(cfg->vector);
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}
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#ifdef CONFIG_PCI_MSI
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#ifdef CONFIG_PCI_MSI
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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struct msi_msg *msg, u8 hpet_id)
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struct msi_msg *msg, u8 hpet_id)
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@ -3040,34 +3070,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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if (err)
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if (err)
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return err;
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return err;
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if (irq_remapped(cfg)) {
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x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
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return 0;
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}
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if (x2apic_enabled())
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msg->address_hi = MSI_ADDR_BASE_HI |
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MSI_ADDR_EXT_DEST_ID(dest);
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else
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msg->address_hi = MSI_ADDR_BASE_HI;
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msg->address_lo =
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MSI_ADDR_BASE_LO |
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((apic->irq_dest_mode == 0) ?
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MSI_ADDR_DEST_MODE_PHYSICAL:
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MSI_ADDR_DEST_MODE_LOGICAL) |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_ADDR_REDIRECTION_CPU:
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MSI_ADDR_REDIRECTION_LOWPRI) |
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MSI_ADDR_DEST_ID(dest);
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msg->data =
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MSI_DATA_TRIGGER_EDGE |
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MSI_DATA_LEVEL_ASSERT |
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((apic->irq_delivery_mode != dest_LowestPrio) ?
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MSI_DATA_DELIVERY_FIXED:
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MSI_DATA_DELIVERY_LOWPRI) |
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MSI_DATA_VECTOR(cfg->vector);
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return 0;
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return 0;
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}
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}
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@ -113,6 +113,7 @@ struct x86_platform_ops x86_platform = {
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EXPORT_SYMBOL_GPL(x86_platform);
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EXPORT_SYMBOL_GPL(x86_platform);
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struct x86_msi_ops x86_msi = {
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struct x86_msi_ops x86_msi = {
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.setup_msi_irqs = native_setup_msi_irqs,
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.setup_msi_irqs = native_setup_msi_irqs,
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.compose_msi_msg = native_compose_msi_msg,
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.teardown_msi_irq = native_teardown_msi_irq,
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.teardown_msi_irq = native_teardown_msi_irq,
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.teardown_msi_irqs = default_teardown_msi_irqs,
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.teardown_msi_irqs = default_teardown_msi_irqs,
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.restore_msi_irqs = default_restore_msi_irqs,
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.restore_msi_irqs = default_restore_msi_irqs,
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@ -150,6 +150,7 @@ static void __init irq_remapping_modify_x86_ops(void)
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x86_io_apic_ops.setup_entry = setup_ioapic_remapped_entry;
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x86_io_apic_ops.setup_entry = setup_ioapic_remapped_entry;
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x86_msi.setup_msi_irqs = irq_remapping_setup_msi_irqs;
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x86_msi.setup_msi_irqs = irq_remapping_setup_msi_irqs;
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x86_msi.setup_hpet_msi = setup_hpet_msi_remapped;
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x86_msi.setup_hpet_msi = setup_hpet_msi_remapped;
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x86_msi.compose_msi_msg = compose_remapped_msi_msg;
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}
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}
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static __init int setup_nointremap(char *str)
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static __init int setup_nointremap(char *str)
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@ -295,9 +296,11 @@ void compose_remapped_msi_msg(struct pci_dev *pdev,
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unsigned int irq, unsigned int dest,
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unsigned int irq, unsigned int dest,
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struct msi_msg *msg, u8 hpet_id)
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struct msi_msg *msg, u8 hpet_id)
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{
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{
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if (!remap_ops || !remap_ops->compose_msi_msg)
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struct irq_cfg *cfg = irq_get_chip_data(irq);
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return;
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if (!irq_remapped(cfg))
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native_compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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else if (remap_ops && remap_ops->compose_msi_msg)
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remap_ops->compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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remap_ops->compose_msi_msg(pdev, irq, dest, msg, hpet_id);
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}
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}
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