forked from Minki/linux
net: dsa: qca8k: add support for internal phy and internal mdio
Add support to setup_mdio_bus for internal phy declaration. Introduce a flag to use the legacy port phy mapping by default and use the direct mapping if a mdio node is detected in the switch node. Register a dedicated mdio internal mdio bus to address the different mapping between port and phy if the mdio node is detected. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ansuel Smith
David S. Miller
parent
617960d72e
commit
759bafb8a3
@ -11,6 +11,7 @@
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#include <linux/netdevice.h>
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#include <net/dsa.h>
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#include <linux/of_net.h>
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#include <linux/of_mdio.h>
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#include <linux/of_platform.h>
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#include <linux/if_bridge.h>
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#include <linux/mdio.h>
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@ -629,7 +630,7 @@ qca8k_port_to_phy(int port)
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}
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static int
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qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
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qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
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{
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u16 r1, r2, page;
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u32 val;
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@ -639,7 +640,7 @@ qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
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ret = read_poll_timeout(qca8k_mii_read32, val, !(val & mask), 0,
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QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
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priv->bus, 0x10 | r2, r1);
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bus, 0x10 | r2, r1);
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/* Check if qca8k_read has failed for a different reason
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* before returnting -ETIMEDOUT
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@ -651,19 +652,16 @@ qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
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}
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static int
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qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
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qca8k_mdio_write(struct mii_bus *salve_bus, int phy, int regnum, u16 data)
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{
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struct qca8k_priv *priv = salve_bus->priv;
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u16 r1, r2, page;
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u32 phy, val;
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u32 val;
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int ret;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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/* callee is responsible for not passing bad ports,
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* but we still would like to make spills impossible.
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*/
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phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
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QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
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QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
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@ -679,33 +677,29 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data)
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qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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exit:
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mutex_unlock(&priv->bus->mdio_lock);
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_EN);
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qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);
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mutex_unlock(&priv->bus->mdio_lock);
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return ret;
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}
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static int
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qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
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qca8k_mdio_read(struct mii_bus *salve_bus, int phy, int regnum)
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{
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struct qca8k_priv *priv = salve_bus->priv;
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u16 r1, r2, page;
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u32 phy, val;
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u32 val;
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int ret;
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if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
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return -EINVAL;
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/* callee is responsible for not passing bad ports,
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* but we still would like to make spills impossible.
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*/
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phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
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QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
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QCA8K_MDIO_MASTER_REG_ADDR(regnum);
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@ -720,24 +714,22 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum)
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qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
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ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL,
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ret = qca8k_mdio_busy_wait(priv->bus, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_BUSY);
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if (ret)
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goto exit;
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val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
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val &= QCA8K_MDIO_MASTER_DATA_MASK;
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exit:
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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qca8k_mii_write32(priv->bus, 0x10 | r2, r1, 0);
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mutex_unlock(&priv->bus->mdio_lock);
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if (val >= 0)
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val &= QCA8K_MDIO_MASTER_DATA_MASK;
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/* even if the busy_wait timeouts try to clear the MASTER_EN */
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qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL,
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QCA8K_MDIO_MASTER_EN);
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return val;
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}
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@ -746,7 +738,14 @@ qca8k_phy_write(struct dsa_switch *ds, int port, int regnum, u16 data)
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{
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struct qca8k_priv *priv = ds->priv;
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return qca8k_mdio_write(priv, port, regnum, data);
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/* Check if the legacy mapping should be used and the
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* port is not correctly mapped to the right PHY in the
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* devicetree
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*/
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if (priv->legacy_phy_port_mapping)
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port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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return qca8k_mdio_write(priv->bus, port, regnum, data);
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}
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static int
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@ -755,7 +754,14 @@ qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
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struct qca8k_priv *priv = ds->priv;
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int ret;
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ret = qca8k_mdio_read(priv, port, regnum);
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/* Check if the legacy mapping should be used and the
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* port is not correctly mapped to the right PHY in the
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* devicetree
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*/
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if (priv->legacy_phy_port_mapping)
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port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
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ret = qca8k_mdio_read(priv->bus, port, regnum);
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if (ret < 0)
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return 0xffff;
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@ -763,11 +769,38 @@ qca8k_phy_read(struct dsa_switch *ds, int port, int regnum)
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return ret;
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}
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static int
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qca8k_mdio_register(struct qca8k_priv *priv, struct device_node *mdio)
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{
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struct dsa_switch *ds = priv->ds;
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struct mii_bus *bus;
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bus = devm_mdiobus_alloc(ds->dev);
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if (!bus)
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return -ENOMEM;
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bus->priv = (void *)priv;
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bus->name = "qca8k slave mii";
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bus->read = qca8k_mdio_read;
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bus->write = qca8k_mdio_write;
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snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d",
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ds->index);
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bus->parent = ds->dev;
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bus->phy_mask = ~ds->phys_mii_mask;
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ds->slave_mii_bus = bus;
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return devm_of_mdiobus_register(priv->dev, bus, mdio);
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}
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static int
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qca8k_setup_mdio_bus(struct qca8k_priv *priv)
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{
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u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
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struct device_node *ports, *port;
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struct device_node *ports, *port, *mdio;
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phy_interface_t mode;
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int err;
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ports = of_get_child_by_name(priv->dev->of_node, "ports");
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@ -788,7 +821,10 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv)
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if (!dsa_is_user_port(priv->ds, reg))
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continue;
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if (of_property_read_bool(port, "phy-handle"))
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of_get_phy_mode(port, &mode);
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if (of_property_read_bool(port, "phy-handle") &&
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mode != PHY_INTERFACE_MODE_INTERNAL)
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external_mdio_mask |= BIT(reg);
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else
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internal_mdio_mask |= BIT(reg);
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@ -825,8 +861,23 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv)
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QCA8K_MDIO_MASTER_EN);
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}
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/* Check if the devicetree declare the port:phy mapping */
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mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
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if (of_device_is_available(mdio)) {
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err = qca8k_mdio_register(priv, mdio);
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if (err)
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of_node_put(mdio);
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return err;
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}
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/* If a mapping can't be found the legacy mapping is used,
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* using the qca8k_port_to_phy function
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*/
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priv->legacy_phy_port_mapping = true;
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priv->ops.phy_read = qca8k_phy_read;
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priv->ops.phy_write = qca8k_phy_write;
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return 0;
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}
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@ -1212,7 +1263,8 @@ qca8k_phylink_validate(struct dsa_switch *ds, int port,
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case 5:
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/* Internal PHY */
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_GMII)
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state->interface != PHY_INTERFACE_MODE_GMII &&
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state->interface != PHY_INTERFACE_MODE_INTERNAL)
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goto unsupported;
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break;
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case 6: /* 2nd CPU port / external PHY */
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@ -255,6 +255,7 @@ struct qca8k_priv {
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u8 switch_revision;
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u8 rgmii_tx_delay;
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u8 rgmii_rx_delay;
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bool legacy_phy_port_mapping;
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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