i2c: mpc: fix PORDEVSR2 mask for MPC8533/44
According to the reference manuals for the corresponding SoCs, SEC frequency ratio configuration is indicated by bit 26 of the POR Device Status Register 2. Consequently, SEC_CFG bit should be tested by mask 0x20, not 0x80. Testing the wrong bit leads to selection of wrong I2C clock prescaler on those SoCs. Signed-off-by: Arseny Solokha <asolokha@kb.kras.ru> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -332,14 +332,18 @@ static u32 mpc_i2c_get_sec_cfg_8xxx(void)
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if (prop) {
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if (prop) {
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/*
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/*
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* Map and check POR Device Status Register 2
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* Map and check POR Device Status Register 2
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* (PORDEVSR2) at 0xE0014
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* (PORDEVSR2) at 0xE0014. Note than while MPC8533
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* and MPC8544 indicate SEC frequency ratio
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* configuration as bit 26 in PORDEVSR2, other MPC8xxx
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* parts may store it differently or may not have it
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* at all.
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*/
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*/
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reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
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reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
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if (!reg)
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if (!reg)
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printk(KERN_ERR
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printk(KERN_ERR
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"Error: couldn't map PORDEVSR2\n");
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"Error: couldn't map PORDEVSR2\n");
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else
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else
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val = in_be32(reg) & 0x00000080; /* sec-cfg */
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val = in_be32(reg) & 0x00000020; /* sec-cfg */
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iounmap(reg);
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iounmap(reg);
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}
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}
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}
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}
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