forked from Minki/linux
crypto: mv_cesa - Add sha1 and hmac(sha1) async hash drivers
Add sha1 and hmac(sha1) async hash drivers Signed-off-by: Uri Simchoni <uri@jdland.co.il> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Uri Simchoni
Herbert Xu
parent
0c5c6c4bae
commit
750052dd24
@ -14,8 +14,14 @@
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#include <linux/kthread.h>
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#include <linux/platform_device.h>
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#include <linux/scatterlist.h>
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#include <crypto/internal/hash.h>
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#include <crypto/sha.h>
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#include "mv_cesa.h"
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#define MV_CESA "MV-CESA:"
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#define MAX_HW_HASH_SIZE 0xFFFF
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/*
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* STM:
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* /---------------------------------------\
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@ -38,7 +44,7 @@ enum engine_status {
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* @dst_sg_it: sg iterator for dst
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* @sg_src_left: bytes left in src to process (scatter list)
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* @src_start: offset to add to src start position (scatter list)
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* @crypt_len: length of current crypt process
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* @crypt_len: length of current hw crypt/hash process
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* @hw_nbytes: total bytes to process in hw for this request
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* @copy_back: whether to copy data back (crypt) or not (hash)
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* @sg_dst_left: bytes left dst to process in this scatter list
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@ -81,6 +87,8 @@ struct crypto_priv {
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struct req_progress p;
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int max_req_size;
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int sram_size;
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int has_sha1;
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int has_hmac_sha1;
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};
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static struct crypto_priv *cpg;
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@ -102,6 +110,31 @@ struct mv_req_ctx {
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int decrypt;
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};
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enum hash_op {
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COP_SHA1,
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COP_HMAC_SHA1
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};
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struct mv_tfm_hash_ctx {
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struct crypto_shash *fallback;
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struct crypto_shash *base_hash;
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u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
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int count_add;
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enum hash_op op;
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};
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struct mv_req_hash_ctx {
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u64 count;
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u32 state[SHA1_DIGEST_SIZE / 4];
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u8 buffer[SHA1_BLOCK_SIZE];
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int first_hash; /* marks that we don't have previous state */
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int last_chunk; /* marks that this is the 'final' request */
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int extra_bytes; /* unprocessed bytes in buffer */
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enum hash_op op;
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int count_add;
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struct scatterlist dummysg;
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};
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static void compute_aes_dec_key(struct mv_ctx *ctx)
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{
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struct crypto_aes_ctx gen_aes_key;
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@ -265,6 +298,132 @@ static void mv_crypto_algo_completion(void)
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memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
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}
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static void mv_process_hash_current(int first_block)
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{
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struct ahash_request *req = ahash_request_cast(cpg->cur_req);
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struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
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struct req_progress *p = &cpg->p;
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struct sec_accel_config op = { 0 };
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int is_last;
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switch (req_ctx->op) {
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case COP_SHA1:
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default:
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op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
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break;
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case COP_HMAC_SHA1:
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op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
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break;
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}
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op.mac_src_p =
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MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
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req_ctx->
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count);
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setup_data_in();
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op.mac_digest =
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MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
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op.mac_iv =
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MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
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MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
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is_last = req_ctx->last_chunk
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&& (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
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&& (req_ctx->count <= MAX_HW_HASH_SIZE);
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if (req_ctx->first_hash) {
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if (is_last)
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op.config |= CFG_NOT_FRAG;
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else
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op.config |= CFG_FIRST_FRAG;
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req_ctx->first_hash = 0;
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} else {
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if (is_last)
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op.config |= CFG_LAST_FRAG;
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else
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op.config |= CFG_MID_FRAG;
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}
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memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
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writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
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/* GO */
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writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
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/*
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* XXX: add timer if the interrupt does not occur for some mystery
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* reason
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*/
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}
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static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
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struct shash_desc *desc)
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{
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int i;
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struct sha1_state shash_state;
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shash_state.count = ctx->count + ctx->count_add;
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for (i = 0; i < 5; i++)
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shash_state.state[i] = ctx->state[i];
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memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
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return crypto_shash_import(desc, &shash_state);
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}
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static int mv_hash_final_fallback(struct ahash_request *req)
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{
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const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
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struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
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struct {
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struct shash_desc shash;
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char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
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} desc;
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int rc;
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desc.shash.tfm = tfm_ctx->fallback;
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desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
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if (unlikely(req_ctx->first_hash)) {
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crypto_shash_init(&desc.shash);
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crypto_shash_update(&desc.shash, req_ctx->buffer,
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req_ctx->extra_bytes);
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} else {
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/* only SHA1 for now....
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*/
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rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
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if (rc)
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goto out;
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}
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rc = crypto_shash_final(&desc.shash, req->result);
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out:
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return rc;
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}
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static void mv_hash_algo_completion(void)
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{
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struct ahash_request *req = ahash_request_cast(cpg->cur_req);
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struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
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if (ctx->extra_bytes)
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copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
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sg_miter_stop(&cpg->p.src_sg_it);
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ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
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ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
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ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
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ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
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ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
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if (likely(ctx->last_chunk)) {
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if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
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memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
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crypto_ahash_digestsize(crypto_ahash_reqtfm
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(req)));
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} else
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mv_hash_final_fallback(req);
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}
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}
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static void dequeue_complete_req(void)
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{
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struct crypto_async_request *req = cpg->cur_req;
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@ -332,7 +491,7 @@ static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
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return i;
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}
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static void mv_enqueue_new_req(struct ablkcipher_request *req)
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static void mv_start_new_crypt_req(struct ablkcipher_request *req)
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{
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struct req_progress *p = &cpg->p;
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int num_sgs;
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@ -353,11 +512,68 @@ static void mv_enqueue_new_req(struct ablkcipher_request *req)
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mv_process_current_q(1);
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}
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static void mv_start_new_hash_req(struct ahash_request *req)
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{
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struct req_progress *p = &cpg->p;
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struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
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const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
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int num_sgs, hw_bytes, old_extra_bytes, rc;
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cpg->cur_req = &req->base;
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memset(p, 0, sizeof(struct req_progress));
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hw_bytes = req->nbytes + ctx->extra_bytes;
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old_extra_bytes = ctx->extra_bytes;
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if (unlikely(ctx->extra_bytes)) {
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memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
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ctx->extra_bytes);
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p->crypt_len = ctx->extra_bytes;
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}
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memcpy(cpg->sram + SRAM_HMAC_IV_IN, tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
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if (unlikely(!ctx->first_hash)) {
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writel(ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
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writel(ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
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writel(ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
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writel(ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
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writel(ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
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}
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ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
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if (ctx->extra_bytes != 0
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&& (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
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hw_bytes -= ctx->extra_bytes;
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else
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ctx->extra_bytes = 0;
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num_sgs = count_sgs(req->src, req->nbytes);
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sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
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if (hw_bytes) {
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p->hw_nbytes = hw_bytes;
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p->complete = mv_hash_algo_completion;
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p->process = mv_process_hash_current;
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mv_process_hash_current(1);
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} else {
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copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
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ctx->extra_bytes - old_extra_bytes);
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sg_miter_stop(&p->src_sg_it);
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if (ctx->last_chunk)
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rc = mv_hash_final_fallback(req);
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else
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rc = 0;
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cpg->eng_st = ENGINE_IDLE;
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local_bh_disable();
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req->base.complete(&req->base, rc);
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local_bh_enable();
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}
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}
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static int queue_manag(void *data)
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{
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cpg->eng_st = ENGINE_IDLE;
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do {
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struct ablkcipher_request *req;
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struct crypto_async_request *async_req = NULL;
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struct crypto_async_request *backlog;
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@ -383,9 +599,18 @@ static int queue_manag(void *data)
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}
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if (async_req) {
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req = container_of(async_req,
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struct ablkcipher_request, base);
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mv_enqueue_new_req(req);
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if (async_req->tfm->__crt_alg->cra_type !=
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&crypto_ahash_type) {
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struct ablkcipher_request *req =
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container_of(async_req,
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struct ablkcipher_request,
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base);
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mv_start_new_crypt_req(req);
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} else {
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struct ahash_request *req =
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ahash_request_cast(async_req);
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mv_start_new_hash_req(req);
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}
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async_req = NULL;
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}
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@ -457,6 +682,215 @@ static int mv_cra_init(struct crypto_tfm *tfm)
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return 0;
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}
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static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
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int is_last, unsigned int req_len,
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int count_add)
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{
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memset(ctx, 0, sizeof(*ctx));
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ctx->op = op;
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ctx->count = req_len;
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ctx->first_hash = 1;
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ctx->last_chunk = is_last;
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ctx->count_add = count_add;
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}
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static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
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unsigned req_len)
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{
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ctx->last_chunk = is_last;
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ctx->count += req_len;
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}
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static int mv_hash_init(struct ahash_request *req)
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{
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const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
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mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
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tfm_ctx->count_add);
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return 0;
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}
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static int mv_hash_update(struct ahash_request *req)
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{
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if (!req->nbytes)
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return 0;
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mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
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return mv_handle_req(&req->base);
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}
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static int mv_hash_final(struct ahash_request *req)
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{
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struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
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/* dummy buffer of 4 bytes */
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sg_init_one(&ctx->dummysg, ctx->buffer, 4);
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/* I think I'm allowed to do that... */
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ahash_request_set_crypt(req, &ctx->dummysg, req->result, 0);
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mv_update_hash_req_ctx(ctx, 1, 0);
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return mv_handle_req(&req->base);
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}
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static int mv_hash_finup(struct ahash_request *req)
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{
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if (!req->nbytes)
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return mv_hash_final(req);
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mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
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return mv_handle_req(&req->base);
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}
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static int mv_hash_digest(struct ahash_request *req)
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{
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const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
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mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
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req->nbytes, tfm_ctx->count_add);
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return mv_handle_req(&req->base);
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}
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static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
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const void *ostate)
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{
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const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
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int i;
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for (i = 0; i < 5; i++) {
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ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
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ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
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}
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}
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static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
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unsigned int keylen)
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{
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int rc;
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struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
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int bs, ds, ss;
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if (!ctx->base_hash)
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return 0;
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rc = crypto_shash_setkey(ctx->fallback, key, keylen);
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if (rc)
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return rc;
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/* Can't see a way to extract the ipad/opad from the fallback tfm
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so I'm basically copying code from the hmac module */
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bs = crypto_shash_blocksize(ctx->base_hash);
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ds = crypto_shash_digestsize(ctx->base_hash);
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ss = crypto_shash_statesize(ctx->base_hash);
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{
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struct {
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struct shash_desc shash;
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char ctx[crypto_shash_descsize(ctx->base_hash)];
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} desc;
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unsigned int i;
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char ipad[ss];
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char opad[ss];
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desc.shash.tfm = ctx->base_hash;
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desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
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CRYPTO_TFM_REQ_MAY_SLEEP;
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if (keylen > bs) {
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int err;
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err =
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crypto_shash_digest(&desc.shash, key, keylen, ipad);
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if (err)
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return err;
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keylen = ds;
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} else
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memcpy(ipad, key, keylen);
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memset(ipad + keylen, 0, bs - keylen);
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memcpy(opad, ipad, bs);
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for (i = 0; i < bs; i++) {
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ipad[i] ^= 0x36;
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opad[i] ^= 0x5c;
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}
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rc = crypto_shash_init(&desc.shash) ? :
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crypto_shash_update(&desc.shash, ipad, bs) ? :
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crypto_shash_export(&desc.shash, ipad) ? :
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crypto_shash_init(&desc.shash) ? :
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crypto_shash_update(&desc.shash, opad, bs) ? :
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crypto_shash_export(&desc.shash, opad);
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if (rc == 0)
|
||||
mv_hash_init_ivs(ctx, ipad, opad);
|
||||
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
|
||||
enum hash_op op, int count_add)
|
||||
{
|
||||
const char *fallback_driver_name = tfm->__crt_alg->cra_name;
|
||||
struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
struct crypto_shash *fallback_tfm = NULL;
|
||||
struct crypto_shash *base_hash = NULL;
|
||||
int err = -ENOMEM;
|
||||
|
||||
ctx->op = op;
|
||||
ctx->count_add = count_add;
|
||||
|
||||
/* Allocate a fallback and abort if it failed. */
|
||||
fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
|
||||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
if (IS_ERR(fallback_tfm)) {
|
||||
printk(KERN_WARNING MV_CESA
|
||||
"Fallback driver '%s' could not be loaded!\n",
|
||||
fallback_driver_name);
|
||||
err = PTR_ERR(fallback_tfm);
|
||||
goto out;
|
||||
}
|
||||
ctx->fallback = fallback_tfm;
|
||||
|
||||
if (base_hash_name) {
|
||||
/* Allocate a hash to compute the ipad/opad of hmac. */
|
||||
base_hash = crypto_alloc_shash(base_hash_name, 0,
|
||||
CRYPTO_ALG_NEED_FALLBACK);
|
||||
if (IS_ERR(base_hash)) {
|
||||
printk(KERN_WARNING MV_CESA
|
||||
"Base driver '%s' could not be loaded!\n",
|
||||
base_hash_name);
|
||||
err = PTR_ERR(fallback_tfm);
|
||||
goto err_bad_base;
|
||||
}
|
||||
}
|
||||
ctx->base_hash = base_hash;
|
||||
|
||||
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
||||
sizeof(struct mv_req_hash_ctx) +
|
||||
crypto_shash_descsize(ctx->fallback));
|
||||
return 0;
|
||||
err_bad_base:
|
||||
crypto_free_shash(fallback_tfm);
|
||||
out:
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mv_cra_hash_exit(struct crypto_tfm *tfm)
|
||||
{
|
||||
struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
|
||||
|
||||
crypto_free_shash(ctx->fallback);
|
||||
if (ctx->base_hash)
|
||||
crypto_free_shash(ctx->base_hash);
|
||||
}
|
||||
|
||||
static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
|
||||
}
|
||||
|
||||
static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
|
||||
{
|
||||
return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
irqreturn_t crypto_int(int irq, void *priv)
|
||||
{
|
||||
u32 val;
|
||||
@ -519,6 +953,53 @@ struct crypto_alg mv_aes_alg_cbc = {
|
||||
},
|
||||
};
|
||||
|
||||
struct ahash_alg mv_sha1_alg = {
|
||||
.init = mv_hash_init,
|
||||
.update = mv_hash_update,
|
||||
.final = mv_hash_final,
|
||||
.finup = mv_hash_finup,
|
||||
.digest = mv_hash_digest,
|
||||
.halg = {
|
||||
.digestsize = SHA1_DIGEST_SIZE,
|
||||
.base = {
|
||||
.cra_name = "sha1",
|
||||
.cra_driver_name = "mv-sha1",
|
||||
.cra_priority = 300,
|
||||
.cra_flags =
|
||||
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_blocksize = SHA1_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
|
||||
.cra_init = mv_cra_hash_sha1_init,
|
||||
.cra_exit = mv_cra_hash_exit,
|
||||
.cra_module = THIS_MODULE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
struct ahash_alg mv_hmac_sha1_alg = {
|
||||
.init = mv_hash_init,
|
||||
.update = mv_hash_update,
|
||||
.final = mv_hash_final,
|
||||
.finup = mv_hash_finup,
|
||||
.digest = mv_hash_digest,
|
||||
.setkey = mv_hash_setkey,
|
||||
.halg = {
|
||||
.digestsize = SHA1_DIGEST_SIZE,
|
||||
.base = {
|
||||
.cra_name = "hmac(sha1)",
|
||||
.cra_driver_name = "mv-hmac-sha1",
|
||||
.cra_priority = 300,
|
||||
.cra_flags =
|
||||
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
|
||||
.cra_blocksize = SHA1_BLOCK_SIZE,
|
||||
.cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
|
||||
.cra_init = mv_cra_hash_hmac_sha1_init,
|
||||
.cra_exit = mv_cra_hash_exit,
|
||||
.cra_module = THIS_MODULE,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static int mv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct crypto_priv *cp;
|
||||
@ -527,7 +1008,7 @@ static int mv_probe(struct platform_device *pdev)
|
||||
int ret;
|
||||
|
||||
if (cpg) {
|
||||
printk(KERN_ERR "Second crypto dev?\n");
|
||||
printk(KERN_ERR MV_CESA "Second crypto dev?\n");
|
||||
return -EEXIST;
|
||||
}
|
||||
|
||||
@ -591,6 +1072,21 @@ static int mv_probe(struct platform_device *pdev)
|
||||
ret = crypto_register_alg(&mv_aes_alg_cbc);
|
||||
if (ret)
|
||||
goto err_unreg_ecb;
|
||||
|
||||
ret = crypto_register_ahash(&mv_sha1_alg);
|
||||
if (ret == 0)
|
||||
cpg->has_sha1 = 1;
|
||||
else
|
||||
printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
|
||||
|
||||
ret = crypto_register_ahash(&mv_hmac_sha1_alg);
|
||||
if (ret == 0) {
|
||||
cpg->has_hmac_sha1 = 1;
|
||||
} else {
|
||||
printk(KERN_WARNING MV_CESA
|
||||
"Could not register hmac-sha1 driver\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_unreg_ecb:
|
||||
crypto_unregister_alg(&mv_aes_alg_ecb);
|
||||
@ -615,6 +1111,10 @@ static int mv_remove(struct platform_device *pdev)
|
||||
|
||||
crypto_unregister_alg(&mv_aes_alg_ecb);
|
||||
crypto_unregister_alg(&mv_aes_alg_cbc);
|
||||
if (cp->has_sha1)
|
||||
crypto_unregister_ahash(&mv_sha1_alg);
|
||||
if (cp->has_hmac_sha1)
|
||||
crypto_unregister_ahash(&mv_hmac_sha1_alg);
|
||||
kthread_stop(cp->queue_th);
|
||||
free_irq(cp->irq, cp);
|
||||
memset(cp->sram, 0, cp->sram_size);
|
||||
|
||||
@ -1,6 +1,10 @@
|
||||
#ifndef __MV_CRYPTO_H__
|
||||
|
||||
#define DIGEST_INITIAL_VAL_A 0xdd00
|
||||
#define DIGEST_INITIAL_VAL_B 0xdd04
|
||||
#define DIGEST_INITIAL_VAL_C 0xdd08
|
||||
#define DIGEST_INITIAL_VAL_D 0xdd0c
|
||||
#define DIGEST_INITIAL_VAL_E 0xdd10
|
||||
#define DES_CMD_REG 0xdd58
|
||||
|
||||
#define SEC_ACCEL_CMD 0xde00
|
||||
@ -70,6 +74,10 @@ struct sec_accel_config {
|
||||
#define CFG_AES_LEN_128 (0 << 24)
|
||||
#define CFG_AES_LEN_192 (1 << 24)
|
||||
#define CFG_AES_LEN_256 (2 << 24)
|
||||
#define CFG_NOT_FRAG (0 << 30)
|
||||
#define CFG_FIRST_FRAG (1 << 30)
|
||||
#define CFG_LAST_FRAG (2 << 30)
|
||||
#define CFG_MID_FRAG (3 << 30)
|
||||
|
||||
u32 enc_p;
|
||||
#define ENC_P_SRC(x) (x)
|
||||
@ -90,7 +98,11 @@ struct sec_accel_config {
|
||||
#define MAC_SRC_TOTAL_LEN(x) ((x) << 16)
|
||||
|
||||
u32 mac_digest;
|
||||
#define MAC_DIGEST_P(x) (x)
|
||||
#define MAC_FRAG_LEN(x) ((x) << 16)
|
||||
u32 mac_iv;
|
||||
#define MAC_INNER_IV_P(x) (x)
|
||||
#define MAC_OUTER_IV_P(x) ((x) << 16)
|
||||
}__attribute__ ((packed));
|
||||
/*
|
||||
* /-----------\ 0
|
||||
@ -101,19 +113,37 @@ struct sec_accel_config {
|
||||
* | IV IN | 4 * 4
|
||||
* |-----------| 0x40 (inplace)
|
||||
* | IV BUF | 4 * 4
|
||||
* |-----------| 0x50
|
||||
* |-----------| 0x80
|
||||
* | DATA IN | 16 * x (max ->max_req_size)
|
||||
* |-----------| 0x50 (inplace operation)
|
||||
* |-----------| 0x80 (inplace operation)
|
||||
* | DATA OUT | 16 * x (max ->max_req_size)
|
||||
* \-----------/ SRAM size
|
||||
*/
|
||||
|
||||
/* Hashing memory map:
|
||||
* /-----------\ 0
|
||||
* | ACCEL CFG | 4 * 8
|
||||
* |-----------| 0x20
|
||||
* | Inner IV | 5 * 4
|
||||
* |-----------| 0x34
|
||||
* | Outer IV | 5 * 4
|
||||
* |-----------| 0x48
|
||||
* | Output BUF| 5 * 4
|
||||
* |-----------| 0x80
|
||||
* | DATA IN | 64 * x (max ->max_req_size)
|
||||
* \-----------/ SRAM size
|
||||
*/
|
||||
#define SRAM_CONFIG 0x00
|
||||
#define SRAM_DATA_KEY_P 0x20
|
||||
#define SRAM_DATA_IV 0x40
|
||||
#define SRAM_DATA_IV_BUF 0x40
|
||||
#define SRAM_DATA_IN_START 0x50
|
||||
#define SRAM_DATA_OUT_START 0x50
|
||||
#define SRAM_DATA_IN_START 0x80
|
||||
#define SRAM_DATA_OUT_START 0x80
|
||||
|
||||
#define SRAM_CFG_SPACE 0x50
|
||||
#define SRAM_HMAC_IV_IN 0x20
|
||||
#define SRAM_HMAC_IV_OUT 0x34
|
||||
#define SRAM_DIGEST_BUF 0x48
|
||||
|
||||
#define SRAM_CFG_SPACE 0x80
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user