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crypto: stm32/crc - Add power management support

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Adding pm and pm_runtime support to STM32 CRC.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
lionel.debieve@st.com 2018-06-26 14:52:46 +02:00 committed by Herbert Xu
parent 8b4d566de6
commit 73463ade0a
1 changed files with 62 additions and 0 deletions
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62
drivers/crypto/stm32/stm32_crc32.c
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@ -8,6 +8,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <crypto/internal/hash.h> #include <crypto/internal/hash.h>
@ -32,6 +33,8 @@
#define POLY_CRC32 0xEDB88320 #define POLY_CRC32 0xEDB88320
#define POLY_CRC32C 0x82F63B78 #define POLY_CRC32C 0x82F63B78
#define CRC_AUTOSUSPEND_DELAY 50
struct stm32_crc { struct stm32_crc {
struct list_head list; struct list_head list;
struct device *dev; struct device *dev;
@ -106,6 +109,8 @@ static int stm32_crc_init(struct shash_desc *desc)
} }
spin_unlock_bh(&crc_list.lock); spin_unlock_bh(&crc_list.lock);
pm_runtime_get_sync(ctx->crc->dev);
/* Reset, set key, poly and configure in bit reverse mode */ /* Reset, set key, poly and configure in bit reverse mode */
writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT); writel_relaxed(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL); writel_relaxed(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
@ -115,6 +120,9 @@ static int stm32_crc_init(struct shash_desc *desc)
ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR); ctx->partial = readl_relaxed(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0; ctx->crc->nb_pending_bytes = 0;
pm_runtime_mark_last_busy(ctx->crc->dev);
pm_runtime_put_autosuspend(ctx->crc->dev);
return 0; return 0;
} }
@ -126,6 +134,8 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
u32 *d32; u32 *d32;
unsigned int i; unsigned int i;
pm_runtime_get_sync(crc->dev);
if (unlikely(crc->nb_pending_bytes)) { if (unlikely(crc->nb_pending_bytes)) {
while (crc->nb_pending_bytes != sizeof(u32) && length) { while (crc->nb_pending_bytes != sizeof(u32) && length) {
/* Fill in pending data */ /* Fill in pending data */
@ -149,6 +159,9 @@ static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
/* Store partial result */ /* Store partial result */
ctx->partial = readl_relaxed(crc->regs + CRC_DR); ctx->partial = readl_relaxed(crc->regs + CRC_DR);
pm_runtime_mark_last_busy(crc->dev);
pm_runtime_put_autosuspend(crc->dev);
/* Check for pending data (non 32 bits) */ /* Check for pending data (non 32 bits) */
length &= 3; length &= 3;
if (likely(!length)) if (likely(!length))
@ -272,6 +285,13 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret; return ret;
} }
pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(dev);
pm_runtime_get_noresume(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);
platform_set_drvdata(pdev, crc); platform_set_drvdata(pdev, crc);
spin_lock(&crc_list.lock); spin_lock(&crc_list.lock);
@ -287,12 +307,18 @@ static int stm32_crc_probe(struct platform_device *pdev)
dev_info(dev, "Initialized\n"); dev_info(dev, "Initialized\n");
pm_runtime_put_sync(dev);
return 0; return 0;
} }
static int stm32_crc_remove(struct platform_device *pdev) static int stm32_crc_remove(struct platform_device *pdev)
{ {
struct stm32_crc *crc = platform_get_drvdata(pdev); struct stm32_crc *crc = platform_get_drvdata(pdev);
int ret = pm_runtime_get_sync(crc->dev);
if (ret < 0)
return ret;
spin_lock(&crc_list.lock); spin_lock(&crc_list.lock);
list_del(&crc->list); list_del(&crc->list);
@ -300,11 +326,46 @@ static int stm32_crc_remove(struct platform_device *pdev)
crypto_unregister_shashes(algs, ARRAY_SIZE(algs)); crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
pm_runtime_disable(crc->dev);
pm_runtime_put_noidle(crc->dev);
clk_disable_unprepare(crc->clk); clk_disable_unprepare(crc->clk);
return 0; return 0;
} }
#ifdef CONFIG_PM
static int stm32_crc_runtime_suspend(struct device *dev)
{
struct stm32_crc *crc = dev_get_drvdata(dev);
clk_disable_unprepare(crc->clk);
return 0;
}
static int stm32_crc_runtime_resume(struct device *dev)
{
struct stm32_crc *crc = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(crc->clk);
if (ret) {
dev_err(crc->dev, "Failed to prepare_enable clock\n");
return ret;
}
return 0;
}
#endif
static const struct dev_pm_ops stm32_crc_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
stm32_crc_runtime_resume, NULL)
};
static const struct of_device_id stm32_dt_ids[] = { static const struct of_device_id stm32_dt_ids[] = {
{ .compatible = "st,stm32f7-crc", }, { .compatible = "st,stm32f7-crc", },
{}, {},
@ -316,6 +377,7 @@ static struct platform_driver stm32_crc_driver = {
.remove = stm32_crc_remove, .remove = stm32_crc_remove,
.driver = { .driver = {
.name = DRIVER_NAME, .name = DRIVER_NAME,
.pm = &stm32_crc_pm_ops,
.of_match_table = stm32_dt_ids, .of_match_table = stm32_dt_ids,
}, },
}; };