forked from Minki/linux
intelfb: prepare for i9xx support.
This code just moves the PLL min/max calculations variables into a structure, it doesn't change or add any new functionality. Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Dave Airlie
parent
6fdb94bd95
commit
7258b11d2e
@ -40,6 +40,26 @@
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#include "intelfb.h"
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#include "intelfbhw.h"
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struct pll_min_max {
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int min_m, max_m;
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int min_m1, max_m1;
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int min_m2, max_m2;
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int min_n, max_n;
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int min_p, max_p;
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int min_p1, max_p1;
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int min_vco_freq, max_vco_freq;
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int p_transition_clock;
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};
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#define PLLS_I8xx 0
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#define PLLS_I9xx 1
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#define PLLS_MAX 2
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struct pll_min_max plls[PLLS_MAX] = {
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{ 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000 }, //I8xx
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{ 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000 } //I9xx
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};
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int
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intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
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int *mobile)
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@ -697,17 +717,17 @@ intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
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/* Split the M parameter into M1 and M2. */
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static int
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splitm(unsigned int m, unsigned int *retm1, unsigned int *retm2)
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splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
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{
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int m1, m2;
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m1 = (m - 2 - (MIN_M2 + MAX_M2) / 2) / 5 - 2;
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if (m1 < MIN_M1)
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m1 = MIN_M1;
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if (m1 > MAX_M1)
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m1 = MAX_M1;
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m1 = (m - 2 - (plls[index].min_m1 + plls[index].max_m2) / 2) / 5 - 2;
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if (m1 < plls[index].min_m1)
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m1 = plls[index].min_m1;
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if (m1 > plls[index].max_m1)
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m1 = plls[index].max_m1;
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m2 = m - 5 * (m1 + 2) - 2;
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if (m2 < MIN_M2 || m2 > MAX_M2 || m2 >= m1) {
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if (m2 < plls[index].min_m2 || m2 > plls[index].max_m2 || m2 >= m1) {
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return 1;
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} else {
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*retm1 = (unsigned int)m1;
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@ -718,30 +738,34 @@ splitm(unsigned int m, unsigned int *retm1, unsigned int *retm2)
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/* Split the P parameter into P1 and P2. */
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static int
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splitp(unsigned int p, unsigned int *retp1, unsigned int *retp2)
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splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
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{
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int p1, p2;
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if (p % 4 == 0)
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p2 = 1;
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else
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p2 = 0;
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p1 = (p / (1 << (p2 + 1))) - 2;
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if (p % 4 == 0 && p1 < MIN_P1) {
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p2 = 0;
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if (index==PLLS_I8xx)
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{
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if (p % 4 == 0)
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p2 = 1;
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else
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p2 = 0;
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p1 = (p / (1 << (p2 + 1))) - 2;
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if (p % 4 == 0 && p1 < plls[index].min_p1) {
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p2 = 0;
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p1 = (p / (1 << (p2 + 1))) - 2;
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}
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if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
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return 1;
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} else {
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*retp1 = (unsigned int)p1;
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*retp2 = (unsigned int)p2;
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return 0;
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}
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}
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if (p1 < MIN_P1 || p1 > MAX_P1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
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return 1;
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} else {
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*retp1 = (unsigned int)p1;
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*retp2 = (unsigned int)p2;
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return 0;
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}
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return 1;
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}
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static int
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calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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u32 *retp2, u32 *retclock)
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{
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u32 m1, m2, n, p1, p2, n1;
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@ -756,40 +780,40 @@ calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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DBG_MSG("Clock is %d\n", clock);
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div_max = MAX_VCO_FREQ / clock;
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div_min = ROUND_UP_TO(MIN_VCO_FREQ, clock) / clock;
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div_max = plls[index].max_vco_freq / clock;
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div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
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if (clock <= P_TRANSITION_CLOCK)
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if (clock <= plls[index].p_transition_clock)
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p_inc = 4;
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else
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p_inc = 2;
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p_min = ROUND_UP_TO(div_min, p_inc);
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p_max = ROUND_DOWN_TO(div_max, p_inc);
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if (p_min < MIN_P)
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if (p_min < plls[index].min_p)
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p_min = 4;
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if (p_max > MAX_P)
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if (p_max > plls[index].max_p)
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p_max = 128;
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DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
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p = p_min;
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do {
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if (splitp(p, &p1, &p2)) {
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if (splitp(index, p, &p1, &p2)) {
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WRN_MSG("cannot split p = %d\n", p);
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p += p_inc;
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continue;
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}
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n = MIN_N;
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n = plls[index].min_n;
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f_vco = clock * p;
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do {
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m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
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if (m < MIN_M)
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m = MIN_M;
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if (m > MAX_M)
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m = MAX_M;
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if (m < plls[index].min_m)
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m = plls[index].min_m;
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if (m > plls[index].max_m)
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m = plls[index].max_m;
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f_out = CALC_VCLOCK3(m, n, p);
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if (splitm(m, &m1, &m2)) {
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if (splitm(index, m, &m1, &m2)) {
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WRN_MSG("cannot split m = %d\n", m);
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n++;
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continue;
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@ -807,7 +831,7 @@ calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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err_best = f_err;
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}
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n++;
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} while ((n <= MAX_N) && (f_out >= clock));
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} while ((n <= plls[index].max_n) && (f_out >= clock));
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p += p_inc;
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} while ((p <= p_max));
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@ -818,8 +842,8 @@ calc_pll_params(int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
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m = m_best;
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n = n_best;
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p = p_best;
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splitm(m, &m1, &m2);
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splitp(p, &p1, &p2);
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splitm(index, m, &m1, &m2);
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splitp(index, p, &p1, &p2);
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n1 = n - 2;
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DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
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@ -929,7 +953,7 @@ intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
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/* Desired clock in kHz */
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clock_target = 1000000000 / var->pixclock;
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if (calc_pll_params(clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
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if (calc_pll_params(PLLS_I8xx, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
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WRN_MSG("calc_pll_params failed\n");
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return 1;
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}
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@ -155,23 +155,8 @@
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/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
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/* Clock values are in units of kHz */
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#define PLL_REFCLK 48000
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#define MIN_VCO_FREQ 930000
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#define MAX_VCO_FREQ 1400000
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#define MIN_CLOCK 25000
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#define MAX_CLOCK 350000
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#define P_TRANSITION_CLOCK 165000
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#define MIN_M 108
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#define MAX_M 140
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#define MIN_M1 18
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#define MAX_M1 26
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#define MIN_M2 6
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#define MAX_M2 16
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#define MIN_P 4
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#define MAX_P 128
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#define MIN_P1 0
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#define MAX_P1 31
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#define MIN_N 3
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#define MAX_N 16
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#define CALC_VCLOCK(m1, m2, n, p1, p2) \
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((PLL_REFCLK * (5 * ((m1) + 2) + ((m2) + 2)) / ((n) + 2)) / \
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