forked from Minki/linux
net/mlx5: Allocating a pool of MSI-X vectors for SFs
SFs (Sub Functions) currently use IRQs from the global IRQ table their parent Physical Function have. In order to better scale, we need to allocate more IRQs and share them between different SFs. Driver will maintain 3 separated irq pools: 1. A pool that serve the PF consumer (PF's netdev, rdma stacks), similar to what the driver had before this patch. i.e, this pool will share irqs between rdma and netev, and will keep the irq indexes and allocation order. The last is important for PF netdev rmap (aRFS). 2. A pool of control IRQs for SFs. The size of this pool is the number of SFs that can be created divided by SFS_PER_IRQ. This pool will serve the control path EQs of the SFs. 3. A pool of completion data path IRQs for SFs transport queues. The size of this pool is: num_irqs_allocated - pf_pool_size - sf_ctrl_pool_size. This pool will served netdev and rdma stacks. Moreover, rmap is not supported on SFs. Sharing methodology of the SFs pools is explained in the next patch. Important note: rmap is not supported on SFs because rmap mapping cannot function correctly for IRQs that are shared for different core/netdev RX rings. Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Shay Drory
Saeed Mahameed
parent
fc63dd2a85
commit
71e084e264
@ -471,14 +471,7 @@ static int create_async_eq(struct mlx5_core_dev *dev,
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int err;
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mutex_lock(&eq_table->lock);
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/* Async EQs must share irq index 0 */
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if (param->irq_index != 0) {
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err = -EINVAL;
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goto unlock;
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}
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err = create_map_eq(dev, eq, param);
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unlock:
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mutex_unlock(&eq_table->lock);
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return err;
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}
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@ -996,8 +989,11 @@ int mlx5_eq_table_create(struct mlx5_core_dev *dev)
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eq_table->num_comp_eqs =
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min_t(int,
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mlx5_irq_get_num_comp(eq_table->irq_table),
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mlx5_irq_table_get_num_comp(eq_table->irq_table),
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num_eqs - MLX5_MAX_ASYNC_EQS);
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if (mlx5_core_is_sf(dev))
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eq_table->num_comp_eqs = min_t(int, eq_table->num_comp_eqs,
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MLX5_COMP_EQS_PER_SF);
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err = create_async_eqs(dev);
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if (err) {
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@ -6,13 +6,17 @@
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#include <linux/mlx5/driver.h>
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#define MLX5_COMP_EQS_PER_SF 8
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#define MLX5_IRQ_EQ_CTRL (0)
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struct mlx5_irq;
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int mlx5_irq_table_init(struct mlx5_core_dev *dev);
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void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);
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int mlx5_irq_table_create(struct mlx5_core_dev *dev);
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void mlx5_irq_table_destroy(struct mlx5_core_dev *dev);
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int mlx5_irq_get_num_comp(struct mlx5_irq_table *table);
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int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table);
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struct mlx5_irq_table *mlx5_irq_table_get(struct mlx5_core_dev *dev);
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int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, int devfn,
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@ -7,11 +7,19 @@
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#include <linux/mlx5/driver.h>
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#include "mlx5_core.h"
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#include "mlx5_irq.h"
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#include "sf/sf.h"
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#ifdef CONFIG_RFS_ACCEL
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#include <linux/cpu_rmap.h>
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#endif
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#define MLX5_MAX_IRQ_NAME (32)
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/* max irq_index is 255. three chars */
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#define MLX5_MAX_IRQ_IDX_CHARS (3)
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#define MLX5_SFS_PER_CTRL_IRQ 64
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#define MLX5_IRQ_CTRL_SF_MAX 8
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/* min num of vectores for SFs to be enabled */
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#define MLX5_IRQ_VEC_COMP_BASE_SF 2
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struct mlx5_irq {
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u32 index;
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@ -20,42 +28,22 @@ struct mlx5_irq {
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char name[MLX5_MAX_IRQ_NAME];
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struct kref kref;
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int irqn;
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struct mlx5_irq_table *table;
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struct mlx5_irq_pool *pool;
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};
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struct mlx5_irq_pool {
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char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
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struct xa_limit xa_num_irqs;
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struct xarray irqs;
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struct mlx5_core_dev *dev;
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};
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struct mlx5_irq_table {
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struct xarray irqs;
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int nvec;
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struct mlx5_irq_pool *pf_pool;
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struct mlx5_irq_pool *sf_ctrl_pool;
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struct mlx5_irq_pool *sf_comp_pool;
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};
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int mlx5_irq_table_init(struct mlx5_core_dev *dev)
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{
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struct mlx5_irq_table *irq_table;
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if (mlx5_core_is_sf(dev))
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return 0;
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irq_table = kvzalloc(sizeof(*irq_table), GFP_KERNEL);
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if (!irq_table)
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return -ENOMEM;
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dev->priv.irq_table = irq_table;
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return 0;
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}
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void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev)
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{
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if (mlx5_core_is_sf(dev))
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return;
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kvfree(dev->priv.irq_table);
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}
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int mlx5_irq_get_num_comp(struct mlx5_irq_table *table)
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{
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return table->nvec - MLX5_IRQ_VEC_COMP_BASE;
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}
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/**
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* mlx5_get_default_msix_vec_count - Get the default number of MSI-X vectors
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* to be ssigned to each VF.
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@ -144,9 +132,9 @@ out:
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static void irq_release(struct kref *kref)
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{
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struct mlx5_irq *irq = container_of(kref, struct mlx5_irq, kref);
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struct mlx5_irq_table *table = irq->table;
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struct mlx5_irq_pool *pool = irq->pool;
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xa_erase(&table->irqs, irq->index);
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xa_erase(&pool->irqs, irq->index);
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/* free_irq requires that affinity and rmap will be cleared
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* before calling it. This is why there is asymmetry with set_rmap
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* which should be called after alloc_irq but before request_irq.
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@ -162,6 +150,76 @@ static void irq_put(struct mlx5_irq *irq)
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kref_put(&irq->kref, irq_release);
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}
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static irqreturn_t irq_int_handler(int irq, void *nh)
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{
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atomic_notifier_call_chain(nh, 0, NULL);
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return IRQ_HANDLED;
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}
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static void irq_sf_set_name(struct mlx5_irq_pool *pool, char *name, int vecidx)
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{
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snprintf(name, MLX5_MAX_IRQ_NAME, "%s%d", pool->name, vecidx);
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}
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static void irq_set_name(char *name, int vecidx)
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{
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if (vecidx == 0) {
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_async%d", vecidx);
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return;
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}
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d",
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vecidx - MLX5_IRQ_VEC_COMP_BASE);
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}
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static struct mlx5_irq *irq_request(struct mlx5_irq_pool *pool, int i)
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{
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struct mlx5_core_dev *dev = pool->dev;
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char name[MLX5_MAX_IRQ_NAME];
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struct mlx5_irq *irq;
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int err;
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irq = kzalloc(sizeof(*irq), GFP_KERNEL);
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if (!irq)
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return ERR_PTR(-ENOMEM);
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irq->irqn = pci_irq_vector(dev->pdev, i);
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if (!pool->name[0])
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irq_set_name(name, i);
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else
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irq_sf_set_name(pool, name, i);
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ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh);
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snprintf(irq->name, MLX5_MAX_IRQ_NAME,
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"%s@pci:%s", name, pci_name(dev->pdev));
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err = request_irq(irq->irqn, irq_int_handler, 0, irq->name,
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&irq->nh);
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if (err) {
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mlx5_core_err(dev, "Failed to request irq. err = %d\n", err);
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goto err_req_irq;
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}
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if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) {
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mlx5_core_warn(dev, "zalloc_cpumask_var failed\n");
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err = -ENOMEM;
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goto err_cpumask;
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}
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err = xa_alloc(&pool->irqs, &irq->index, irq, pool->xa_num_irqs,
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GFP_KERNEL);
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if (err) {
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mlx5_core_err(dev, "Failed to alloc xa entry for irq(%u). err = %d\n",
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irq->index, err);
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goto err_xa;
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}
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irq->pool = pool;
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kref_init(&irq->kref);
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return irq;
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err_xa:
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free_cpumask_var(irq->mask);
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err_cpumask:
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free_irq(irq->irqn, &irq->nh);
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err_req_irq:
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kfree(irq);
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return ERR_PTR(err);
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}
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int mlx5_irq_attach_nb(struct mlx5_irq *irq, struct notifier_block *nb)
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{
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int err;
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@ -184,69 +242,9 @@ int mlx5_irq_detach_nb(struct mlx5_irq *irq, struct notifier_block *nb)
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return atomic_notifier_chain_unregister(&irq->nh, nb);
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}
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static irqreturn_t irq_int_handler(int irq, void *nh)
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struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq)
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{
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atomic_notifier_call_chain(nh, 0, NULL);
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return IRQ_HANDLED;
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}
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static void irq_set_name(char *name, int vecidx)
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{
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if (!vecidx) {
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_async");
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return;
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}
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snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d",
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vecidx - MLX5_IRQ_VEC_COMP_BASE);
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}
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static struct mlx5_irq *irq_request(struct mlx5_core_dev *dev, int i)
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{
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struct mlx5_irq_table *table = mlx5_irq_table_get(dev);
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char name[MLX5_MAX_IRQ_NAME];
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struct xa_limit xa_num_irqs;
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struct mlx5_irq *irq;
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int err;
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irq = kzalloc(sizeof(*irq), GFP_KERNEL);
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if (!irq)
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return ERR_PTR(-ENOMEM);
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irq->irqn = pci_irq_vector(dev->pdev, i);
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irq_set_name(name, i);
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ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh);
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snprintf(irq->name, MLX5_MAX_IRQ_NAME,
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"%s@pci:%s", name, pci_name(dev->pdev));
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err = request_irq(irq->irqn, irq_int_handler, 0, irq->name,
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&irq->nh);
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if (err) {
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mlx5_core_err(dev, "Failed to request irq. err = %d\n", err);
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goto err_req_irq;
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}
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if (!zalloc_cpumask_var(&irq->mask, GFP_KERNEL)) {
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mlx5_core_warn(dev, "zalloc_cpumask_var failed\n");
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err = -ENOMEM;
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goto err_cpumask;
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}
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xa_num_irqs.min = 0;
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xa_num_irqs.max = table->nvec;
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err = xa_alloc(&table->irqs, &irq->index, irq, xa_num_irqs,
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GFP_KERNEL);
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if (err) {
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mlx5_core_err(dev, "Failed to alloc xa entry for irq(%u). err = %d\n",
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irq->index, err);
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goto err_xa;
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}
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irq->table = table;
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kref_init(&irq->kref);
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return irq;
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err_xa:
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free_cpumask_var(irq->mask);
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err_cpumask:
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free_irq(irq->irqn, &irq->nh);
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err_req_irq:
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kfree(irq);
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return ERR_PTR(err);
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return irq->mask;
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}
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/**
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@ -272,14 +270,17 @@ struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, int vecidx,
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struct cpumask *affinity)
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{
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struct mlx5_irq_table *irq_table = mlx5_irq_table_get(dev);
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struct mlx5_irq_pool *pool;
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struct mlx5_irq *irq;
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irq = xa_load(&irq_table->irqs, vecidx);
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pool = irq_table->pf_pool;
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irq = xa_load(&pool->irqs, vecidx);
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if (irq) {
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kref_get(&irq->kref);
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return irq;
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}
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irq = irq_request(dev, vecidx);
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irq = irq_request(pool, vecidx);
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if (IS_ERR(irq))
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return irq;
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cpumask_copy(irq->mask, affinity);
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@ -287,53 +288,162 @@ struct mlx5_irq *mlx5_irq_request(struct mlx5_core_dev *dev, int vecidx,
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return irq;
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}
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struct cpumask *mlx5_irq_get_affinity_mask(struct mlx5_irq *irq)
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/* irq_pool API */
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static struct mlx5_irq_pool *
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irq_pool_alloc(struct mlx5_core_dev *dev, int start, int size, char *name)
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{
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return irq->mask;
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struct mlx5_irq_pool *pool = kvzalloc(sizeof(*pool), GFP_KERNEL);
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if (!pool)
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return ERR_PTR(-ENOMEM);
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pool->dev = dev;
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xa_init_flags(&pool->irqs, XA_FLAGS_ALLOC);
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pool->xa_num_irqs.min = start;
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pool->xa_num_irqs.max = start + size - 1;
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if (name)
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snprintf(pool->name, MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS,
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name);
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mlx5_core_dbg(dev, "pool->name = %s, pool->size = %d, pool->start = %d",
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name, size, start);
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return pool;
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}
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static void irq_pool_free(struct mlx5_irq_pool *pool)
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{
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struct mlx5_irq *irq;
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unsigned long index;
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xa_for_each(&pool->irqs, index, irq)
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irq_release(&irq->kref);
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xa_destroy(&pool->irqs);
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kvfree(pool);
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}
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static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pf_vec)
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{
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struct mlx5_irq_table *table = dev->priv.irq_table;
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int num_sf_ctrl_by_msix;
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int num_sf_ctrl_by_sfs;
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int num_sf_ctrl;
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int err;
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/* init pf_pool */
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table->pf_pool = irq_pool_alloc(dev, 0, pf_vec, NULL);
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if (IS_ERR(table->pf_pool))
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return PTR_ERR(table->pf_pool);
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if (!mlx5_sf_max_functions(dev))
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return 0;
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if (sf_vec < MLX5_IRQ_VEC_COMP_BASE_SF) {
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mlx5_core_err(dev, "Not enught IRQs for SFs. SF may run at lower performance\n");
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return 0;
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}
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/* init sf_ctrl_pool */
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num_sf_ctrl_by_msix = DIV_ROUND_UP(sf_vec, MLX5_COMP_EQS_PER_SF);
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num_sf_ctrl_by_sfs = DIV_ROUND_UP(mlx5_sf_max_functions(dev),
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MLX5_SFS_PER_CTRL_IRQ);
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num_sf_ctrl = min_t(int, num_sf_ctrl_by_msix, num_sf_ctrl_by_sfs);
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num_sf_ctrl = min_t(int, MLX5_IRQ_CTRL_SF_MAX, num_sf_ctrl);
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table->sf_ctrl_pool = irq_pool_alloc(dev, pf_vec, num_sf_ctrl,
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"mlx5_sf_ctrl");
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if (IS_ERR(table->sf_ctrl_pool)) {
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err = PTR_ERR(table->sf_ctrl_pool);
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goto err_pf;
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}
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/* init sf_comp_pool */
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table->sf_comp_pool = irq_pool_alloc(dev, pf_vec + num_sf_ctrl,
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sf_vec - num_sf_ctrl, "mlx5_sf_comp");
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if (IS_ERR(table->sf_comp_pool)) {
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err = PTR_ERR(table->sf_comp_pool);
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goto err_sf_ctrl;
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}
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return 0;
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err_sf_ctrl:
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irq_pool_free(table->sf_ctrl_pool);
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err_pf:
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irq_pool_free(table->pf_pool);
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return err;
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}
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static void irq_pools_destroy(struct mlx5_irq_table *table)
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{
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if (table->sf_ctrl_pool) {
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irq_pool_free(table->sf_comp_pool);
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irq_pool_free(table->sf_ctrl_pool);
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}
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irq_pool_free(table->pf_pool);
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}
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/* irq_table API */
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int mlx5_irq_table_init(struct mlx5_core_dev *dev)
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{
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struct mlx5_irq_table *irq_table;
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if (mlx5_core_is_sf(dev))
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return 0;
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irq_table = kvzalloc(sizeof(*irq_table), GFP_KERNEL);
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if (!irq_table)
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return -ENOMEM;
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dev->priv.irq_table = irq_table;
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return 0;
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}
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|
||||
void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev)
|
||||
{
|
||||
if (mlx5_core_is_sf(dev))
|
||||
return;
|
||||
|
||||
kvfree(dev->priv.irq_table);
|
||||
}
|
||||
|
||||
int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table)
|
||||
{
|
||||
return table->pf_pool->xa_num_irqs.max - table->pf_pool->xa_num_irqs.min;
|
||||
}
|
||||
|
||||
int mlx5_irq_table_create(struct mlx5_core_dev *dev)
|
||||
{
|
||||
struct mlx5_priv *priv = &dev->priv;
|
||||
struct mlx5_irq_table *table = priv->irq_table;
|
||||
int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
|
||||
MLX5_CAP_GEN(dev, max_num_eqs) :
|
||||
1 << MLX5_CAP_GEN(dev, log_max_eq);
|
||||
int nvec;
|
||||
int total_vec;
|
||||
int pf_vec;
|
||||
int err;
|
||||
|
||||
if (mlx5_core_is_sf(dev))
|
||||
return 0;
|
||||
|
||||
nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
|
||||
pf_vec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
|
||||
MLX5_IRQ_VEC_COMP_BASE;
|
||||
nvec = min_t(int, nvec, num_eqs);
|
||||
if (nvec <= MLX5_IRQ_VEC_COMP_BASE)
|
||||
pf_vec = min_t(int, pf_vec, num_eqs);
|
||||
if (pf_vec <= MLX5_IRQ_VEC_COMP_BASE)
|
||||
return -ENOMEM;
|
||||
|
||||
xa_init_flags(&table->irqs, XA_FLAGS_ALLOC);
|
||||
total_vec = pf_vec;
|
||||
if (mlx5_sf_max_functions(dev))
|
||||
total_vec += MLX5_IRQ_CTRL_SF_MAX +
|
||||
MLX5_COMP_EQS_PER_SF * mlx5_sf_max_functions(dev);
|
||||
|
||||
nvec = pci_alloc_irq_vectors(dev->pdev, MLX5_IRQ_VEC_COMP_BASE + 1,
|
||||
nvec, PCI_IRQ_MSIX);
|
||||
if (nvec < 0) {
|
||||
err = nvec;
|
||||
goto err_free_irq;
|
||||
}
|
||||
total_vec = pci_alloc_irq_vectors(dev->pdev, MLX5_IRQ_VEC_COMP_BASE + 1,
|
||||
total_vec, PCI_IRQ_MSIX);
|
||||
if (total_vec < 0)
|
||||
return total_vec;
|
||||
pf_vec = min(pf_vec, total_vec);
|
||||
|
||||
table->nvec = nvec;
|
||||
err = irq_pools_init(dev, total_vec - pf_vec, pf_vec);
|
||||
if (err)
|
||||
pci_free_irq_vectors(dev->pdev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_irq:
|
||||
xa_destroy(&table->irqs);
|
||||
return err;
|
||||
}
|
||||
|
||||
void mlx5_irq_table_destroy(struct mlx5_core_dev *dev)
|
||||
{
|
||||
struct mlx5_irq_table *table = dev->priv.irq_table;
|
||||
struct mlx5_irq *irq;
|
||||
unsigned long index;
|
||||
|
||||
if (mlx5_core_is_sf(dev))
|
||||
return;
|
||||
@ -341,10 +451,8 @@ void mlx5_irq_table_destroy(struct mlx5_core_dev *dev)
|
||||
/* There are cases where IRQs still will be in used when we reaching
|
||||
* to here. Hence, making sure all the irqs are realeased.
|
||||
*/
|
||||
xa_for_each(&table->irqs, index, irq)
|
||||
irq_release(&irq->kref);
|
||||
irq_pools_destroy(table);
|
||||
pci_free_irq_vectors(dev->pdev);
|
||||
xa_destroy(&table->irqs);
|
||||
}
|
||||
|
||||
struct mlx5_irq_table *mlx5_irq_table_get(struct mlx5_core_dev *dev)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user