forked from Minki/linux
irqchip fixes for v4.0
- armada-370-xp
- Chained per-cpu interrupts
- gic{,-v3,v3-its}
- Various fixes for safer operation
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Merge tag 'irqchip-fixes-4.0' of git://git.infradead.org/users/jcooper/linux
Pull irqchip fixes from Jason Cooper:
"armada-370-xp:
- Chained per-cpu interrupts
gic{,-v3,v3-its}"
- Various fixes for safer operation"
* tag 'irqchip-fixes-4.0' of git://git.infradead.org/users/jcooper/linux:
irqchip: gicv3-its: Support safe initialization
irqchip: gicv3-its: Define macros for GITS_CTLR fields
irqchip: gicv3-its: Add limitation to page order
irqchip: gicv3-its: Use 64KB page as default granule
irqchip: gicv3-its: Zero itt before handling to hardware
irqchip: gic-v3: Fix out of bounds access to cpu_logical_map
irqchip: gic: Fix unsafe locking reported by lockdep
irqchip: gicv3-its: Fix unsafe locking reported by lockdep
irqchip: gicv3-its: Iterate over PCI aliases to generate ITS configuration
irqchip: gicv3-its: Allocate enough memory for the full range of DeviceID
irqchip: gicv3-its: Fix ITS CPU init
irqchip: armada-370-xp: Fix chained per-cpu interrupts
This commit is contained in:
Linus Torvalds
commit
71c87bd062
@ -69,6 +69,7 @@ static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static u32 doorbell_mask_reg;
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static int parent_irq;
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#ifdef CONFIG_PCI_MSI
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static struct irq_domain *armada_370_xp_msi_domain;
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static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
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@ -356,6 +357,7 @@ static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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armada_xp_mpic_smp_cpu_init();
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return NOTIFY_OK;
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}
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@ -364,6 +366,20 @@ static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
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.priority = 100,
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};
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static int mpic_cascaded_secondary_init(struct notifier_block *nfb,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
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enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
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return NOTIFY_OK;
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}
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static struct notifier_block mpic_cascaded_cpu_notifier = {
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.notifier_call = mpic_cascaded_secondary_init,
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.priority = 100,
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};
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#endif /* CONFIG_SMP */
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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@ -539,7 +555,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource main_int_res, per_cpu_int_res;
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int parent_irq, nr_irqs, i;
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int nr_irqs, i;
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u32 control;
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BUG_ON(of_address_to_resource(node, 0, &main_int_res));
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@ -587,6 +603,9 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
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#endif
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} else {
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#ifdef CONFIG_SMP
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register_cpu_notifier(&mpic_cascaded_cpu_notifier);
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#endif
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irq_set_chained_handler(parent_irq,
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armada_370_xp_mpic_handle_cascade_irq);
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}
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@ -416,13 +416,14 @@ static void its_send_single_command(struct its_node *its,
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{
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struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
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struct its_collection *sync_col;
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unsigned long flags;
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raw_spin_lock(&its->lock);
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raw_spin_lock_irqsave(&its->lock, flags);
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cmd = its_allocate_entry(its);
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if (!cmd) { /* We're soooooo screewed... */
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pr_err_ratelimited("ITS can't allocate, dropping command\n");
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raw_spin_unlock(&its->lock);
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raw_spin_unlock_irqrestore(&its->lock, flags);
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return;
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}
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sync_col = builder(cmd, desc);
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@ -442,7 +443,7 @@ static void its_send_single_command(struct its_node *its,
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post:
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next_cmd = its_post_commands(its);
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raw_spin_unlock(&its->lock);
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raw_spin_unlock_irqrestore(&its->lock, flags);
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its_wait_for_range_completion(its, cmd, next_cmd);
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}
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@ -799,21 +800,43 @@ static int its_alloc_tables(struct its_node *its)
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{
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int err;
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int i;
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int psz = PAGE_SIZE;
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int psz = SZ_64K;
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u64 shr = GITS_BASER_InnerShareable;
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for (i = 0; i < GITS_BASER_NR_REGS; i++) {
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u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
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u64 type = GITS_BASER_TYPE(val);
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u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
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int order = get_order(psz);
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int alloc_size;
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u64 tmp;
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void *base;
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if (type == GITS_BASER_TYPE_NONE)
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continue;
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/* We're lazy and only allocate a single page for now */
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base = (void *)get_zeroed_page(GFP_KERNEL);
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/*
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* Allocate as many entries as required to fit the
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* range of device IDs that the ITS can grok... The ID
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* space being incredibly sparse, this results in a
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* massive waste of memory.
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*
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* For other tables, only allocate a single page.
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*/
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if (type == GITS_BASER_TYPE_DEVICE) {
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u64 typer = readq_relaxed(its->base + GITS_TYPER);
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u32 ids = GITS_TYPER_DEVBITS(typer);
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order = get_order((1UL << ids) * entry_size);
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if (order >= MAX_ORDER) {
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order = MAX_ORDER - 1;
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pr_warn("%s: Device Table too large, reduce its page order to %u\n",
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its->msi_chip.of_node->full_name, order);
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}
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}
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alloc_size = (1 << order) * PAGE_SIZE;
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base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (!base) {
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err = -ENOMEM;
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goto out_free;
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@ -841,7 +864,7 @@ retry_baser:
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break;
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}
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val |= (PAGE_SIZE / psz) - 1;
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val |= (alloc_size / psz) - 1;
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writeq_relaxed(val, its->base + GITS_BASER + i * 8);
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tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
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@ -882,7 +905,7 @@ retry_baser:
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}
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pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
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(int)(PAGE_SIZE / entry_size),
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(int)(alloc_size / entry_size),
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its_base_type_string[type],
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(unsigned long)virt_to_phys(base),
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psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
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@ -1020,8 +1043,9 @@ static void its_cpu_init_collection(void)
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static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
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{
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struct its_device *its_dev = NULL, *tmp;
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unsigned long flags;
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raw_spin_lock(&its->lock);
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raw_spin_lock_irqsave(&its->lock, flags);
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list_for_each_entry(tmp, &its->its_device_list, entry) {
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if (tmp->device_id == dev_id) {
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@ -1030,7 +1054,7 @@ static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
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}
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}
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raw_spin_unlock(&its->lock);
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raw_spin_unlock_irqrestore(&its->lock, flags);
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return its_dev;
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}
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@ -1040,6 +1064,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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{
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struct its_device *dev;
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unsigned long *lpi_map;
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unsigned long flags;
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void *itt;
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int lpi_base;
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int nr_lpis;
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@ -1056,7 +1081,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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nr_ites = max(2UL, roundup_pow_of_two(nvecs));
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sz = nr_ites * its->ite_size;
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sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
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itt = kmalloc(sz, GFP_KERNEL);
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itt = kzalloc(sz, GFP_KERNEL);
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lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
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if (!dev || !itt || !lpi_map) {
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@ -1075,9 +1100,9 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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dev->device_id = dev_id;
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INIT_LIST_HEAD(&dev->entry);
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raw_spin_lock(&its->lock);
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raw_spin_lock_irqsave(&its->lock, flags);
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list_add(&dev->entry, &its->its_device_list);
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raw_spin_unlock(&its->lock);
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raw_spin_unlock_irqrestore(&its->lock, flags);
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/* Bind the device to the first possible CPU */
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cpu = cpumask_first(cpu_online_mask);
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@ -1091,9 +1116,11 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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static void its_free_device(struct its_device *its_dev)
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{
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raw_spin_lock(&its_dev->its->lock);
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unsigned long flags;
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raw_spin_lock_irqsave(&its_dev->its->lock, flags);
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list_del(&its_dev->entry);
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raw_spin_unlock(&its_dev->its->lock);
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raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
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kfree(its_dev->itt);
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kfree(its_dev);
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}
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@ -1112,31 +1139,69 @@ static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
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return 0;
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}
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struct its_pci_alias {
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struct pci_dev *pdev;
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u32 dev_id;
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u32 count;
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};
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static int its_pci_msi_vec_count(struct pci_dev *pdev)
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{
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int msi, msix;
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msi = max(pci_msi_vec_count(pdev), 0);
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msix = max(pci_msix_vec_count(pdev), 0);
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return max(msi, msix);
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}
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static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data)
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{
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struct its_pci_alias *dev_alias = data;
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dev_alias->dev_id = alias;
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if (pdev != dev_alias->pdev)
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dev_alias->count += its_pci_msi_vec_count(dev_alias->pdev);
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return 0;
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}
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static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *info)
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{
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struct pci_dev *pdev;
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struct its_node *its;
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u32 dev_id;
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struct its_device *its_dev;
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struct its_pci_alias dev_alias;
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if (!dev_is_pci(dev))
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return -EINVAL;
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pdev = to_pci_dev(dev);
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dev_id = PCI_DEVID(pdev->bus->number, pdev->devfn);
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dev_alias.pdev = pdev;
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dev_alias.count = nvec;
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pci_for_each_dma_alias(pdev, its_get_pci_alias, &dev_alias);
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its = domain->parent->host_data;
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its_dev = its_find_device(its, dev_id);
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if (WARN_ON(its_dev))
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return -EINVAL;
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its_dev = its_find_device(its, dev_alias.dev_id);
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if (its_dev) {
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/*
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* We already have seen this ID, probably through
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* another alias (PCI bridge of some sort). No need to
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* create the device.
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*/
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dev_dbg(dev, "Reusing ITT for devID %x\n", dev_alias.dev_id);
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goto out;
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}
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its_dev = its_create_device(its, dev_id, nvec);
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its_dev = its_create_device(its, dev_alias.dev_id, dev_alias.count);
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if (!its_dev)
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return -ENOMEM;
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dev_dbg(&pdev->dev, "ITT %d entries, %d bits\n", nvec, ilog2(nvec));
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dev_dbg(&pdev->dev, "ITT %d entries, %d bits\n",
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dev_alias.count, ilog2(dev_alias.count));
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out:
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info->scratchpad[0].ptr = its_dev;
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info->scratchpad[1].ptr = dev;
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return 0;
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@ -1255,6 +1320,34 @@ static const struct irq_domain_ops its_domain_ops = {
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.deactivate = its_irq_domain_deactivate,
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};
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static int its_force_quiescent(void __iomem *base)
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{
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u32 count = 1000000; /* 1s */
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u32 val;
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val = readl_relaxed(base + GITS_CTLR);
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if (val & GITS_CTLR_QUIESCENT)
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return 0;
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/* Disable the generation of all interrupts to this ITS */
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val &= ~GITS_CTLR_ENABLE;
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writel_relaxed(val, base + GITS_CTLR);
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/* Poll GITS_CTLR and wait until ITS becomes quiescent */
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while (1) {
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val = readl_relaxed(base + GITS_CTLR);
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if (val & GITS_CTLR_QUIESCENT)
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return 0;
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||||
count--;
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if (!count)
|
||||
return -EBUSY;
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|
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cpu_relax();
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udelay(1);
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}
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}
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static int its_probe(struct device_node *node, struct irq_domain *parent)
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||||
{
|
||||
struct resource res;
|
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@ -1283,6 +1376,13 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
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goto out_unmap;
|
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}
|
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|
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err = its_force_quiescent(its_base);
|
||||
if (err) {
|
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pr_warn("%s: failed to quiesce, giving up\n",
|
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node->full_name);
|
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goto out_unmap;
|
||||
}
|
||||
|
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pr_info("ITS: %s\n", node->full_name);
|
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|
||||
its = kzalloc(sizeof(*its), GFP_KERNEL);
|
||||
@ -1323,7 +1423,7 @@ static int its_probe(struct device_node *node, struct irq_domain *parent)
|
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writeq_relaxed(baser, its->base + GITS_CBASER);
|
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tmp = readq_relaxed(its->base + GITS_CBASER);
|
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writeq_relaxed(0, its->base + GITS_CWRITER);
|
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writel_relaxed(1, its->base + GITS_CTLR);
|
||||
writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
|
||||
|
||||
if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) {
|
||||
pr_info("ITS: using cache flushing for cmd queue\n");
|
||||
@ -1382,12 +1482,11 @@ static bool gic_rdists_supports_plpis(void)
|
||||
|
||||
int its_cpu_init(void)
|
||||
{
|
||||
if (!gic_rdists_supports_plpis()) {
|
||||
pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
if (!list_empty(&its_nodes)) {
|
||||
if (!gic_rdists_supports_plpis()) {
|
||||
pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
|
||||
return -ENXIO;
|
||||
}
|
||||
its_cpu_init_lpis();
|
||||
its_cpu_init_collection();
|
||||
}
|
||||
|
||||
@ -466,7 +466,7 @@ static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask,
|
||||
tlist |= 1 << (mpidr & 0xf);
|
||||
|
||||
cpu = cpumask_next(cpu, mask);
|
||||
if (cpu == nr_cpu_ids)
|
||||
if (cpu >= nr_cpu_ids)
|
||||
goto out;
|
||||
|
||||
mpidr = cpu_logical_map(cpu);
|
||||
|
||||
@ -154,23 +154,25 @@ static inline unsigned int gic_irq(struct irq_data *d)
|
||||
static void gic_mask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
raw_spin_lock_irqsave(&irq_controller_lock, flags);
|
||||
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
|
||||
if (gic_arch_extn.irq_mask)
|
||||
gic_arch_extn.irq_mask(d);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
|
||||
}
|
||||
|
||||
static void gic_unmask_irq(struct irq_data *d)
|
||||
{
|
||||
u32 mask = 1 << (gic_irq(d) % 32);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
raw_spin_lock_irqsave(&irq_controller_lock, flags);
|
||||
if (gic_arch_extn.irq_unmask)
|
||||
gic_arch_extn.irq_unmask(d);
|
||||
writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
|
||||
}
|
||||
|
||||
static void gic_eoi_irq(struct irq_data *d)
|
||||
@ -188,6 +190,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
void __iomem *base = gic_dist_base(d);
|
||||
unsigned int gicirq = gic_irq(d);
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* Interrupt configuration for SGIs can't be changed */
|
||||
@ -199,14 +202,14 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
|
||||
type != IRQ_TYPE_EDGE_RISING)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
raw_spin_lock_irqsave(&irq_controller_lock, flags);
|
||||
|
||||
if (gic_arch_extn.irq_set_type)
|
||||
gic_arch_extn.irq_set_type(d, type);
|
||||
|
||||
ret = gic_configure_irq(gicirq, type, base, NULL);
|
||||
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -227,6 +230,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
|
||||
unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
|
||||
u32 val, mask, bit;
|
||||
unsigned long flags;
|
||||
|
||||
if (!force)
|
||||
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
||||
@ -236,12 +240,12 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
|
||||
if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock(&irq_controller_lock);
|
||||
raw_spin_lock_irqsave(&irq_controller_lock, flags);
|
||||
mask = 0xff << shift;
|
||||
bit = gic_cpu_map[cpu] << shift;
|
||||
val = readl_relaxed(reg) & ~mask;
|
||||
writel_relaxed(val | bit, reg);
|
||||
raw_spin_unlock(&irq_controller_lock);
|
||||
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
|
||||
@ -166,6 +166,11 @@
|
||||
|
||||
#define GITS_TRANSLATER 0x10040
|
||||
|
||||
#define GITS_CTLR_ENABLE (1U << 0)
|
||||
#define GITS_CTLR_QUIESCENT (1U << 31)
|
||||
|
||||
#define GITS_TYPER_DEVBITS_SHIFT 13
|
||||
#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
|
||||
#define GITS_TYPER_PTA (1UL << 19)
|
||||
|
||||
#define GITS_CBASER_VALID (1UL << 63)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user