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x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()

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Rename checking_wrmsrl() to wrmsrl_safe(), to match the naming
convention used by all the other MSR access functions/macros.

Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
H. Peter Anvin 2012-06-07 13:32:04 -07:00
parent 2c929ce6f1
commit 715c85b1fc
8 changed files with 21 additions and 21 deletions
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2
arch/x86/include/asm/msr.h
View File

@ -211,7 +211,7 @@ do { \
#endif /* !CONFIG_PARAVIRT */ #endif /* !CONFIG_PARAVIRT */
#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \
(u32)((val) >> 32)) (u32)((val) >> 32))
#define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))

4
arch/x86/kernel/cpu/amd.c
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@ -621,7 +621,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (!rdmsrl_safe(0xc0011005, &val)) { if (!rdmsrl_safe(0xc0011005, &val)) {
val |= 1ULL << 54; val |= 1ULL << 54;
checking_wrmsrl(0xc0011005, val); wrmsrl_safe(0xc0011005, val);
rdmsrl(0xc0011005, val); rdmsrl(0xc0011005, val);
if (val & (1ULL << 54)) { if (val & (1ULL << 54)) {
set_cpu_cap(c, X86_FEATURE_TOPOEXT); set_cpu_cap(c, X86_FEATURE_TOPOEXT);
@ -712,7 +712,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
if (err == 0) { if (err == 0) {
mask |= (1 << 10); mask |= (1 << 10);
checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
} }
} }

2
arch/x86/kernel/cpu/perf_event.c
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@ -222,7 +222,7 @@ static bool check_hw_exists(void)
* that don't trap on the MSR access and always return 0s. * that don't trap on the MSR access and always return 0s.
*/ */
val = 0xabcdUL; val = 0xabcdUL;
ret = checking_wrmsrl(x86_pmu_event_addr(0), val); ret = wrmsrl_safe(x86_pmu_event_addr(0), val);
ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
if (ret || val != val_new) if (ret || val != val_new)
goto msr_fail; goto msr_fail;

6
arch/x86/kernel/cpu/perf_event_intel.c
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@ -1003,11 +1003,11 @@ static void intel_pmu_reset(void)
printk("clearing PMU state on CPU#%d\n", smp_processor_id()); printk("clearing PMU state on CPU#%d\n", smp_processor_id());
for (idx = 0; idx < x86_pmu.num_counters; idx++) { for (idx = 0; idx < x86_pmu.num_counters; idx++) {
checking_wrmsrl(x86_pmu_config_addr(idx), 0ull); wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
checking_wrmsrl(x86_pmu_event_addr(idx), 0ull); wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
} }
for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
if (ds) if (ds)
ds->bts_index = ds->bts_buffer_base; ds->bts_index = ds->bts_buffer_base;

14
arch/x86/kernel/cpu/perf_event_p4.c
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@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void)
* So at moment let leave metrics turned on forever -- it's * So at moment let leave metrics turned on forever -- it's
* ok for now but need to be revisited! * ok for now but need to be revisited!
* *
* (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0); * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);
* (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0); * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
*/ */
} }
@ -909,7 +909,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
* state we need to clear P4_CCCR_OVF, otherwise interrupt get * state we need to clear P4_CCCR_OVF, otherwise interrupt get
* asserted again and again * asserted again and again
*/ */
(void)checking_wrmsrl(hwc->config_base, (void)wrmsrl_safe(hwc->config_base,
(u64)(p4_config_unpack_cccr(hwc->config)) & (u64)(p4_config_unpack_cccr(hwc->config)) &
~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
} }
@ -943,8 +943,8 @@ static void p4_pmu_enable_pebs(u64 config)
bind = &p4_pebs_bind_map[idx]; bind = &p4_pebs_bind_map[idx];
(void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);
(void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert);
} }
static void p4_pmu_enable_event(struct perf_event *event) static void p4_pmu_enable_event(struct perf_event *event)
@ -978,8 +978,8 @@ static void p4_pmu_enable_event(struct perf_event *event)
*/ */
p4_pmu_enable_pebs(hwc->config); p4_pmu_enable_pebs(hwc->config);
(void)checking_wrmsrl(escr_addr, escr_conf); (void)wrmsrl_safe(escr_addr, escr_conf);
(void)checking_wrmsrl(hwc->config_base, (void)wrmsrl_safe(hwc->config_base,
(cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE); (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
} }

4
arch/x86/kernel/cpu/perf_event_p6.c
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@ -71,7 +71,7 @@ p6_pmu_disable_event(struct perf_event *event)
if (cpuc->enabled) if (cpuc->enabled)
val |= ARCH_PERFMON_EVENTSEL_ENABLE; val |= ARCH_PERFMON_EVENTSEL_ENABLE;
(void)checking_wrmsrl(hwc->config_base, val); (void)wrmsrl_safe(hwc->config_base, val);
} }
static void p6_pmu_enable_event(struct perf_event *event) static void p6_pmu_enable_event(struct perf_event *event)
@ -84,7 +84,7 @@ static void p6_pmu_enable_event(struct perf_event *event)
if (cpuc->enabled) if (cpuc->enabled)
val |= ARCH_PERFMON_EVENTSEL_ENABLE; val |= ARCH_PERFMON_EVENTSEL_ENABLE;
(void)checking_wrmsrl(hwc->config_base, val); (void)wrmsrl_safe(hwc->config_base, val);
} }
PMU_FORMAT_ATTR(event, "config:0-7" ); PMU_FORMAT_ATTR(event, "config:0-7" );

4
arch/x86/kernel/process_64.c
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@ -466,7 +466,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
task->thread.gs = addr; task->thread.gs = addr;
if (doit) { if (doit) {
load_gs_index(0); load_gs_index(0);
ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr); ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
} }
} }
put_cpu(); put_cpu();
@ -494,7 +494,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
/* set the selector to 0 to not confuse /* set the selector to 0 to not confuse
__switch_to */ __switch_to */
loadsegment(fs, 0); loadsegment(fs, 0);
ret = checking_wrmsrl(MSR_FS_BASE, addr); ret = wrmsrl_safe(MSR_FS_BASE, addr);
} }
} }
put_cpu(); put_cpu();

6
arch/x86/vdso/vdso32-setup.c
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@ -205,9 +205,9 @@ void syscall32_cpu_init(void)
{ {
/* Load these always in case some future AMD CPU supports /* Load these always in case some future AMD CPU supports
SYSENTER from compat mode too. */ SYSENTER from compat mode too. */
checking_wrmsrl(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
checking_wrmsrl(MSR_IA32_SYSENTER_ESP, 0ULL); wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
checking_wrmsrl(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
wrmsrl(MSR_CSTAR, ia32_cstar_target); wrmsrl(MSR_CSTAR, ia32_cstar_target);
} }