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ixgbe: consolidate reporting of MSIX vectors into a single function

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This patch modifies ixgbe_get_pcie_msix_count_generic() to support
all current HW and removes the 82598 specific function.

- change the type of ixgbe_get_pcie_msix_count_generic() to u16
- include a check to make sure the maximum allowed number of vectors
is not exceeded.

Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Emil Tantilov 2012-03-22 03:00:29 +00:00 committed by Jeff Kirsher
parent fad59b0d3f
commit 7116130251
4 changed files with 29 additions and 31 deletions
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25
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
View File

@ -91,29 +91,6 @@ out:
IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr); IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
} }
/**
* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
* @hw: pointer to hardware structure
*
* Read PCIe configuration space, and get the MSI-X vector count from
* the capabilities table.
**/
static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
{
struct ixgbe_adapter *adapter = hw->back;
u16 msix_count;
pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
&msix_count);
msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
/* MSI-X count is zero-based in HW, so increment to give proper value */
msix_count++;
return msix_count;
}
/**
*/
static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw) static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
{ {
struct ixgbe_mac_info *mac = &hw->mac; struct ixgbe_mac_info *mac = &hw->mac;
@ -126,7 +103,7 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw); mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
return 0; return 0;
} }

29
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
View File

@ -2783,17 +2783,36 @@ san_mac_addr_out:
* Read PCIe configuration space, and get the MSI-X vector count from * Read PCIe configuration space, and get the MSI-X vector count from
* the capabilities table. * the capabilities table.
**/ **/
u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
{ {
struct ixgbe_adapter *adapter = hw->back; struct ixgbe_adapter *adapter = hw->back;
u16 msix_count; u16 msix_count = 1;
pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS, u16 max_msix_count;
&msix_count); u16 pcie_offset;
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
break;
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
break;
default:
return msix_count;
}
pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
/* MSI-X count is zero-based in HW, so increment to give proper value */ /* MSI-X count is zero-based in HW */
msix_count++; msix_count++;
if (msix_count > max_msix_count)
msix_count = max_msix_count;
return msix_count; return msix_count;
} }

2
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
View File

@ -31,7 +31,7 @@
#include "ixgbe_type.h" #include "ixgbe_type.h"
#include "ixgbe.h" #include "ixgbe.h"
u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw); u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw); s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw); s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw); s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);

4
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View File

@ -1681,7 +1681,9 @@ enum {
#define IXGBE_DEVICE_CAPS 0x2C #define IXGBE_DEVICE_CAPS 0x2C
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
/* MSI-X capability fields masks */ /* MSI-X capability fields masks */
#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
@ -2813,6 +2815,7 @@ struct ixgbe_mac_info {
u16 wwnn_prefix; u16 wwnn_prefix;
/* prefix for World Wide Port Name (WWPN) */ /* prefix for World Wide Port Name (WWPN) */
u16 wwpn_prefix; u16 wwpn_prefix;
u16 max_msix_vectors;
#define IXGBE_MAX_MTA 128 #define IXGBE_MAX_MTA 128
u32 mta_shadow[IXGBE_MAX_MTA]; u32 mta_shadow[IXGBE_MAX_MTA];
s32 mc_filter_type; s32 mc_filter_type;
@ -2823,7 +2826,6 @@ struct ixgbe_mac_info {
u32 rx_pb_size; u32 rx_pb_size;
u32 max_tx_queues; u32 max_tx_queues;
u32 max_rx_queues; u32 max_rx_queues;
u32 max_msix_vectors;
u32 orig_autoc; u32 orig_autoc;
u32 orig_autoc2; u32 orig_autoc2;
bool orig_link_settings_stored; bool orig_link_settings_stored;