forked from Minki/linux
ixgbe: consolidate reporting of MSIX vectors into a single function
This patch modifies ixgbe_get_pcie_msix_count_generic() to support all current HW and removes the 82598 specific function. - change the type of ixgbe_get_pcie_msix_count_generic() to u16 - include a check to make sure the maximum allowed number of vectors is not exceeded. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -91,29 +91,6 @@ out:
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IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
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}
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/**
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* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
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* @hw: pointer to hardware structure
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*
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* Read PCIe configuration space, and get the MSI-X vector count from
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* the capabilities table.
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**/
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static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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u16 msix_count;
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pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
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&msix_count);
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msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
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/* MSI-X count is zero-based in HW, so increment to give proper value */
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msix_count++;
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return msix_count;
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}
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/**
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*/
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static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
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{
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struct ixgbe_mac_info *mac = &hw->mac;
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@ -126,7 +103,7 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
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mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
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mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
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mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
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mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
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mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
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return 0;
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}
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@ -2783,17 +2783,36 @@ san_mac_addr_out:
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* Read PCIe configuration space, and get the MSI-X vector count from
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* the capabilities table.
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**/
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u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
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u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
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{
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struct ixgbe_adapter *adapter = hw->back;
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u16 msix_count;
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pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
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&msix_count);
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u16 msix_count = 1;
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u16 max_msix_count;
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u16 pcie_offset;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
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max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
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max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
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break;
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default:
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return msix_count;
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}
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pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
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msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
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/* MSI-X count is zero-based in HW, so increment to give proper value */
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/* MSI-X count is zero-based in HW */
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msix_count++;
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if (msix_count > max_msix_count)
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msix_count = max_msix_count;
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return msix_count;
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}
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@ -31,7 +31,7 @@
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#include "ixgbe_type.h"
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#include "ixgbe.h"
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u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
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u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
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s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
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s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
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s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
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@ -1681,7 +1681,9 @@ enum {
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#define IXGBE_DEVICE_CAPS 0x2C
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#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
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#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
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#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
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#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
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#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
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/* MSI-X capability fields masks */
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#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
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@ -2813,6 +2815,7 @@ struct ixgbe_mac_info {
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u16 wwnn_prefix;
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/* prefix for World Wide Port Name (WWPN) */
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u16 wwpn_prefix;
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u16 max_msix_vectors;
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#define IXGBE_MAX_MTA 128
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u32 mta_shadow[IXGBE_MAX_MTA];
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s32 mc_filter_type;
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@ -2823,7 +2826,6 @@ struct ixgbe_mac_info {
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u32 rx_pb_size;
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u32 max_tx_queues;
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u32 max_rx_queues;
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u32 max_msix_vectors;
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u32 orig_autoc;
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u32 orig_autoc2;
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bool orig_link_settings_stored;
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