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Renesas ARM based SoC cleanups for v3.11

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__initdata annotations for the r8a7790 SoC by Morimoto-san.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIcBAABAgAGBQJRvrESAAoJENfPZGlqN0++Kl4P/j1twlyTQ7WA99/qba3Ql36u
 hGUbqmpoq5MtqdIrkJh4L48Y5M2+MJmmQaH9CkxyxlsmIFDvAb5Ta55iQ6BJgap3
 I6yLxRbhQ2ZhydaY/VrtSQLtPg1wAmAYdfTP/1FT+XuR5JddBk95j9I91LnzkTuP
 pUr6k3Ahz9Uz6//cYIdyBvM5y1CWSMtwhSTjL7Fb8UXWls/PzRrvmP1lWH5h0v8L
 PZAmVWIE5AaeChd8Z88rtlcf61TouxDnghe72yFlE4A9RD3JFjoduBo7/izn3EAA
 BYEAyqJYvrW9mxrMuyJlpE8+Gy2CGB0asKYu63n9FYC6T+RKVhNtGNHJ35ys3xMa
 hmAOkpa2oFTJI57APtmR+/SzCGTXElqRNw5LJP95GZkpa5PsugtRXVpczgdTOvnv
 4VswyH6EzdzcW5KQYE3v/Zp3/58ZzbLzj+nRkjLG1shi739+CQuJngQin+GGdBWL
 hUEIgoNuZl1GN/OjMQzpt5b+rWfIyy8jnRTcluvaNIulaFhqc/sYvolurqQGWa0n
 U/mSIZT/PxQftguAgUfzhV1vgvJ80Kkb37c9UKwglJjX7E0oNCkZZ8JD9sce7EXn
 IvOZL8k8IPDrl8URtNV3IialW3FpGCwM7S/DZ8qM4JHgBYEbJGZ2QGboUMgvnOBo
 cEveedi1Qur0x4ZKYrS7
 =i7Kv
 -----END PGP SIGNATURE-----

Merge tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

From Simon Horman:

Renesas ARM based SoC cleanups for v3.11

__initdata annotations for the r8a7790 SoC by Morimoto-san.

* tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (158 commits)
  ARM: shmobile: r8a7790: add __initdata on resource and device data

Based on 'renesas-pinmux-for-v3.11' and 'renesas-soc-for-v3.11

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-21 14:54:09 +02:00
commit 704b1005d1
40 changed files with 11232 additions and 2863 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/Kconfig
View File

@ -645,7 +645,7 @@ config ARCH_SHMOBILE
select MULTI_IRQ_HANDLER
select NEED_MACH_MEMORY_H
select NO_IOPORT
select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
select PINCTRL
select PM_GENERIC_DOMAINS if PM
select SPARSE_IRQ
help

5
arch/arm/mach-shmobile/Kconfig
View File

@ -36,7 +36,8 @@ config ARCH_R8A7740
select RENESAS_INTC_IRQPIN
config ARCH_R8A7778
bool "R-Car M1 (R8A77780)"
bool "R-Car M1A (R8A77781)"
select ARCH_WANT_OPTIONAL_GPIOLIB
select CPU_V7
select SH_CLK_CPG
select ARM_GIC
@ -169,6 +170,8 @@ config MACH_KZM9D
config MACH_KZM9G
bool "KZM-A9-GT board"
depends on ARCH_SH73A0
select ARCH_HAS_CPUFREQ
select ARCH_HAS_OPP
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SND_SOC_AK4642 if SND_SIMPLE_CARD

132
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -1026,10 +1026,8 @@ out:
/* TouchScreen */
#ifdef CONFIG_AP4EVB_QHD
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
# define GPIO_TSC_PORT 123
#else /* WVGA */
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
# define GPIO_TSC_PORT 40
#endif
@ -1037,22 +1035,12 @@ out:
#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
static int ts_get_pendown_state(void)
{
int val;
gpio_free(GPIO_TSC_IRQ);
gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
val = gpio_get_value(GPIO_TSC_PORT);
gpio_request(GPIO_TSC_IRQ, NULL);
return !val;
return !gpio_get_value(GPIO_TSC_PORT);
}
static int ts_init(void)
{
gpio_request(GPIO_TSC_IRQ, NULL);
gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
return 0;
}
@ -1086,11 +1074,42 @@ static struct i2c_board_info i2c1_devices[] = {
static const struct pinctrl_map ap4evb_pinctrl_map[] = {
/* CEU */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
"ceu_clk_0", "ceu"),
/* FSIA (AK4643) */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_data_out", "fsia"),
/* FSIB (HDMI) */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
"fsib_mclk_in", "fsib"),
/* HDMI */
PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
"hdmi", "hdmi"),
/* KEYSC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
"keysc_in04_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
"keysc_out5", "keysc"),
#ifndef CONFIG_AP4EVB_QHD
/* LCDC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
"lcd_data18", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
"lcd_sync", "lcd"),
#endif
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_ctrl_0", "mmc0"),
/* SCIFA0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
"scifa0_data", "scifa0"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_data4", "sdhi0"),
@ -1105,6 +1124,26 @@ static const struct pinctrl_map ap4evb_pinctrl_map[] = {
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_ctrl", "sdhi1"),
/* SMSC911X */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
"bsc_cs5a", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
"intc_irq6_0", "intc"),
/* TSC2007 */
#ifdef CONFIG_AP4EVB_QHD
PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
"intc_irq28_0", "intc"),
#else /* WVGA */
PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
"intc_irq7_0", "intc"),
#endif
/* USBHS1 */
PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
"usb1_vbus", "usb1"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
"usb1_otg_id_0", "usb1"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
"usb1_otg_ctrl_0", "usb1"),
};
#define GPIO_PORT9CR IOMEM(0xE6051009)
@ -1137,36 +1176,16 @@ static void __init ap4evb_init(void)
ARRAY_SIZE(ap4evb_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
/* enable SMSC911X */
gpio_request(GPIO_FN_CS5A, NULL);
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable Debug switch (S6) */
gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* USB enable */
gpio_request(GPIO_FN_VBUS0_1, NULL);
gpio_request(GPIO_FN_IDIN_1_18, NULL);
gpio_request(GPIO_FN_PWEN_1_115, NULL);
gpio_request(GPIO_FN_OVCN_1_114, NULL);
gpio_request(GPIO_FN_EXTLP_1, NULL);
gpio_request(GPIO_FN_OVCN2_1, NULL);
/* setup USB phy */
__raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
/* enable FSI2 port A (ak4643) */
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* FSI2 port A (ak4643) */
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request(9, NULL);
@ -1177,8 +1196,7 @@ static void __init ap4evb_init(void)
/* card detect pin for MMC slot (CN7) */
gpio_request_one(41, GPIOF_IN, NULL);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
/* FSI2 port B (HDMI) */
__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
/* set SPU2 clock to 119.6 MHz */
@ -1208,18 +1226,6 @@ static void __init ap4evb_init(void)
* IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
*/
/* enable KEYSC */
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4, NULL);
gpio_request(GPIO_FN_KEYIN0_136, NULL);
gpio_request(GPIO_FN_KEYIN1_135, NULL);
gpio_request(GPIO_FN_KEYIN2_134, NULL);
gpio_request(GPIO_FN_KEYIN3_133, NULL);
gpio_request(GPIO_FN_KEYIN4, NULL);
/* enable TouchScreen */
irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
@ -1241,28 +1247,6 @@ static void __init ap4evb_init(void)
* For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
* IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
*/
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
@ -1288,8 +1272,6 @@ static void __init ap4evb_init(void)
*/
/* MIPI-CSI stuff */
gpio_request(GPIO_FN_VIO_CKO, NULL);
clk = clk_get(NULL, "vck1_clk");
if (!IS_ERR(clk)) {
clk_set_rate(clk, clk_round_rate(clk, 13000000));
@ -1299,10 +1281,6 @@ static void __init ap4evb_init(void)
sh7372_add_standard_devices();
/* HDMI */
gpio_request(GPIO_FN_HDMI_HPD, NULL);
gpio_request(GPIO_FN_HDMI_CEC, NULL);
/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
#define SRCR4 IOMEM(0xe61580bc)
srcr4 = __raw_readl(SRCR4);

116
arch/arm/mach-shmobile/board-armadillo800eva.c
View File

@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
static struct fixed_voltage_config vcc_sdhi0_info = {
.supply_name = "SDHI0 Vcc",
.microvolts = 3300000,
.gpio = GPIO_PORT75,
.gpio = 75,
.enable_high = 1,
.init_data = &vcc_sdhi0_init_data,
};
@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
};
static struct gpio vccq_sdhi0_gpios[] = {
{GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
{17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
};
static struct gpio_regulator_state vccq_sdhi0_states[] = {
@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
static struct gpio_regulator_config vccq_sdhi0_info = {
.supply_name = "vqmmc",
.enable_gpio = GPIO_PORT74,
.enable_gpio = 74,
.enable_high = 1,
.enabled_at_boot = 0,
@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
static struct fixed_voltage_config vcc_sdhi1_info = {
.supply_name = "SDHI1 Vcc",
.microvolts = 3300000,
.gpio = GPIO_PORT16,
.gpio = 16,
.enable_high = 1,
.init_data = &vcc_sdhi1_init_data,
};
@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.cd_gpio = GPIO_PORT167,
.cd_gpio = 167,
};
static struct resource sdhi0_resources[] = {
@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
MMC_CAP_POWER_OFF_CARD,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
/* Port72 cannot generate IRQs, will be used in polling mode. */
.cd_gpio = GPIO_PORT72,
.cd_gpio = 72,
};
static struct resource sdhi1_resources[] = {
@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = {
};
static const struct pinctrl_map eva_pinctrl_map[] = {
/* CEU0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
"ceu0_data_0_7", "ceu0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
"ceu0_clk_0", "ceu0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
"ceu0_sync", "ceu0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
"ceu0_field", "ceu0"),
/* FSIA */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
"fsia_mclk_out", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
"fsia_data_in_1", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
"fsia_data_out_0", "fsia"),
/* FSIB */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
"fsib_mclk_in", "fsib"),
/* GETHER */
PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
"gether_mii", "gether"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
"gether_int", "gether"),
/* HDMI */
PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
"hdmi", "hdmi"),
/* LCD0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_data24_0", "lcd0"),
@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
"mmc0_data8_1", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
"mmc0_ctrl_1", "mmc0"),
/* SCIFA1 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
"scifa1_data", "scifa1"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
"sdhi0_data4", "sdhi0"),
@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
"sdhi0_wp", "sdhi0"),
/* ST1232 */
PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
"intc_irq10", "intc"),
/* USBHS */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
"intc_irq7_1", "intc"),
};
static void __init eva_clock_init(void)
@ -1119,40 +1157,14 @@ static void __init eva_init(void)
r8a7740_pinmux_init();
r8a7740_meram_workaround();
/* SCIFA1 */
gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
/* LCDC0 */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
/* Touchscreen */
gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
/* GETHER */
gpio_request(GPIO_FN_ET_CRS, NULL);
gpio_request(GPIO_FN_ET_MDC, NULL);
gpio_request(GPIO_FN_ET_MDIO, NULL);
gpio_request(GPIO_FN_ET_TX_ER, NULL);
gpio_request(GPIO_FN_ET_RX_ER, NULL);
gpio_request(GPIO_FN_ET_ERXD0, NULL);
gpio_request(GPIO_FN_ET_ERXD1, NULL);
gpio_request(GPIO_FN_ET_ERXD2, NULL);
gpio_request(GPIO_FN_ET_ERXD3, NULL);
gpio_request(GPIO_FN_ET_TX_CLK, NULL);
gpio_request(GPIO_FN_ET_TX_EN, NULL);
gpio_request(GPIO_FN_ET_ETXD0, NULL);
gpio_request(GPIO_FN_ET_ETXD1, NULL);
gpio_request(GPIO_FN_ET_ETXD2, NULL);
gpio_request(GPIO_FN_ET_ETXD3, NULL);
gpio_request(GPIO_FN_ET_PHY_INT, NULL);
gpio_request(GPIO_FN_ET_COL, NULL);
gpio_request(GPIO_FN_ET_RX_DV, NULL);
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
/* USB */
@ -1163,34 +1175,17 @@ static void __init eva_init(void)
} else {
/* USB Func */
/*
* A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
* OTOH, usbhs interrupt needs its value (HI/LOW) to decide
* USB connection/disconnection (usbhsf_get_vbus()).
* This means we needs to select GPIO_FN_IRQ7_PORT209 first,
* and select GPIO 209 here
* The USBHS interrupt handlers needs to read the IRQ pin value
* (HI/LOW) to diffentiate USB connection and disconnection
* events (usbhsf_get_vbus()). We thus need to select both the
* intc_irq7_1 pin group and GPIO 209 here.
*/
gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
gpio_request_one(209, GPIOF_IN, NULL);
platform_device_register(&usbhsf_device);
usb = &usbhsf_device;
}
/* CEU0 */
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
gpio_request(GPIO_FN_VIO0_D5, NULL);
gpio_request(GPIO_FN_VIO0_D4, NULL);
gpio_request(GPIO_FN_VIO0_D3, NULL);
gpio_request(GPIO_FN_VIO0_D2, NULL);
gpio_request(GPIO_FN_VIO0_D1, NULL);
gpio_request(GPIO_FN_VIO0_D0, NULL);
gpio_request(GPIO_FN_VIO0_CLK, NULL);
gpio_request(GPIO_FN_VIO0_HD, NULL);
gpio_request(GPIO_FN_VIO0_VD, NULL);
gpio_request(GPIO_FN_VIO0_FIELD, NULL);
gpio_request(GPIO_FN_VIO_CKO, NULL);
/* CON1/CON15 Camera */
gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@ -1198,24 +1193,11 @@ static void __init eva_init(void)
gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
/* FSI-WM8978 */
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAOMC, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
gpio_request(7, NULL);
gpio_request(8, NULL);
gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
/* FSI-HDMI */
gpio_request(GPIO_FN_FSIBCK, NULL);
/* HDMI */
gpio_request(GPIO_FN_HDMI_HPD, NULL);
gpio_request(GPIO_FN_HDMI_CEC, NULL);
/*
* CAUTION
*

13
arch/arm/mach-shmobile/board-bockw.c
View File

@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <mach/common.h>
@ -37,6 +38,14 @@ static struct resource smsc911x_resources[] = {
DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
};
static const struct pinctrl_map bockw_pinctrl_map[] = {
/* SCIF0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
"scif0_data_a", "scif0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
"scif0_ctrl", "scif0"),
};
#define IRQ0MR 0x30
static void __init bockw_init(void)
{
@ -46,6 +55,10 @@ static void __init bockw_init(void)
r8a7778_init_irq_extpin(1);
r8a7778_add_standard_devices();
pinctrl_register_mappings(bockw_pinctrl_map,
ARRAY_SIZE(bockw_pinctrl_map));
r8a7778_pinmux_init();
fpga = ioremap_nocache(0x18200000, SZ_1M);
if (fpga) {
/*

47
arch/arm/mach-shmobile/board-bonito.c
View File

@ -330,12 +330,6 @@ static struct platform_device smsc_device = {
.num_resources = ARRAY_SIZE(smsc_resources),
};
/*
* core board devices
*/
static struct platform_device *bonito_core_devices[] __initdata = {
};
/*
* base board devices
*/
@ -375,12 +369,37 @@ static void __init bonito_map_io(void)
#define VCCQ1CR IOMEM(0xE6058140)
#define VCCQ1LCDCR IOMEM(0xE6058186)
/*
* HACK: The FPGA mappings should be associated with the FPGA device, but we
* don't have one at the moment. Associate them with the PFC device to make
* sure they will be applied.
*/
static const struct pinctrl_map fpga_pinctrl_map[] = {
/* FPGA */
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
"bsc_cs5a_0", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
"bsc_cs5b", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
"bsc_cs6a", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
"intc_irq10", "intc"),
};
static const struct pinctrl_map scifa5_pinctrl_map[] = {
/* SCIFA5 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
"scifa5_data_2", "scifa5"),
};
static void __init bonito_init(void)
{
u16 val;
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(fpga_pinctrl_map,
ARRAY_SIZE(fpga_pinctrl_map));
r8a7740_pinmux_init();
bonito_fpga_init();
@ -397,9 +416,6 @@ static void __init bonito_init(void)
r8a7740_add_standard_devices();
platform_add_devices(bonito_core_devices,
ARRAY_SIZE(bonito_core_devices));
/*
* base board settings
*/
@ -409,14 +425,6 @@ static void __init bonito_init(void)
u16 bsw3;
u16 bsw4;
/*
* FPGA
*/
gpio_request(GPIO_FN_CS5B, NULL);
gpio_request(GPIO_FN_CS6A, NULL);
gpio_request(GPIO_FN_CS5A_PORT105, NULL);
gpio_request(GPIO_FN_IRQ10, NULL);
val = bonito_fpga_read(BVERR);
pr_info("bonito version: cpu %02x, base %02x\n",
((val >> 8) & 0xFF),
@ -432,8 +440,8 @@ static void __init bonito_init(void)
if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
BIT_OFF(bsw3, 9) && /* S39.6 = ON */
BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
pinctrl_register_mappings(scifa5_pinctrl_map,
ARRAY_SIZE(scifa5_pinctrl_map));
}
/*
@ -443,7 +451,6 @@ static void __init bonito_init(void)
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
pinctrl_register_mappings(lcdc0_pinctrl_map,
ARRAY_SIZE(lcdc0_pinctrl_map));
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */

1
arch/arm/mach-shmobile/board-kzm9g-reference.c
View File

@ -79,7 +79,6 @@ static void __init kzm_init(void)
sh73a0_pinmux_init();
/* enable SD */
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */

11
arch/arm/mach-shmobile/board-kzm9g.c
View File

@ -663,13 +663,13 @@ static unsigned long pin_pullup_conf[] = {
static const struct pinctrl_map kzm_pinctrl_map[] = {
/* FSIA (AK4648) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@ -788,9 +788,6 @@ static void __init kzm_init(void)
/* Touchscreen */
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
/* enable SD */
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);

15
arch/arm/mach-shmobile/board-lager.c
View File

@ -21,15 +21,30 @@
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/kernel.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <mach/common.h>
#include <mach/r8a7790.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static const struct pinctrl_map lager_pinctrl_map[] = {
/* SCIF0 (CN19: DEBUG SERIAL0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
"scif0_data", "scif0"),
/* SCIF1 (CN20: DEBUG SERIAL1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
"scif1_data", "scif1"),
};
static void __init lager_add_standard_devices(void)
{
r8a7790_clock_init();
pinctrl_register_mappings(lager_pinctrl_map,
ARRAY_SIZE(lager_pinctrl_map));
r8a7790_pinmux_init();
r8a7790_add_standard_devices();
}

171
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
};
static const struct pinctrl_map mackerel_pinctrl_map[] = {
/* ADXL34X */
PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
"intc_irq21", "intc"),
/* CEU */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
"ceu_data_0_7", "ceu"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
"ceu_clk_0", "ceu"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
"ceu_sync", "ceu"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
"ceu_field", "ceu"),
/* FLCTL */
PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
"flctl_data", "flctl"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
"flctl_ce0", "flctl"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
"flctl_ctrl", "flctl"),
/* FSIA (AK4643) */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
"fsia_data_out", "fsia"),
/* FSIB (HDMI) */
PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
"fsib_mclk_in", "fsib"),
/* HDMI */
PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
"hdmi", "hdmi"),
/* LCDC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
"lcd_sync", "lcd"),
/* SCIFA0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
"scifa0_data", "scifa0"),
/* SCIFA2 (GT-720F GPS module) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
"scifa2_data", "scifa2"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_data4", "sdhi0"),
@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_wp", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"intc_irq26_1", "intc"),
/* SDHI1 */
#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
"sdhi2_ctrl", "sdhi2"),
/* SMSC911X */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
"bsc_cs5a", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
"intc_irq6_0", "intc"),
/* ST1232 */
PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
"intc_irq7_0", "intc"),
/* TCA6416 */
PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
"intc_irq9_0", "intc"),
/* USBHS0 */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
"usb0_vbus", "usb0"),
/* USBHS1 */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
"usb1_vbus", "usb1"),
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
"usb1_otg_id_0", "usb1"),
};
#define GPIO_PORT9CR IOMEM(0xE6051009)
@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
ARRAY_SIZE(mackerel_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
/* enable SMSC911X */
gpio_request(GPIO_FN_CS5A, NULL);
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
/* backlight, off by default */
gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
/* USBHS0 */
gpio_request(GPIO_FN_VBUS0_0, NULL);
gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
/* USBHS1 */
gpio_request(GPIO_FN_VBUS0_1, NULL);
gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
gpio_request(GPIO_FN_IDIN_1_113, NULL);
/* enable FSI2 port A (ak4643) */
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* FSI2 port A (ak4643) */
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request(9, NULL);
@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
/* FSI2 port B (HDMI) */
__raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
/* set SPU2 clock to 119.6 MHz */
@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
clk_put(clk);
}
/* enable Keypad */
gpio_request(GPIO_FN_IRQ9_42, NULL);
/* Keypad */
irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
/* enable Touchscreen */
gpio_request(GPIO_FN_IRQ7_40, NULL);
/* Touchscreen */
irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
/* enable Accelerometer */
gpio_request(GPIO_FN_IRQ21, NULL);
/* Accelerometer */
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
/* SDHI0 PORT172 card-detect IRQ26 */
gpio_request(GPIO_FN_IRQ26_172, NULL);
/* FLCTL */
gpio_request(GPIO_FN_D0_NAF0, NULL);
gpio_request(GPIO_FN_D1_NAF1, NULL);
gpio_request(GPIO_FN_D2_NAF2, NULL);
gpio_request(GPIO_FN_D3_NAF3, NULL);
gpio_request(GPIO_FN_D4_NAF4, NULL);
gpio_request(GPIO_FN_D5_NAF5, NULL);
gpio_request(GPIO_FN_D6_NAF6, NULL);
gpio_request(GPIO_FN_D7_NAF7, NULL);
gpio_request(GPIO_FN_D8_NAF8, NULL);
gpio_request(GPIO_FN_D9_NAF9, NULL);
gpio_request(GPIO_FN_D10_NAF10, NULL);
gpio_request(GPIO_FN_D11_NAF11, NULL);
gpio_request(GPIO_FN_D12_NAF12, NULL);
gpio_request(GPIO_FN_D13_NAF13, NULL);
gpio_request(GPIO_FN_D14_NAF14, NULL);
gpio_request(GPIO_FN_D15_NAF15, NULL);
gpio_request(GPIO_FN_FCE0, NULL);
gpio_request(GPIO_FN_WE0_FWE, NULL);
gpio_request(GPIO_FN_FRB, NULL);
gpio_request(GPIO_FN_A4_FOE, NULL);
gpio_request(GPIO_FN_A5_FCDE, NULL);
gpio_request(GPIO_FN_RD_FSC, NULL);
/* enable GPS module (GT-720F) */
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
/* CEU */
gpio_request(GPIO_FN_VIO_CLK, NULL);
gpio_request(GPIO_FN_VIO_VD, NULL);
gpio_request(GPIO_FN_VIO_HD, NULL);
gpio_request(GPIO_FN_VIO_FIELD, NULL);
gpio_request(GPIO_FN_VIO_CKO, NULL);
gpio_request(GPIO_FN_VIO_D7, NULL);
gpio_request(GPIO_FN_VIO_D6, NULL);
gpio_request(GPIO_FN_VIO_D5, NULL);
gpio_request(GPIO_FN_VIO_D4, NULL);
gpio_request(GPIO_FN_VIO_D3, NULL);
gpio_request(GPIO_FN_VIO_D2, NULL);
gpio_request(GPIO_FN_VIO_D1, NULL);
gpio_request(GPIO_FN_VIO_D0, NULL);
/* HDMI */
gpio_request(GPIO_FN_HDMI_HPD, NULL);
gpio_request(GPIO_FN_HDMI_CEC, NULL);
/* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
srcr4 = __raw_readl(SRCR4);
__raw_writel(srcr4 | (1 << 13), SRCR4);

7
arch/arm/mach-shmobile/board-marzen.c
View File

@ -28,6 +28,7 @@
#include <linux/leds.h>
#include <linux/dma-mapping.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@ -173,15 +174,15 @@ static struct platform_device usb_phy_device = {
static struct gpio_led marzen_leds[] = {
{
.name = "led2",
.gpio = 157,
.gpio = RCAR_GP_PIN(4, 29),
.default_state = LEDS_GPIO_DEFSTATE_ON,
}, {
.name = "led3",
.gpio = 158,
.gpio = RCAR_GP_PIN(4, 30),
.default_state = LEDS_GPIO_DEFSTATE_ON,
}, {
.name = "led4",
.gpio = 159,
.gpio = RCAR_GP_PIN(4, 31),
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
};

375
arch/arm/mach-shmobile/clock-r8a73a4.c
View File

@ -22,15 +22,43 @@
#include <linux/kernel.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/common.h>
#define CPG_BASE 0xe6150000
#define CPG_LEN 0x270
#define MPCKCR 0xe6150080
#define SMSTPCR2 0xe6150138
#define SMSTPCR5 0xe6150144
#define FRQCRA 0xE6150000
#define FRQCRB 0xE6150004
#define VCLKCR1 0xE6150008
#define VCLKCR2 0xE615000C
#define VCLKCR3 0xE615001C
#define VCLKCR4 0xE6150014
#define VCLKCR5 0xE6150034
#define ZBCKCR 0xE6150010
#define SD0CKCR 0xE6150074
#define SD1CKCR 0xE6150078
#define SD2CKCR 0xE615007C
#define MMC0CKCR 0xE6150240
#define MMC1CKCR 0xE6150244
#define FSIACKCR 0xE6150018
#define FSIBCKCR 0xE6150090
#define MPCKCR 0xe6150080
#define SPUVCKCR 0xE6150094
#define HSICKCR 0xE615026C
#define M4CKCR 0xE6150098
#define PLLECR 0xE61500D0
#define PLL1CR 0xE6150028
#define PLL2CR 0xE615002C
#define PLL2SCR 0xE61501F4
#define PLL2HCR 0xE61501E4
#define CKSCR 0xE61500C0
#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
static struct clk_mapping cpg_mapping = {
.phys = CPG_BASE,
.len = CPG_LEN,
@ -51,12 +79,273 @@ static struct clk extal2_clk = {
.mapping = &cpg_mapping,
};
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
static struct clk main_clk = {
/* .parent will be set r8a73a4_clock_init */
.ops = &followparent_clk_ops,
};
SH_CLK_RATIO(div2, 1, 2);
SH_CLK_RATIO(div4, 1, 4);
SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
/* External FSIACK/FSIBCK clock */
static struct clk fsiack_clk = {
};
static struct clk fsibck_clk = {
};
/*
* PLL clocks
*/
static struct clk *pll_parent_main[] = {
[0] = &main_clk,
[1] = &main_div2_clk
};
static struct clk *pll_parent_main_extal[8] = {
[0] = &main_div2_clk,
[1] = &extal2_div2_clk,
[3] = &extal2_div4_clk,
[4] = &main_clk,
[5] = &extal2_clk,
};
static unsigned long pll_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
return clk->parent->rate * mult;
}
static int pll_set_parent(struct clk *clk, struct clk *parent)
{
u32 val;
int i, ret;
if (!clk->parent_table || !clk->parent_num)
return -EINVAL;
/* Search the parent */
for (i = 0; i < clk->parent_num; i++)
if (clk->parent_table[i] == parent)
break;
if (i == clk->parent_num)
return -ENODEV;
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
val = ioread32(clk->mapped_reg) &
~(((1 << clk->src_width) - 1) << clk->src_shift);
iowrite32(val | i << clk->src_shift, clk->mapped_reg);
return 0;
}
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
.set_parent = pll_set_parent,
};
#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
static struct clk name = { \
.ops = &pll_clk_ops, \
.flags = CLK_ENABLE_ON_INIT, \
.parent = p, \
.parent_table = pt, \
.parent_num = ARRAY_SIZE(pt), \
.src_width = w, \
.src_shift = s, \
.enable_reg = (void __iomem *)reg, \
.enable_bit = e, \
.mapping = &cpg_mapping, \
}
PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
static struct clk *main_clks[] = {
&extalr_clk,
&extal1_clk,
&extal1_div2_clk,
&extal2_clk,
&extal2_div2_clk,
&extal2_div4_clk,
&main_clk,
&main_div2_clk,
&fsiack_clk,
&fsibck_clk,
&pll1_clk,
&pll1_div2_clk,
&pll2_clk,
&pll2s_clk,
&pll2h_clk,
};
/* DIV4 */
static void div4_kick(struct clk *clk)
{
unsigned long value;
/* set KICK bit in FRQCRB to update hardware setting */
value = ioread32(CPG_MAP(FRQCRB));
value |= (1 << 31);
iowrite32(value, CPG_MAP(FRQCRB));
}
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
.kick = div4_kick,
};
enum {
DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
DIV4_ZX, DIV4_ZS, DIV4_HP,
DIV4_NR };
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
[DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
[DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
[DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
[DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
[DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
};
enum {
DIV6_ZB,
DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
DIV6_MMC0, DIV6_MMC1,
DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
DIV6_FSIA, DIV6_FSIB,
DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
DIV6_NR };
static struct clk *div6_parents[8] = {
[0] = &pll1_div2_clk,
[1] = &pll2s_clk,
[3] = &extal2_clk,
[4] = &main_div2_clk,
[6] = &extalr_clk,
};
static struct clk *fsia_parents[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2s_clk,
[2] = &fsiack_clk,
};
static struct clk *fsib_parents[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2s_clk,
[2] = &fsibck_clk,
};
static struct clk *mp_parents[4] = {
[0] = &pll1_div2_clk,
[1] = &pll2s_clk,
[2] = &extal2_clk,
[3] = &extal2_clk,
};
static struct clk *m4_parents[2] = {
[0] = &pll2s_clk,
};
static struct clk *hsi_parents[4] = {
[0] = &pll2h_clk,
[1] = &pll1_div2_clk,
[3] = &pll2s_clk,
};
/*** FIXME ***
* SH_CLK_DIV6_EXT() macro doesn't care .mapping
* but, it is necessary on R-Car (= ioremap() base CPG)
* The difference between
* SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
* is only .mapping
*/
#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents, \
_num_parents, _src_shift, _src_width) \
{ \
.enable_reg = (void __iomem *)_reg, \
.enable_bit = 0, /* unused */ \
.flags = _flags | CLK_MASK_DIV_ON_DISABLE, \
.div_mask = SH_CLK_DIV6_MSK, \
.parent_table = _parents, \
.parent_num = _num_parents, \
.src_shift = _src_shift, \
.src_width = _src_width, \
.mapping = &cpg_mapping, \
}
static struct clk div6_clks[DIV6_NR] = {
[DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
div6_parents, 2, 7, 1),
[DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
div6_parents, 2, 6, 2),
[DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
div6_parents, 2, 6, 2),
[DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
div6_parents, 2, 6, 2),
[DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
div6_parents, 2, 6, 2),
[DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
div6_parents, 2, 6, 2),
[DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
[DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
[DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
[DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
[DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
[DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
[DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
[DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
/* pll2s will be selected always for M4 */
[DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
[DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
[DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
};
/* MSTP */
enum {
MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
MSTP522,
@ -64,16 +353,52 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
[MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
[MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
[MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
[MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 4, 0), /* SCIFA0 */
[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 3, 0), /* SCIFA1 */
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 6, 0), /* SCIFB0 */
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
};
static struct clk_lookup lookups[] = {
/* main clock */
CLKDEV_CON_ID("extal1", &extal1_clk),
CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
CLKDEV_CON_ID("extal2", &extal2_clk),
CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
CLKDEV_CON_ID("fsiack", &fsiack_clk),
CLKDEV_CON_ID("fsibck", &fsibck_clk),
/* pll clock */
CLKDEV_CON_ID("pll1", &pll1_clk),
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
CLKDEV_CON_ID("pll2", &pll2_clk),
CLKDEV_CON_ID("pll2s", &pll2s_clk),
CLKDEV_CON_ID("pll2h", &pll2h_clk),
/* DIV6 */
CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
CLKDEV_CON_ID("sdhi0", &div6_clks[DIV6_SDHI0]),
CLKDEV_CON_ID("sdhi1", &div6_clks[DIV6_SDHI1]),
CLKDEV_CON_ID("sdhi2", &div6_clks[DIV6_SDHI2]),
CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]),
CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]),
CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3", &div6_clks[DIV6_VCK3]),
CLKDEV_CON_ID("vck4", &div6_clks[DIV6_VCK4]),
CLKDEV_CON_ID("vck5", &div6_clks[DIV6_VCK5]),
CLKDEV_CON_ID("fsia", &div6_clks[DIV6_FSIA]),
CLKDEV_CON_ID("fsib", &div6_clks[DIV6_FSIB]),
CLKDEV_CON_ID("mp", &div6_clks[DIV6_MP]),
CLKDEV_CON_ID("m4", &div6_clks[DIV6_M4]),
CLKDEV_CON_ID("hsi", &div6_clks[DIV6_HSI]),
CLKDEV_CON_ID("spuv", &div6_clks[DIV6_SPUV]),
/* MSTP */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@ -88,21 +413,39 @@ static struct clk_lookup lookups[] = {
void __init r8a73a4_clock_init(void)
{
void __iomem *cpg_base, *reg;
void __iomem *reg;
int k, ret = 0;
u32 ckscr;
/* fix MPCLK to EXTAL2 for now.
* this is needed until more detailed clock topology is supported
*/
cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
BUG_ON(!cpg_base);
reg = cpg_base + (MPCKCR - CPG_BASE);
iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
iounmap(cpg_base);
reg = ioremap_nocache(CKSCR, PAGE_SIZE);
BUG_ON(!reg);
ckscr = ioread32(reg);
iounmap(reg);
switch ((ckscr >> 28) & 0x3) {
case 0:
main_clk.parent = &extal1_clk;
break;
case 1:
main_clk.parent = &extal1_div2_clk;
break;
case 2:
main_clk.parent = &extal2_clk;
break;
case 3:
main_clk.parent = &extal2_div2_clk;
break;
}
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

11
arch/arm/mach-shmobile/clock-r8a7740.c
View File

@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
static struct clk fsibck_clk = {
};
struct clk *main_clks[] = {
static struct clk *main_clks[] = {
&extalr_clk,
&extal1_clk,
&extal2_clk,
@ -317,7 +317,7 @@ enum {
DIV4_NR
};
struct clk div4_clks[DIV4_NR] = {
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
@ -461,7 +461,7 @@ enum {
MSTP329, MSTP328, MSTP323, MSTP320,
MSTP314, MSTP313, MSTP312,
MSTP309,
MSTP309, MSTP304,
MSTP416, MSTP415, MSTP407, MSTP406,
@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
[MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 9, 0), /* GEther */
[MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP], SMSTPCR3, 4, 0), /* TPU0 */
[MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
[MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_tmu.4", &mstp_clks[MSTP111]),
CLKDEV_DEV_ID("sh_tmu.5", &mstp_clks[MSTP111]),
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]),
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]),
@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),

156
arch/arm/mach-shmobile/clock-r8a7778.c
View File

@ -23,9 +23,23 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* MD MD MD MD PLLA PLLB EXTAL clki clkz
* 19 18 12 11 (HMz) (MHz) (MHz)
*----------------------------------------------------------------------------
* 1 0 0 0 x21 x21 38.00 800 800
* 1 0 0 1 x24 x24 33.33 800 800
* 1 0 1 0 x28 x28 28.50 800 800
* 1 0 1 1 x32 x32 25.00 800 800
* 1 1 0 1 x24 x21 33.33 800 700
* 1 1 1 0 x28 x21 28.50 800 600
* 1 1 1 1 x32 x24 25.00 800 600
*/
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/common.h>
#define MSTPCR0 IOMEM(0xffc80030)
@ -37,6 +51,9 @@
#define MSTPCR4 IOMEM(0xffc80050)
#define MSTPCR5 IOMEM(0xffc80054)
#define MSTPCR6 IOMEM(0xffc80058)
#define MODEMR 0xFFCC0020
#define MD(nr) BIT(nr)
/* ioremap() through clock mapping mandatory to avoid
* collision with ARM coherent DMA virtual memory range.
@ -47,36 +64,71 @@ static struct clk_mapping cpg_mapping = {
.len = 0x80,
};
static struct clk clkp = {
.rate = 62500000, /* FIXME: shortcut */
.flags = CLK_ENABLE_ON_INIT,
static struct clk extal_clk = {
/* .rate will be updated on r8a7778_clock_init() */
.mapping = &cpg_mapping,
};
/*
* clock ratio of these clock will be updated
* on r8a7778_clock_init()
*/
SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1);
static struct clk *main_clks[] = {
&clkp,
&extal_clk,
&plla_clk,
&pllb_clk,
&i_clk,
&s_clk,
&s1_clk,
&s3_clk,
&s4_clk,
&b_clk,
&out_clk,
&p_clk,
&g_clk,
&z_clk,
};
enum {
MSTP323, MSTP322, MSTP321,
MSTP114,
MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP016, MSTP015,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
[MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
[MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
[MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
[MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
[MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
[MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
[MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
[MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
};
static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
@ -90,8 +142,86 @@ static struct clk_lookup lookups[] = {
void __init r8a7778_clock_init(void)
{
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
u32 mode;
int k, ret = 0;
BUG_ON(!modemr);
mode = ioread32(modemr);
iounmap(modemr);
switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
case MD(19):
extal_clk.rate = 38000000;
SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
break;
case MD(19) | MD(11):
extal_clk.rate = 33333333;
SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
break;
case MD(19) | MD(12):
extal_clk.rate = 28500000;
SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1);
break;
case MD(19) | MD(12) | MD(11):
extal_clk.rate = 25000000;
SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1);
break;
case MD(19) | MD(18) | MD(11):
extal_clk.rate = 33333333;
SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
break;
case MD(19) | MD(18) | MD(12):
extal_clk.rate = 28500000;
SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
break;
case MD(19) | MD(18) | MD(12) | MD(11):
extal_clk.rate = 25000000;
SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
break;
default:
BUG();
}
if (mode & MD(1)) {
SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3);
SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12);
SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
if (mode & MD(2)) {
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18);
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18);
} else {
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
}
} else {
SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4);
SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16);
SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
if (mode & MD(2)) {
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16);
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16);
} else {
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
}
}
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);

4
arch/arm/mach-shmobile/clock-r8a7779.c
View File

@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
};
enum { MSTP323, MSTP322, MSTP321, MSTP320,
MSTP115, MSTP114,
MSTP116, MSTP115, MSTP114,
MSTP103, MSTP101, MSTP100,
MSTP030,
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
/* MSTP32 clocks */
CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */

238
arch/arm/mach-shmobile/clock-r8a7790.c
View File

@ -22,39 +22,174 @@
#include <linux/kernel.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include <mach/clock.h>
#include <mach/common.h>
/*
* MD EXTAL PLL0 PLL1 PLL3
* 14 13 19 (MHz) *1 *1
*---------------------------------------------------
* 0 0 0 15 x 1 x172/2 x208/2 x106
* 0 0 1 15 x 1 x172/2 x208/2 x88
* 0 1 0 20 x 1 x130/2 x156/2 x80
* 0 1 1 20 x 1 x130/2 x156/2 x66
* 1 0 0 26 / 2 x200/2 x240/2 x122
* 1 0 1 26 / 2 x200/2 x240/2 x102
* 1 1 0 30 / 2 x172/2 x208/2 x106
* 1 1 1 30 / 2 x172/2 x208/2 x88
*
* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
*/
#define MD(nr) (1 << nr)
#define CPG_BASE 0xe6150000
#define CPG_LEN 0x1000
#define SMSTPCR2 0xe6150138
#define SMSTPCR3 0xe615013c
#define SMSTPCR7 0xe615014c
#define MODEMR 0xE6160060
#define SDCKCR 0xE6150074
#define SD2CKCR 0xE6150078
#define SD3CKCR 0xE615007C
#define MMC0CKCR 0xE6150240
#define MMC1CKCR 0xE6150244
#define SSPCKCR 0xE6150248
#define SSPRSCKCR 0xE615024C
static struct clk_mapping cpg_mapping = {
.phys = CPG_BASE,
.len = CPG_LEN,
};
static struct clk p_clk = {
.rate = 65000000, /* shortcut for now */
static struct clk extal_clk = {
/* .rate will be updated on r8a7790_clock_init() */
.mapping = &cpg_mapping,
};
static struct clk mp_clk = {
.rate = 52000000, /* shortcut for now */
.mapping = &cpg_mapping,
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
static struct clk main_clk = {
/* .parent will be set r8a73a4_clock_init */
.ops = &followparent_clk_ops,
};
/*
* clock ratio of these clock will be updated
* on r8a7790_clock_init()
*/
SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
static struct clk *main_clks[] = {
&extal_clk,
&extal_div2_clk,
&main_clk,
&pll1_clk,
&pll1_div2_clk,
&pll3_clk,
&lb_clk,
&qspi_clk,
&zg_clk,
&zx_clk,
&zs_clk,
&hp_clk,
&i_clk,
&b_clk,
&p_clk,
&cl_clk,
&m2_clk,
&imp_clk,
&rclk_clk,
&oscclk_clk,
&zb3_clk,
&zb3d2_clk,
&ddr_clk,
&mp_clk,
&cp_clk,
};
/* SDHI (DIV4) clock */
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = divisors,
.nr_divisors = ARRAY_SIZE(divisors),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum {
DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
};
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */
enum {
DIV6_SD2, DIV6_SD3,
DIV6_MMC0, DIV6_MMC1,
DIV6_SSP, DIV6_SSPRS,
DIV6_NR
};
static struct clk div6_clks[DIV6_NR] = {
[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
[DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
[DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
[DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
[DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
[DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
};
/* MSTP */
enum {
MSTP721, MSTP720,
MSTP304,
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
MSTP_NR
};
enum { MSTP721, MSTP720,
MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@ -64,6 +199,48 @@ static struct clk mstp_clks[MSTP_NR] = {
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
CLKDEV_CON_ID("main", &main_clk),
CLKDEV_CON_ID("pll1", &pll1_clk),
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
CLKDEV_CON_ID("pll3", &pll3_clk),
CLKDEV_CON_ID("zg", &zg_clk),
CLKDEV_CON_ID("zx", &zx_clk),
CLKDEV_CON_ID("zs", &zs_clk),
CLKDEV_CON_ID("hp", &hp_clk),
CLKDEV_CON_ID("i", &i_clk),
CLKDEV_CON_ID("b", &b_clk),
CLKDEV_CON_ID("lb", &lb_clk),
CLKDEV_CON_ID("p", &p_clk),
CLKDEV_CON_ID("cl", &cl_clk),
CLKDEV_CON_ID("m2", &m2_clk),
CLKDEV_CON_ID("imp", &imp_clk),
CLKDEV_CON_ID("rclk", &rclk_clk),
CLKDEV_CON_ID("oscclk", &oscclk_clk),
CLKDEV_CON_ID("zb3", &zb3_clk),
CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
CLKDEV_CON_ID("ddr", &ddr_clk),
CLKDEV_CON_ID("mp", &mp_clk),
CLKDEV_CON_ID("qspi", &qspi_clk),
CLKDEV_CON_ID("cp", &cp_clk),
/* DIV4 */
CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
CLKDEV_CON_ID("sd0", &div4_clks[DIV4_SD0]),
CLKDEV_CON_ID("sd1", &div4_clks[DIV4_SD1]),
/* DIV6 */
CLKDEV_CON_ID("sd2", &div6_clks[DIV6_SD2]),
CLKDEV_CON_ID("sd3", &div6_clks[DIV6_SD3]),
CLKDEV_CON_ID("mmc0", &div6_clks[DIV6_MMC0]),
CLKDEV_CON_ID("mmc1", &div6_clks[DIV6_MMC1]),
CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
/* MSTP */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@ -74,13 +251,60 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
};
#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
extal_clk.rate = e * 1000 * 1000; \
main_clk.parent = m; \
SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
if (mode & MD(19)) \
SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
else \
SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
void __init r8a7790_clock_init(void)
{
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
u32 mode;
int k, ret = 0;
BUG_ON(!modemr);
mode = ioread32(modemr);
iounmap(modemr);
switch (mode & (MD(14) | MD(13))) {
case 0:
R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
break;
case MD(13):
R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
break;
case MD(14):
R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
break;
case MD(13) | MD(14):
R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
break;
}
if (mode & (MD(18)))
SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
else
SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
else
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

111
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
/*
* ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
* exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
* 239.2MHz for VDD_DVFS=1.315V.
*/
[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@ -252,6 +257,101 @@ static struct clk twd_clk = {
.ops = &twd_clk_ops,
};
static struct sh_clk_ops zclk_ops, kicker_ops;
static const struct sh_clk_ops *div4_clk_ops;
static int zclk_set_rate(struct clk *clk, unsigned long rate)
{
int ret;
if (!clk->parent || !__clk_get(clk->parent))
return -ENODEV;
if (readl(FRQCRB) & (1 << 31))
return -EBUSY;
if (rate == clk_get_rate(clk->parent)) {
/* 1:1 - switch off divider */
__raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
/* nullify the divider to prepare for the next time */
ret = div4_clk_ops->set_rate(clk, rate / 2);
if (!ret)
ret = frqcr_kick();
if (ret > 0)
ret = 0;
} else {
/* Enable the divider */
__raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
ret = frqcr_kick();
if (ret >= 0)
/*
* set the divider - call the DIV4 method, it will kick
* FRQCRB too
*/
ret = div4_clk_ops->set_rate(clk, rate);
if (ret < 0)
goto esetrate;
}
esetrate:
__clk_put(clk->parent);
return ret;
}
static long zclk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
parent_freq = clk_get_rate(clk->parent);
if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
return parent_freq;
return div_freq;
}
static unsigned long zclk_recalc(struct clk *clk)
{
/*
* Must recalculate frequencies in case PLL0 has been changed, even if
* the divisor is unused ATM!
*/
unsigned long div_freq = div4_clk_ops->recalc(clk);
if (__raw_readl(FRQCRB) & (1 << 28))
return div_freq;
return clk_get_rate(clk->parent);
}
static int kicker_set_rate(struct clk *clk, unsigned long rate)
{
if (__raw_readl(FRQCRB) & (1 << 31))
return -EBUSY;
return div4_clk_ops->set_rate(clk, rate);
}
static void div4_clk_extend(void)
{
int i;
div4_clk_ops = div4_clks[0].ops;
/* Add a kicker-busy check before changing the rate */
kicker_ops = *div4_clk_ops;
/* We extend the DIV4 clock with a 1:1 pass-through case */
zclk_ops = *div4_clk_ops;
kicker_ops.set_rate = kicker_set_rate;
zclk_ops.set_rate = zclk_set_rate;
zclk_ops.round_rate = zclk_round_rate;
zclk_ops.recalc = zclk_recalc;
for (i = 0; i < DIV4_NR; i++)
div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
}
enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
};
enum { MSTP001,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
MSTP219, MSTP218, MSTP217,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
[MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
[MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
[MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("r_clk", &r_clk),
CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
/* DIV4 clocks */
CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
if (!ret)
if (!ret) {
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
div4_clk_extend();
}
if (!ret)
ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);

8
arch/arm/mach-shmobile/include/mach/clock.h
View File

@ -24,16 +24,16 @@ struct clk name = { \
}
#define SH_FIXED_RATIO_CLK(name, p, r) \
static SH_FIXED_RATIO_CLKg(name, p, r);
static SH_FIXED_RATIO_CLKg(name, p, r)
#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
SH_CLK_RATIO(name, m, d); \
SH_FIXED_RATIO_CLK(name, p, name);
SH_FIXED_RATIO_CLK(name, p, name)
#define SH_CLK_SET_RATIO(p, m, d) \
{ \
do { \
(p)->mul = m; \
(p)->div = d; \
}
} while (0)
#endif

5
arch/arm/mach-shmobile/include/mach/irqs.h
View File

@ -16,4 +16,9 @@
#define IRQPIN_BASE 2000
#define irq_pin(nr) ((nr) + IRQPIN_BASE)
/* GPIO IRQ */
#define _GPIO_IRQ_BASE 2500
#define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x))
#define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y)
#endif /* __ASM_MACH_IRQS_H */

488
arch/arm/mach-shmobile/include/mach/r8a7740.h
View File

@ -28,494 +28,6 @@
#define MD_CK1 (1 << 1)
#define MD_CK0 (1 << 0)
/*
* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* PORT */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
GPIO_PORT210, GPIO_PORT211,
/* IRQ */
GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
GPIO_FN_IRQ1,
GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
GPIO_FN_IRQ8,
GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
GPIO_FN_IRQ10,
GPIO_FN_IRQ11,
GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
GPIO_FN_IRQ17,
GPIO_FN_IRQ18,
GPIO_FN_IRQ19,
GPIO_FN_IRQ20,
GPIO_FN_IRQ21,
GPIO_FN_IRQ22,
GPIO_FN_IRQ23,
GPIO_FN_IRQ24,
GPIO_FN_IRQ25,
GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
/* Function */
/* DBGT */
GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
GPIO_FN_DBGMD21,
/* FSI-A */
GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
GPIO_FN_FSIAISLD_PORT5,
GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
GPIO_FN_FSIASPDIF_PORT18,
GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
GPIO_FN_FSIAIBT,
/* FSI-B */
GPIO_FN_FSIBCK,
/* FMSI */
GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
GPIO_FN_FMSISLD_PORT6,
GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
GPIO_FN_FMSOCK,
/* SCIFA0 */
GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_TXD,
/* SCIFA1 */
GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
GPIO_FN_SCIFA1_RTS,
/* SCIFA2 */
GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
GPIO_FN_SCIFA2_SCK_PORT199,
GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
/* SCIFA3 */
GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
GPIO_FN_SCIFA3_SCK_PORT116,
GPIO_FN_SCIFA3_CTS_PORT117,
GPIO_FN_SCIFA3_RXD_PORT174,
GPIO_FN_SCIFA3_TXD_PORT175,
GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
GPIO_FN_SCIFA3_SCK_PORT158,
GPIO_FN_SCIFA3_CTS_PORT162,
GPIO_FN_SCIFA3_RXD_PORT159,
GPIO_FN_SCIFA3_TXD_PORT160,
/* SCIFA4 */
GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
GPIO_FN_SCIFA4_TXD_PORT13,
GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
GPIO_FN_SCIFA4_TXD_PORT203,
GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
GPIO_FN_SCIFA4_TXD_PORT93,
GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
GPIO_FN_SCIFA4_SCK_PORT205,
/* SCIFA5 */
GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
GPIO_FN_SCIFA5_RXD_PORT10,
GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
GPIO_FN_SCIFA5_TXD_PORT208,
GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
GPIO_FN_SCIFA5_RXD_PORT92,
GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
GPIO_FN_SCIFA5_SCK_PORT206,
/* SCIFA6 */
GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
/* SCIFA7 */
GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
/* SCIFAB */
GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
GPIO_FN_SCIFB_RXD_PORT191,
GPIO_FN_SCIFB_TXD_PORT192,
GPIO_FN_SCIFB_RTS_PORT186,
GPIO_FN_SCIFB_CTS_PORT187,
GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
GPIO_FN_SCIFB_RXD_PORT3,
GPIO_FN_SCIFB_TXD_PORT4,
GPIO_FN_SCIFB_RTS_PORT172,
GPIO_FN_SCIFB_CTS_PORT173,
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
GPIO_FN_RSPI_CK_A,
/* VIO CKO */
GPIO_FN_VIO_CKO1,
GPIO_FN_VIO_CKO2,
GPIO_FN_VIO_CKO_1,
GPIO_FN_VIO_CKO,
/* VIO0 */
GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
GPIO_FN_VIO0_D14_PORT25,
GPIO_FN_VIO0_D15_PORT24,
GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
GPIO_FN_VIO0_D14_PORT95,
GPIO_FN_VIO0_D15_PORT96,
/* VIO1 */
GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
/* TPU0 */
GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
GPIO_FN_TPU0TO3,
GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
GPIO_FN_TPU0TO2_PORT202,
/* SSP1 0 */
GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
/* SSP1 1 */
GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
GPIO_FN_STP1_IPEN_PORT187,
GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
GPIO_FN_STP1_IPEN_PORT193,
/* SIM */
GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_MSIOF2_RSCK,
/* KEYSC */
GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
GPIO_FN_KEYIN1_PORT44,
GPIO_FN_KEYIN2_PORT45,
GPIO_FN_KEYIN3_PORT46,
GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
GPIO_FN_KEYIN1_PORT57,
GPIO_FN_KEYIN2_PORT56,
GPIO_FN_KEYIN3_PORT55,
/* VOU */
GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
GPIO_FN_DV_CLK,
GPIO_FN_DV_VSYNC,
GPIO_FN_DV_HSYNC,
/* MEMC */
GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
GPIO_FN_MEMC_ADV,
GPIO_FN_MEMC_WAIT,
GPIO_FN_MEMC_BUSCLK,
GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
GPIO_FN_MEMC_DREQ0,
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
/* MSIOF1 */
GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
GPIO_FN_MSIOF1_TSYNC_PORT120,
GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
GPIO_FN_MSIOF1_RXD_PORT75,
GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
/* GPIO */
GPIO_FN_GPO0, GPIO_FN_GPI0,
GPIO_FN_GPO1, GPIO_FN_GPI1,
/* USB0 */
GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
/* USB1 */
GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
/* BBIF1 */
GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
/* BBIF2 */
GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
GPIO_FN_BBIF2_RXD2_PORT60,
GPIO_FN_BBIF2_TSYNC2_PORT6,
GPIO_FN_BBIF2_TSCK2_PORT59,
GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
GPIO_FN_BBIF2_TXD2_PORT183,
GPIO_FN_BBIF2_TSCK2_PORT89,
GPIO_FN_BBIF2_TSYNC2_PORT184,
/* BSC / FLCTL / PCMCIA */
GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
GPIO_FN_CS5B, GPIO_FN_CS6A,
GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
GPIO_FN_CS5A_PORT19,
GPIO_FN_IOIS16, /* ? */
GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
GPIO_FN_A4_FOE, /* share with FLCTL */
GPIO_FN_A5_FCDE, /* share with FLCTL */
GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
GPIO_FN_A26,
GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
GPIO_FN_WE0_FWE, /* share with FLCTL */
GPIO_FN_WE1,
GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
GPIO_FN_RD_FSC, /* share with FLCTL */
GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
GPIO_FN_WAIT_PORT90,
GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
/* IRDA */
GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
/* ATAPI */
GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
/* RMII */
GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
GPIO_FN_RMII_REF50CK, /* for RMII */
GPIO_FN_RMII_REF125CK, /* for GMII */
/* GEther */
GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
/* DMA0 */
GPIO_FN_DREQ0, GPIO_FN_DACK0,
/* DMA1 */
GPIO_FN_DREQ1, GPIO_FN_DACK1,
/* SYSC */
GPIO_FN_RESETOUTS,
GPIO_FN_RESETP_PULLUP,
GPIO_FN_RESETP_PLAIN,
/* HDMI */
GPIO_FN_HDMI_HPD,
GPIO_FN_HDMI_CEC,
/* SDENC */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
/* IRREM */
GPIO_FN_IROUT,
/* DEBUG */
GPIO_FN_EDEBGREQ_PULLDOWN,
GPIO_FN_EDEBGREQ_PULLUP,
GPIO_FN_TRACEAUD_FROM_VIO,
GPIO_FN_TRACEAUD_FROM_LCDC0,
GPIO_FN_TRACEAUD_FROM_MEMC,
};
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,

3
arch/arm/mach-shmobile/include/mach/r8a7778.h
View File

@ -18,6 +18,7 @@
#ifndef __ASM_R8A7778_H__
#define __ASM_R8A7778_H__
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/sh_eth.h>
extern void r8a7778_add_standard_devices(void);
@ -28,5 +29,7 @@ extern void r8a7778_init_irq(void);
extern void r8a7778_init_irq_dt(void);
extern void r8a7778_clock_init(void);
extern void r8a7778_init_irq_extpin(int irlm);
extern void r8a7778_pinmux_init(void);
extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
#endif /* __ASM_R8A7778_H__ */

391
arch/arm/mach-shmobile/include/mach/sh7372.h
View File

@ -15,397 +15,6 @@
#include <linux/pm_domain.h>
#include <mach/pm-rmobile.h>
/*
* Pin Function Controller:
* GPIO_FN_xx - GPIO used to select pin function
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
*/
enum {
/* PORT */
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
GPIO_PORT190,
/* IRQ */
GPIO_FN_IRQ0_6, /* PORT 6 */
GPIO_FN_IRQ0_162, /* PORT 162 */
GPIO_FN_IRQ1, /* PORT 12 */
GPIO_FN_IRQ2_4, /* PORT 4 */
GPIO_FN_IRQ2_5, /* PORT 5 */
GPIO_FN_IRQ3_8, /* PORT 8 */
GPIO_FN_IRQ3_16, /* PORT 16 */
GPIO_FN_IRQ4_17, /* PORT 17 */
GPIO_FN_IRQ4_163, /* PORT 163 */
GPIO_FN_IRQ5, /* PORT 18 */
GPIO_FN_IRQ6_39, /* PORT 39 */
GPIO_FN_IRQ6_164, /* PORT 164 */
GPIO_FN_IRQ7_40, /* PORT 40 */
GPIO_FN_IRQ7_167, /* PORT 167 */
GPIO_FN_IRQ8_41, /* PORT 41 */
GPIO_FN_IRQ8_168, /* PORT 168 */
GPIO_FN_IRQ9_42, /* PORT 42 */
GPIO_FN_IRQ9_169, /* PORT 169 */
GPIO_FN_IRQ10, /* PORT 65 */
GPIO_FN_IRQ11, /* PORT 67 */
GPIO_FN_IRQ12_80, /* PORT 80 */
GPIO_FN_IRQ12_137, /* PORT 137 */
GPIO_FN_IRQ13_81, /* PORT 81 */
GPIO_FN_IRQ13_145, /* PORT 145 */
GPIO_FN_IRQ14_82, /* PORT 82 */
GPIO_FN_IRQ14_146, /* PORT 146 */
GPIO_FN_IRQ15_83, /* PORT 83 */
GPIO_FN_IRQ15_147, /* PORT 147 */
GPIO_FN_IRQ16_84, /* PORT 84 */
GPIO_FN_IRQ16_170, /* PORT 170 */
GPIO_FN_IRQ17, /* PORT 85 */
GPIO_FN_IRQ18, /* PORT 86 */
GPIO_FN_IRQ19, /* PORT 87 */
GPIO_FN_IRQ20, /* PORT 92 */
GPIO_FN_IRQ21, /* PORT 93 */
GPIO_FN_IRQ22, /* PORT 94 */
GPIO_FN_IRQ23, /* PORT 95 */
GPIO_FN_IRQ24, /* PORT 112 */
GPIO_FN_IRQ25, /* PORT 119 */
GPIO_FN_IRQ26_121, /* PORT 121 */
GPIO_FN_IRQ26_172, /* PORT 172 */
GPIO_FN_IRQ27_122, /* PORT 122 */
GPIO_FN_IRQ27_180, /* PORT 180 */
GPIO_FN_IRQ28_123, /* PORT 123 */
GPIO_FN_IRQ28_181, /* PORT 181 */
GPIO_FN_IRQ29_129, /* PORT 129 */
GPIO_FN_IRQ29_182, /* PORT 182 */
GPIO_FN_IRQ30_130, /* PORT 130 */
GPIO_FN_IRQ30_183, /* PORT 183 */
GPIO_FN_IRQ31_138, /* PORT 138 */
GPIO_FN_IRQ31_184, /* PORT 184 */
/*
* MSIOF0 (PORT 36, 37, 38, 39
* 40, 41, 42, 43, 44, 45)
*/
GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_MSIOF0_MCK1, GPIO_FN_MSIOF0_SS1,
GPIO_FN_MSIOF0_SS2, GPIO_FN_MSIOF0_TXD,
/*
* MSIOF1 (PORT 39, 40, 41, 42, 43, 44
* 84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
*/
GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
GPIO_FN_MSIOF1_TXD_41, GPIO_FN_MSIOF1_RXD_42,
GPIO_FN_MSIOF1_TXD_90, GPIO_FN_MSIOF1_RXD_91,
GPIO_FN_MSIOF1_SS1_43, GPIO_FN_MSIOF1_SS2_44,
GPIO_FN_MSIOF1_SS1_92, GPIO_FN_MSIOF1_SS2_93,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
/*
* MSIOF2 (PORT 134, 135, 136, 137, 138, 139
* 148, 149, 150, 151)
*/
GPIO_FN_MSIOF2_RSCK, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_MSIOF2_SS1, GPIO_FN_MSIOF2_SS2,
GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TXD,
/* MSIOF3 (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_TXD,
GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_BBIF1_FLOW, GPIO_FN_BB_RX_FLOW_N,
/* MSIOF4 (PORT 0, 1, 2, 3) */
GPIO_FN_BBIF2_TSCK1, GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_BBIF2_TXD1, GPIO_FN_BBIF2_RXD,
/* FSI (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
GPIO_FN_FSIACK, GPIO_FN_FSIBCK,
GPIO_FN_FSIAILR, GPIO_FN_FSIAIBT,
GPIO_FN_FSIAISLD, GPIO_FN_FSIAOMC,
GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
GPIO_FN_FSIAOSLD, GPIO_FN_FSIASPDIF_11,
GPIO_FN_FSIASPDIF_15,
/* FMSI (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
GPIO_FN_FMSOCK, GPIO_FN_FMSOOLR,
GPIO_FN_FMSIOLR, GPIO_FN_FMSOOBT,
GPIO_FN_FMSIOBT, GPIO_FN_FMSOSLD,
GPIO_FN_FMSOILR, GPIO_FN_FMSIILR,
GPIO_FN_FMSOIBT, GPIO_FN_FMSIIBT,
GPIO_FN_FMSISLD, GPIO_FN_FMSICK,
/* SCIFA0 (PORT 152, 153, 156, 157, 158) */
GPIO_FN_SCIFA0_TXD, GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_RTS,
GPIO_FN_SCIFA0_CTS,
/* SCIFA1 (PORT 154, 155, 159, 160, 161) */
GPIO_FN_SCIFA1_TXD, GPIO_FN_SCIFA1_RXD,
GPIO_FN_SCIFA1_SCK, GPIO_FN_SCIFA1_RTS,
GPIO_FN_SCIFA1_CTS,
/* SCIFA2 (PORT 94, 95, 96, 97, 98) */
GPIO_FN_SCIFA2_CTS1, GPIO_FN_SCIFA2_RTS1,
GPIO_FN_SCIFA2_TXD1, GPIO_FN_SCIFA2_RXD1,
GPIO_FN_SCIFA2_SCK1,
/* SCIFA3 (PORT 43, 44,
140, 141, 142, 143, 144) */
GPIO_FN_SCIFA3_CTS_43, GPIO_FN_SCIFA3_CTS_140,
GPIO_FN_SCIFA3_RTS_44, GPIO_FN_SCIFA3_RTS_141,
GPIO_FN_SCIFA3_SCK, GPIO_FN_SCIFA3_TXD,
GPIO_FN_SCIFA3_RXD,
/* SCIFA4 (PORT 5, 6) */
GPIO_FN_SCIFA4_RXD, GPIO_FN_SCIFA4_TXD,
/* SCIFA5 (PORT 8, 12) */
GPIO_FN_SCIFA5_RXD, GPIO_FN_SCIFA5_TXD,
/* SCIFB (PORT 162, 163, 164, 165, 166) */
GPIO_FN_SCIFB_SCK, GPIO_FN_SCIFB_RTS,
GPIO_FN_SCIFB_CTS, GPIO_FN_SCIFB_TXD,
GPIO_FN_SCIFB_RXD,
/*
* CEU (PORT 16, 17,
* 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
* 110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
* 120)
*/
GPIO_FN_VIO_HD, GPIO_FN_VIO_CKO1, GPIO_FN_VIO_CKO2,
GPIO_FN_VIO_VD, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
GPIO_FN_VIO_CKO,
GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
GPIO_FN_VIO_D15,
/* USB0 (PORT 113, 114, 115, 116, 117, 167) */
GPIO_FN_IDIN_0, GPIO_FN_EXTLP_0,
GPIO_FN_OVCN2_0, GPIO_FN_PWEN_0,
GPIO_FN_OVCN_0, GPIO_FN_VBUS0_0,
/* USB1 (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
GPIO_FN_IDIN_1_18, GPIO_FN_IDIN_1_113,
GPIO_FN_PWEN_1_115, GPIO_FN_PWEN_1_138,
GPIO_FN_OVCN_1_114, GPIO_FN_OVCN_1_162,
GPIO_FN_EXTLP_1, GPIO_FN_OVCN2_1,
GPIO_FN_VBUS0_1,
/* GPIO (PORT 41, 42, 43, 44) */
GPIO_FN_GPI0, GPIO_FN_GPI1, GPIO_FN_GPO0, GPIO_FN_GPO1,
/*
* BSC (PORT 19,
* 20, 21, 22, 25, 26, 27, 28, 29,
* 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
* 40, 41, 42, 43, 44, 45,
* 62, 63, 64, 65, 66, 67,
* 71, 72, 74, 75)
*/
GPIO_FN_BS, GPIO_FN_WE1,
GPIO_FN_CKO, GPIO_FN_WAIT, GPIO_FN_RDWR,
GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
GPIO_FN_A26,
GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_CS6A,
/*
* BSC/FLCTL (PORT 23, 24,
* 46, 47, 48, 49,
* 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
* 60, 61, 69, 70)
*/
GPIO_FN_RD_FSC, GPIO_FN_WE0_FWE,
GPIO_FN_A4_FOE, GPIO_FN_A5_FCDE,
GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, GPIO_FN_D2_NAF2,
GPIO_FN_D3_NAF3, GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5,
GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, GPIO_FN_D8_NAF8,
GPIO_FN_D9_NAF9, GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11,
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
/* SPU2 (PORT 65) */
GPIO_FN_VINT_I,
/* FLCTL (PORT 66, 68, 73) */
GPIO_FN_FCE1, GPIO_FN_FCE0, GPIO_FN_FRB,
/* HSI (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
GPIO_FN_GP_RX_FLAG, GPIO_FN_GP_RX_DATA, GPIO_FN_GP_TX_READY,
GPIO_FN_GP_RX_WAKE, GPIO_FN_MP_TX_FLAG, GPIO_FN_MP_TX_DATA,
GPIO_FN_MP_RX_READY, GPIO_FN_MP_TX_WAKE,
/*
* MFI (PORT 76, 77, 78, 79,
* 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
* 90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
*/
GPIO_FN_MFIv6, /* see MSEL4CR 6 */
GPIO_FN_MFIv4, /* see MSEL4CR 6 */
GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_BUSCLK_MEMC_A0,
GPIO_FN_MEMC_CS1_MEMC_A1, GPIO_FN_MEMC_ADV_MEMC_DREQ0,
GPIO_FN_MEMC_WAIT_MEMC_DREQ1, GPIO_FN_MEMC_NOE,
GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_INT,
GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
GPIO_FN_MEMC_AD15,
/* SIM (PORT 94, 95, 98) */
GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, GPIO_FN_SIM_D,
/* TPU (PORT 93, 99, 112, 160, 161) */
GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
GPIO_FN_TPU0TO2_93, GPIO_FN_TPU0TO2_99,
GPIO_FN_TPU0TO3,
/* I2C2 (PORT 110, 111) */
GPIO_FN_I2C_SCL2, GPIO_FN_I2C_SDA2,
/* I2C3(1) (PORT 114, 115) */
GPIO_FN_I2C_SCL3, GPIO_FN_I2C_SDA3,
/* I2C3(2) (PORT 137, 145) */
GPIO_FN_I2C_SCL3S, GPIO_FN_I2C_SDA3S,
/* I2C4(2) (PORT 116, 117) */
GPIO_FN_I2C_SCL4, GPIO_FN_I2C_SDA4,
/* I2C4(2) (PORT 146, 147) */
GPIO_FN_I2C_SCL4S, GPIO_FN_I2C_SDA4S,
/*
* KEYSC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
* 130, 131, 132, 133, 134, 135, 136)
*/
GPIO_FN_KEYOUT0, GPIO_FN_KEYIN0_121, GPIO_FN_KEYIN0_136,
GPIO_FN_KEYOUT1, GPIO_FN_KEYIN1_122, GPIO_FN_KEYIN1_135,
GPIO_FN_KEYOUT2, GPIO_FN_KEYIN2_123, GPIO_FN_KEYIN2_134,
GPIO_FN_KEYOUT3, GPIO_FN_KEYIN3_124, GPIO_FN_KEYIN3_133,
GPIO_FN_KEYOUT4, GPIO_FN_KEYIN4,
GPIO_FN_KEYOUT5, GPIO_FN_KEYIN5,
GPIO_FN_KEYOUT6, GPIO_FN_KEYIN6,
GPIO_FN_KEYOUT7, GPIO_FN_KEYIN7,
/*
* LCDC (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
* 130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
* 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
* 150, 151)
*/
GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDVSYN,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_LCDRD,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDLCLK,
GPIO_FN_LCDDON,
GPIO_FN_LCDD0, GPIO_FN_LCDD1, GPIO_FN_LCDD2, GPIO_FN_LCDD3,
GPIO_FN_LCDD4, GPIO_FN_LCDD5, GPIO_FN_LCDD6, GPIO_FN_LCDD7,
GPIO_FN_LCDD8, GPIO_FN_LCDD9, GPIO_FN_LCDD10, GPIO_FN_LCDD11,
GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
/* IRDA (PORT 139, 140, 141, 142) */
GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
GPIO_FN_IROUT_139, GPIO_FN_IROUT_140,
/* TSIF1 (PORT 156, 157, 158, 159) */
GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
GPIO_FN_TS_SPSYNC1, GPIO_FN_TS_SDAT1,
GPIO_FN_TS_SDEN1, GPIO_FN_TS_SCK1,
/* TSIF2 (PORT 137, 145, 146, 147) */
GPIO_FN_TS_SPSYNC2, GPIO_FN_TS_SDAT2,
GPIO_FN_TS_SDEN2, GPIO_FN_TS_SCK2,
/* HDMI (PORT 169, 170) */
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
/* SDENC see MSEL4CR 19 */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
};
/* DMA slave IDs */
enum {
SHDMA_SLAVE_INVALID,

24
arch/arm/mach-shmobile/setup-r8a7740.c
View File

@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
}
/* PFC */
static struct resource r8a7740_pfc_resources[] = {
[0] = {
.start = 0xe6050000,
.end = 0xe6057fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0xe605800c,
.end = 0xe605802b,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device r8a7740_pfc_device = {
.name = "pfc-r8a7740",
.id = -1,
.resource = r8a7740_pfc_resources,
.num_resources = ARRAY_SIZE(r8a7740_pfc_resources),
static const struct resource pfc_resources[] = {
DEFINE_RES_MEM(0xe6050000, 0x8000),
DEFINE_RES_MEM(0xe605800c, 0x0020),
};
void __init r8a7740_pinmux_init(void)
{
platform_device_register(&r8a7740_pfc_device);
platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
ARRAY_SIZE(pfc_resources));
}
static struct renesas_intc_irqpin_config irqpin0_platform_data = {

99
arch/arm/mach-shmobile/setup-r8a7778.c
View File

@ -24,6 +24,7 @@
#include <linux/irqchip/arm-gic.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <linux/platform_device.h>
#include <linux/irqchip.h>
@ -80,12 +81,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
.clocksource_rating = 200,
};
/* Ether */
static struct resource ether_resources[] = {
DEFINE_RES_MEM(0xfde00000, 0x400),
DEFINE_RES_IRQ(gic_iid(0x89)),
};
#define r8a7778_register_tmu(idx) \
platform_device_register_resndata( \
&platform_bus, "sh_tmu", idx, \
@ -94,6 +89,90 @@ static struct resource ether_resources[] = {
&sh_tmu##idx##_platform_data, \
sizeof(sh_tmu##idx##_platform_data))
/* Ether */
static struct resource ether_resources[] = {
DEFINE_RES_MEM(0xfde00000, 0x400),
DEFINE_RES_IRQ(gic_iid(0x89)),
};
void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
{
platform_device_register_resndata(&platform_bus, "sh_eth", -1,
ether_resources,
ARRAY_SIZE(ether_resources),
pdata, sizeof(*pdata));
}
/* PFC/GPIO */
static struct resource pfc_resources[] = {
DEFINE_RES_MEM(0xfffc0000, 0x118),
};
#define R8A7778_GPIO(idx) \
static struct resource r8a7778_gpio##idx##_resources[] = { \
DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
DEFINE_RES_IRQ(gic_iid(0x87)), \
}; \
\
static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \
.gpio_base = 32 * (idx), \
.irq_base = GPIO_IRQ_BASE(idx), \
.number_of_pins = 32, \
.pctl_name = "pfc-r8a7778", \
}
R8A7778_GPIO(0);
R8A7778_GPIO(1);
R8A7778_GPIO(2);
R8A7778_GPIO(3);
R8A7778_GPIO(4);
#define r8a7778_register_gpio(idx) \
platform_device_register_resndata( \
&platform_bus, "gpio_rcar", idx, \
r8a7778_gpio##idx##_resources, \
ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
&r8a7778_gpio##idx##_platform_data, \
sizeof(r8a7778_gpio##idx##_platform_data))
void __init r8a7778_pinmux_init(void)
{
platform_device_register_simple(
"pfc-r8a7778", -1,
pfc_resources,
ARRAY_SIZE(pfc_resources));
r8a7778_register_gpio(0);
r8a7778_register_gpio(1);
r8a7778_register_gpio(2);
r8a7778_register_gpio(3);
r8a7778_register_gpio(4);
};
/* SDHI */
static struct resource sdhi_resources[] = {
/* SDHI0 */
DEFINE_RES_MEM(0xFFE4C000, 0x100),
DEFINE_RES_IRQ(gic_iid(0x77)),
/* SDHI1 */
DEFINE_RES_MEM(0xFFE4D000, 0x100),
DEFINE_RES_IRQ(gic_iid(0x78)),
/* SDHI2 */
DEFINE_RES_MEM(0xFFE4F000, 0x100),
DEFINE_RES_IRQ(gic_iid(0x76)),
};
void __init r8a7778_sdhi_init(int id,
struct sh_mobile_sdhi_info *info)
{
BUG_ON(id < 0 || id > 2);
platform_device_register_resndata(
&platform_bus, "sh_mobile_sdhi", id,
sdhi_resources + (2 * id), 2,
info, sizeof(*info));
}
void __init r8a7778_add_standard_devices(void)
{
int i;
@ -118,14 +197,6 @@ void __init r8a7778_add_standard_devices(void)
r8a7778_register_tmu(1);
}
void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
{
platform_device_register_resndata(&platform_bus, "sh_eth", -1,
ether_resources,
ARRAY_SIZE(ether_resources),
pdata, sizeof(*pdata));
}
static struct renesas_intc_irqpin_config irqpin_platform_data = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
.sense_bitfield_width = 2,

17
arch/arm/mach-shmobile/setup-r8a7779.c
View File

@ -65,11 +65,7 @@ void __init r8a7779_map_io(void)
}
static struct resource r8a7779_pfc_resources[] = {
[0] = {
.start = 0xfffc0000,
.end = 0xfffc023b,
.flags = IORESOURCE_MEM,
},
DEFINE_RES_MEM(0xfffc0000, 0x023c),
};
static struct platform_device r8a7779_pfc_device = {
@ -81,15 +77,8 @@ static struct platform_device r8a7779_pfc_device = {
#define R8A7779_GPIO(idx, npins) \
static struct resource r8a7779_gpio##idx##_resources[] = { \
[0] = { \
.start = 0xffc40000 + 0x1000 * (idx), \
.end = 0xffc4002b + 0x1000 * (idx), \
.flags = IORESOURCE_MEM, \
}, \
[1] = { \
.start = gic_iid(0xad + (idx)), \
.flags = IORESOURCE_IRQ, \
} \
DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
}; \
\
static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \

44
arch/arm/mach-shmobile/setup-r8a7790.c
View File

@ -23,21 +23,55 @@
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/serial_sci.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7790.h>
#include <asm/mach/arch.h>
static const struct resource pfc_resources[] = {
static struct resource pfc_resources[] __initdata = {
DEFINE_RES_MEM(0xe6060000, 0x250),
DEFINE_RES_MEM(0xe6050000, 0x5050),
};
#define R8A7790_GPIO(idx) \
static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
}; \
\
static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
.gpio_base = 32 * (idx), \
.irq_base = 0, \
.number_of_pins = 32, \
.pctl_name = "pfc-r8a7790", \
.has_both_edge_trigger = 1, \
}; \
R8A7790_GPIO(0);
R8A7790_GPIO(1);
R8A7790_GPIO(2);
R8A7790_GPIO(3);
R8A7790_GPIO(4);
R8A7790_GPIO(5);
#define r8a7790_register_gpio(idx) \
platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
r8a7790_gpio##idx##_resources, \
ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
&r8a7790_gpio##idx##_platform_data, \
sizeof(r8a7790_gpio##idx##_platform_data))
void __init r8a7790_pinmux_init(void)
{
platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
ARRAY_SIZE(pfc_resources));
r8a7790_register_gpio(0);
r8a7790_register_gpio(1);
r8a7790_register_gpio(2);
r8a7790_register_gpio(3);
r8a7790_register_gpio(4);
r8a7790_register_gpio(5);
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
@ -69,7 +103,7 @@ void __init r8a7790_pinmux_init(void)
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
static const struct plat_sci_port scif[] = {
static struct plat_sci_port scif[] __initdata = {
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@ -86,11 +120,11 @@ static inline void r8a7790_register_scif(int idx)
sizeof(struct plat_sci_port));
}
static struct renesas_irqc_config irqc0_data = {
static struct renesas_irqc_config irqc0_data __initdata = {
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
};
static struct resource irqc0_resources[] = {
static struct resource irqc0_resources[] __initdata = {
DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */

91
arch/arm/mach-shmobile/setup-sh73a0.c
View File

@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
};
static struct resource tmu00_resources[] = {
[0] = {
.name = "TMU00",
.start = 0xfff60008,
.end = 0xfff60013,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
[1] = {
.start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
.flags = IORESOURCE_IRQ,
@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
};
static struct resource tmu01_resources[] = {
[0] = {
.name = "TMU01",
.start = 0xfff60014,
.end = 0xfff6001f,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
[1] = {
.start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
.flags = IORESOURCE_IRQ,
@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
};
static struct resource i2c0_resources[] = {
[0] = {
.name = "IIC0",
.start = 0xe6820000,
.end = 0xe6820425 - 1,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
[1] = {
.start = gic_spi(167),
.end = gic_spi(170),
@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
};
static struct resource i2c1_resources[] = {
[0] = {
.name = "IIC1",
.start = 0xe6822000,
.end = 0xe6822425 - 1,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
[1] = {
.start = gic_spi(51),
.end = gic_spi(54),
@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
};
static struct resource i2c2_resources[] = {
[0] = {
.name = "IIC2",
.start = 0xe6824000,
.end = 0xe6824425 - 1,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
[1] = {
.start = gic_spi(171),
.end = gic_spi(174),
@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
};
static struct resource i2c3_resources[] = {
[0] = {
.name = "IIC3",
.start = 0xe6826000,
.end = 0xe6826425 - 1,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
[1] = {
.start = gic_spi(183),
.end = gic_spi(186),
@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
};
static struct resource i2c4_resources[] = {
[0] = {
.name = "IIC4",
.start = 0xe6828000,
.end = 0xe6828425 - 1,
.flags = IORESOURCE_MEM,
},
[0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
[1] = {
.start = gic_spi(187),
.end = gic_spi(190),
@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
};
static struct resource sh73a0_dmae_resources[] = {
{
/* Registers including DMAOR and channels including DMARSx */
.start = 0xfe000020,
.end = 0xfe008a00 - 1,
.flags = IORESOURCE_MEM,
},
DEFINE_RES_MEM(0xfe000020, 0x89e0),
{
.name = "error_irq",
.start = gic_spi(129),
@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
/* Resource order important! */
static struct resource sh73a0_mpdma_resources[] = {
{
/* Channel registers and DMAOR */
.start = 0xec618020,
.end = 0xec61828f,
.flags = IORESOURCE_MEM,
},
{
DEFINE_RES_MEM(0xec618020, 0x270),
/* DMARSx */
.start = 0xec619000,
.end = 0xec61900b,
.flags = IORESOURCE_MEM,
},
DEFINE_RES_MEM(0xec619000, 0xc),
{
.name = "error_irq",
.start = gic_spi(181),
@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
/* an IPMMU module for ICB */
static struct resource ipmmu_resources[] = {
[0] = {
.name = "IPMMU",
.start = 0xfe951000,
.end = 0xfe9510ff,
.flags = IORESOURCE_MEM,
},
DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
};
static const char * const ipmmu_dev_names[] = {
@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
ARRAY_SIZE(sh73a0_late_devices));
}
void __init sh73a0_init_delay(void)
{
shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
}
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
void __init __weak sh73a0_register_twd(void) { }
void __init sh73a0_earlytimer_init(void)
{
sh73a0_init_delay();
sh73a0_clock_init();
shmobile_earlytimer_init();
sh73a0_register_twd();
@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
#ifdef CONFIG_USE_OF
void __init sh73a0_init_delay(void)
{
shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
}
static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
{},
};
void __init sh73a0_add_standard_devices_dt(void)
{
struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
/* clocks are setup late during boot in the case of DT */
sh73a0_clock_init();
@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
ARRAY_SIZE(sh73a0_devices_dt));
of_platform_populate(NULL, of_default_bus_match_table,
sh73a0_auxdata_lookup, NULL);
/* Instantiate cpufreq-cpu0 */
platform_device_register_full(&devinfo);
}
static const char *sh73a0_boards_compat_dt[] __initdata = {

28
drivers/gpio/gpio-rcar.c
View File

@ -49,6 +49,7 @@ struct gpio_rcar_priv {
#define POSNEG 0x20
#define EDGLEVEL 0x24
#define FILONOFF 0x28
#define BOTHEDGE 0x4c
static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
unsigned int hwirq,
bool active_high_rising_edge,
bool level_trigger)
bool level_trigger,
bool both)
{
unsigned long flags;
@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
/* Configure edge or level trigger in EDGLEVEL */
gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
/* Select one edge or both edges in BOTHEDGE */
if (p->config.has_both_edge_trigger)
gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
/* Select "Interrupt Input Mode" in IOINTSEL */
gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
switch (type & IRQ_TYPE_SENSE_MASK) {
case IRQ_TYPE_LEVEL_HIGH:
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
false);
break;
case IRQ_TYPE_LEVEL_LOW:
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
false);
break;
case IRQ_TYPE_EDGE_RISING:
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
false);
break;
case IRQ_TYPE_EDGE_FALLING:
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
false);
break;
case IRQ_TYPE_EDGE_BOTH:
if (!p->config.has_both_edge_trigger)
return -EINVAL;
gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
true);
break;
default:
return -EINVAL;
@ -333,7 +349,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
}
if (devm_request_irq(&pdev->dev, irq->start,
gpio_rcar_irq_handler, 0, name, p)) {
gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
dev_err(&pdev->dev, "failed to request IRQ\n");
ret = -ENOENT;
goto err1;

13
drivers/pinctrl/sh-pfc/Kconfig
View File

@ -5,8 +5,6 @@
if ARCH_SHMOBILE || SUPERH
config PINCTRL_SH_PFC
# XXX move off the gpio dependency
depends on GPIOLIB
select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
depends on ARCH_R8A7740
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7778
def_bool y
depends on ARCH_R8A7778
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7779
def_bool y
depends on ARCH_R8A7779
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A7790
def_bool y
depends on ARCH_R8A7790
select PINCTRL_SH_PFC
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203
@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
def_bool y
depends on ARCH_SH73A0
select PINCTRL_SH_PFC
select REGULATOR
config PINCTRL_PFC_SH7720
def_bool y

2
drivers/pinctrl/sh-pfc/Makefile
View File

@ -5,7 +5,9 @@ endif
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

22
drivers/pinctrl/sh-pfc/core.c
View File

@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
spin_lock_init(&pfc->lock);
if (info->ops && info->ops->init) {
ret = info->ops->init(pfc);
if (ret < 0)
return ret;
}
pinctrl_provide_dummies();
/*
@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
*/
ret = sh_pfc_register_pinctrl(pfc);
if (unlikely(ret != 0))
return ret;
goto error;
#ifdef CONFIG_GPIO_SH_PFC
/*
@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
error:
if (info->ops && info->ops->exit)
info->ops->exit(pfc);
return ret;
}
static int sh_pfc_remove(struct platform_device *pdev)
@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
#endif
sh_pfc_unregister_pinctrl(pfc);
if (pfc->info->ops && pfc->info->ops->exit)
pfc->info->ops->exit(pfc);
platform_set_drvdata(pdev, NULL);
return 0;
@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A7740
{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7778
{ "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7790
{ "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif

4
drivers/pinctrl/sh-pfc/core.h
View File

@ -11,6 +11,7 @@
#define __SH_PFC_CORE_H__
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include "sh_pfc.h"
@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
void *soc_data;
spinlock_t lock;
unsigned int num_windows;
@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;

1923
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

File diff suppressed because it is too large Load Diff

2783
drivers/pinctrl/sh-pfc/pfc-r8a7778.c Normal file
View File

File diff suppressed because it is too large Load Diff

493
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View File

File diff suppressed because it is too large Load Diff

3835
drivers/pinctrl/sh-pfc/pfc-r8a7790.c Normal file
View File

File diff suppressed because it is too large Load Diff

1652
drivers/pinctrl/sh-pfc/pfc-sh7372.c
View File

File diff suppressed because it is too large Load Diff

742
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -20,9 +20,12 @@
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/slab.h>
#include <mach/sh73a0.h>
#include <mach/irqs.h>
#include "core.h"
@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
static const unsigned int sdhi2_ctrl_mux[] = {
SDHICMD2_MARK, SDHICLK2_MARK,
};
/* - TPU0 ------------------------------------------------------------------- */
static const unsigned int tpu0_to0_pins[] = {
/* TO */
55,
};
static const unsigned int tpu0_to0_mux[] = {
TPU0TO0_MARK,
};
static const unsigned int tpu0_to1_pins[] = {
/* TO */
59,
};
static const unsigned int tpu0_to1_mux[] = {
TPU0TO1_MARK,
};
static const unsigned int tpu0_to2_pins[] = {
/* TO */
140,
};
static const unsigned int tpu0_to2_mux[] = {
TPU0TO2_MARK,
};
static const unsigned int tpu0_to3_pins[] = {
/* TO */
141,
};
static const unsigned int tpu0_to3_mux[] = {
TPU0TO3_MARK,
};
/* - TPU1 ------------------------------------------------------------------- */
static const unsigned int tpu1_to0_pins[] = {
/* TO */
246,
};
static const unsigned int tpu1_to0_mux[] = {
TPU1TO0_MARK,
};
static const unsigned int tpu1_to1_0_pins[] = {
/* TO */
28,
};
static const unsigned int tpu1_to1_0_mux[] = {
PORT28_TPU1TO1_MARK,
};
static const unsigned int tpu1_to1_1_pins[] = {
/* TO */
29,
};
static const unsigned int tpu1_to1_1_mux[] = {
PORT29_TPU1TO1_MARK,
};
static const unsigned int tpu1_to2_pins[] = {
/* TO */
153,
};
static const unsigned int tpu1_to2_mux[] = {
TPU1TO2_MARK,
};
static const unsigned int tpu1_to3_pins[] = {
/* TO */
145,
};
static const unsigned int tpu1_to3_mux[] = {
TPU1TO3_MARK,
};
/* - TPU2 ------------------------------------------------------------------- */
static const unsigned int tpu2_to0_pins[] = {
/* TO */
248,
};
static const unsigned int tpu2_to0_mux[] = {
TPU2TO0_MARK,
};
static const unsigned int tpu2_to1_pins[] = {
/* TO */
197,
};
static const unsigned int tpu2_to1_mux[] = {
TPU2TO1_MARK,
};
static const unsigned int tpu2_to2_pins[] = {
/* TO */
50,
};
static const unsigned int tpu2_to2_mux[] = {
TPU2TO2_MARK,
};
static const unsigned int tpu2_to3_pins[] = {
/* TO */
51,
};
static const unsigned int tpu2_to3_mux[] = {
TPU2TO3_MARK,
};
/* - TPU3 ------------------------------------------------------------------- */
static const unsigned int tpu3_to0_pins[] = {
/* TO */
163,
};
static const unsigned int tpu3_to0_mux[] = {
TPU3TO0_MARK,
};
static const unsigned int tpu3_to1_pins[] = {
/* TO */
247,
};
static const unsigned int tpu3_to1_mux[] = {
TPU3TO1_MARK,
};
static const unsigned int tpu3_to2_pins[] = {
/* TO */
54,
};
static const unsigned int tpu3_to2_mux[] = {
TPU3TO2_MARK,
};
static const unsigned int tpu3_to3_pins[] = {
/* TO */
53,
};
static const unsigned int tpu3_to3_mux[] = {
TPU3TO3_MARK,
};
/* - TPU4 ------------------------------------------------------------------- */
static const unsigned int tpu4_to0_pins[] = {
/* TO */
241,
};
static const unsigned int tpu4_to0_mux[] = {
TPU4TO0_MARK,
};
static const unsigned int tpu4_to1_pins[] = {
/* TO */
199,
};
static const unsigned int tpu4_to1_mux[] = {
TPU4TO1_MARK,
};
static const unsigned int tpu4_to2_pins[] = {
/* TO */
58,
};
static const unsigned int tpu4_to2_mux[] = {
TPU4TO2_MARK,
};
static const unsigned int tpu4_to3_pins[] = {
/* TO */
};
static const unsigned int tpu4_to3_mux[] = {
TPU4TO3_MARK,
};
/* - USB -------------------------------------------------------------------- */
static const unsigned int usb_vbus_pins[] = {
/* VBUS */
@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(tpu0_to0),
SH_PFC_PIN_GROUP(tpu0_to1),
SH_PFC_PIN_GROUP(tpu0_to2),
SH_PFC_PIN_GROUP(tpu0_to3),
SH_PFC_PIN_GROUP(tpu1_to0),
SH_PFC_PIN_GROUP(tpu1_to1_0),
SH_PFC_PIN_GROUP(tpu1_to1_1),
SH_PFC_PIN_GROUP(tpu1_to2),
SH_PFC_PIN_GROUP(tpu1_to3),
SH_PFC_PIN_GROUP(tpu2_to0),
SH_PFC_PIN_GROUP(tpu2_to1),
SH_PFC_PIN_GROUP(tpu2_to2),
SH_PFC_PIN_GROUP(tpu2_to3),
SH_PFC_PIN_GROUP(tpu3_to0),
SH_PFC_PIN_GROUP(tpu3_to1),
SH_PFC_PIN_GROUP(tpu3_to2),
SH_PFC_PIN_GROUP(tpu3_to3),
SH_PFC_PIN_GROUP(tpu4_to0),
SH_PFC_PIN_GROUP(tpu4_to1),
SH_PFC_PIN_GROUP(tpu4_to2),
SH_PFC_PIN_GROUP(tpu4_to3),
SH_PFC_PIN_GROUP(usb_vbus),
};
@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
"usb_vbus",
};
static const char * const tpu0_groups[] = {
"tpu0_to0",
"tpu0_to1",
"tpu0_to2",
"tpu0_to3",
};
static const char * const tpu1_groups[] = {
"tpu1_to0",
"tpu1_to1_0",
"tpu1_to1_1",
"tpu1_to2",
"tpu1_to3",
};
static const char * const tpu2_groups[] = {
"tpu2_to0",
"tpu2_to1",
"tpu2_to2",
"tpu2_to3",
};
static const char * const tpu3_groups[] = {
"tpu3_to0",
"tpu3_to1",
"tpu3_to2",
"tpu3_to3",
};
static const char * const tpu4_groups[] = {
"tpu4_to0",
"tpu4_to1",
"tpu4_to2",
"tpu4_to3",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(bsc),
SH_PFC_FUNCTION(fsia),
@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(tpu0),
SH_PFC_FUNCTION(tpu1),
SH_PFC_FUNCTION(tpu2),
SH_PFC_FUNCTION(tpu3),
SH_PFC_FUNCTION(tpu4),
SH_PFC_FUNCTION(usb),
};
#define PINMUX_FN_BASE GPIO_FN_GPI0
static const struct pinmux_func pinmux_func_gpios[] = {
/* Table 25-1 (Functions 0-7) */
GPIO_FN(GPI0),
GPIO_FN(GPI1),
GPIO_FN(GPI2),
GPIO_FN(GPI3),
GPIO_FN(GPI4),
GPIO_FN(GPI5),
GPIO_FN(GPI6),
GPIO_FN(GPI7),
GPIO_FN(GPO7), \
GPIO_FN(MFG0_OUT2),
GPIO_FN(GPO6), \
GPIO_FN(MFG1_OUT2),
GPIO_FN(GPO5), \
GPIO_FN(PORT16_VIO_CKOR),
GPIO_FN(PORT19_VIO_CKO2),
GPIO_FN(GPO0),
GPIO_FN(GPO1),
GPIO_FN(GPO2), \
GPIO_FN(STATUS0),
GPIO_FN(GPO3), \
GPIO_FN(STATUS1),
GPIO_FN(GPO4), \
GPIO_FN(STATUS2),
GPIO_FN(VINT),
GPIO_FN(TCKON),
GPIO_FN(XDVFS1), \
GPIO_FN(MFG0_OUT1), \
GPIO_FN(PORT27_IROUT),
GPIO_FN(XDVFS2), \
GPIO_FN(PORT28_TPU1TO1),
GPIO_FN(SIM_RST), \
GPIO_FN(PORT29_TPU1TO1),
GPIO_FN(SIM_CLK), \
GPIO_FN(PORT30_VIO_CKOR),
GPIO_FN(SIM_D), \
GPIO_FN(PORT31_IROUT),
GPIO_FN(XWUP),
GPIO_FN(VACK),
GPIO_FN(XTAL1L),
GPIO_FN(PORT49_IROUT), \
GPIO_FN(BBIF2_TSYNC2), \
GPIO_FN(TPU2TO2), \
GPIO_FN(BBIF2_TSCK2), \
GPIO_FN(TPU2TO3), \
GPIO_FN(BBIF2_TXD2),
GPIO_FN(TPU3TO3), \
GPIO_FN(TPU3TO2), \
GPIO_FN(TPU0TO0),
GPIO_FN(A0), \
GPIO_FN(BS_),
GPIO_FN(A12), \
GPIO_FN(TPU4TO2),
GPIO_FN(A13), \
GPIO_FN(TPU0TO1),
GPIO_FN(A14), \
GPIO_FN(A15), \
GPIO_FN(A16), \
GPIO_FN(MSIOF0_SS1),
GPIO_FN(A17), \
GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(A18), \
GPIO_FN(MSIOF0_TSCK),
GPIO_FN(A19), \
GPIO_FN(MSIOF0_TXD),
GPIO_FN(A20), \
GPIO_FN(MSIOF0_RSCK),
GPIO_FN(A21), \
GPIO_FN(MSIOF0_RSYNC),
GPIO_FN(A22), \
GPIO_FN(MSIOF0_MCK0),
GPIO_FN(A23), \
GPIO_FN(MSIOF0_MCK1),
GPIO_FN(A24), \
GPIO_FN(MSIOF0_RXD),
GPIO_FN(A25), \
GPIO_FN(MSIOF0_SS2),
GPIO_FN(A26), \
GPIO_FN(FCE1_),
GPIO_FN(DACK0),
GPIO_FN(FCE0_), \
GPIO_FN(WAIT_), \
GPIO_FN(DREQ0),
GPIO_FN(FRB),
GPIO_FN(CKO),
GPIO_FN(NBRSTOUT_),
GPIO_FN(NBRST_),
GPIO_FN(BBIF2_TXD),
GPIO_FN(BBIF2_RXD),
GPIO_FN(BBIF2_SYNC),
GPIO_FN(BBIF2_SCK),
GPIO_FN(MFG3_IN2),
GPIO_FN(MFG3_IN1),
GPIO_FN(BBIF1_SS2), \
GPIO_FN(MFG3_OUT1),
GPIO_FN(HSI_RX_DATA), \
GPIO_FN(BBIF1_RXD),
GPIO_FN(HSI_TX_WAKE), \
GPIO_FN(BBIF1_TSCK),
GPIO_FN(HSI_TX_DATA), \
GPIO_FN(BBIF1_TSYNC),
GPIO_FN(HSI_TX_READY), \
GPIO_FN(BBIF1_TXD),
GPIO_FN(HSI_RX_READY), \
GPIO_FN(BBIF1_RSCK), \
GPIO_FN(HSI_RX_WAKE), \
GPIO_FN(BBIF1_RSYNC), \
GPIO_FN(HSI_RX_FLAG), \
GPIO_FN(BBIF1_SS1), \
GPIO_FN(BBIF1_FLOW),
GPIO_FN(HSI_TX_FLAG),
GPIO_FN(VIO_VD), \
GPIO_FN(VIO2_VD), \
GPIO_FN(VIO_HD), \
GPIO_FN(VIO2_HD), \
GPIO_FN(VIO_D0), \
GPIO_FN(PORT130_MSIOF2_RXD), \
GPIO_FN(VIO_D1), \
GPIO_FN(PORT131_MSIOF2_SS1), \
GPIO_FN(VIO_D2), \
GPIO_FN(PORT132_MSIOF2_SS2), \
GPIO_FN(VIO_D3), \
GPIO_FN(MSIOF2_TSYNC), \
GPIO_FN(VIO_D4), \
GPIO_FN(MSIOF2_TXD), \
GPIO_FN(VIO_D5), \
GPIO_FN(MSIOF2_TSCK), \
GPIO_FN(VIO_D6), \
GPIO_FN(VIO_D7), \
GPIO_FN(VIO_D8), \
GPIO_FN(VIO2_D0), \
GPIO_FN(VIO_D9), \
GPIO_FN(VIO2_D1), \
GPIO_FN(VIO_D10), \
GPIO_FN(TPU0TO2), \
GPIO_FN(VIO2_D2), \
GPIO_FN(VIO_D11), \
GPIO_FN(TPU0TO3), \
GPIO_FN(VIO2_D3), \
GPIO_FN(VIO_D12), \
GPIO_FN(VIO2_D4), \
GPIO_FN(VIO_D13), \
GPIO_FN(VIO2_D5), \
GPIO_FN(VIO_D14), \
GPIO_FN(VIO2_D6), \
GPIO_FN(VIO_D15), \
GPIO_FN(TPU1TO3), \
GPIO_FN(VIO2_D7), \
GPIO_FN(VIO_CLK), \
GPIO_FN(VIO2_CLK), \
GPIO_FN(VIO_FIELD), \
GPIO_FN(VIO2_FIELD), \
GPIO_FN(VIO_CKO),
GPIO_FN(A27), \
GPIO_FN(MFG0_IN1), \
GPIO_FN(MFG0_IN2),
GPIO_FN(TS_SPSYNC3), \
GPIO_FN(MSIOF2_RSCK),
GPIO_FN(TS_SDAT3), \
GPIO_FN(MSIOF2_RSYNC),
GPIO_FN(TPU1TO2), \
GPIO_FN(TS_SDEN3), \
GPIO_FN(PORT153_MSIOF2_SS1),
GPIO_FN(MSIOF2_MCK0),
GPIO_FN(MSIOF2_MCK1),
GPIO_FN(PORT156_MSIOF2_SS2),
GPIO_FN(PORT157_MSIOF2_RXD),
GPIO_FN(DINT_), \
GPIO_FN(TS_SCK3),
GPIO_FN(NMI),
GPIO_FN(TPU3TO0),
GPIO_FN(BBIF2_TSYNC1),
GPIO_FN(BBIF2_TSCK1),
GPIO_FN(BBIF2_TXD1),
GPIO_FN(MFG2_OUT2), \
GPIO_FN(TPU2TO1),
GPIO_FN(TPU4TO1), \
GPIO_FN(MFG4_OUT2),
GPIO_FN(D16),
GPIO_FN(D17),
GPIO_FN(D18),
GPIO_FN(D19),
GPIO_FN(D20),
GPIO_FN(D21),
GPIO_FN(D22),
GPIO_FN(PORT207_MSIOF0L_SS1), \
GPIO_FN(D23),
GPIO_FN(PORT208_MSIOF0L_SS2), \
GPIO_FN(D24),
GPIO_FN(D25),
GPIO_FN(DREQ2), \
GPIO_FN(PORT210_MSIOF0L_SS1), \
GPIO_FN(D26),
GPIO_FN(PORT211_MSIOF0L_SS2), \
GPIO_FN(D27),
GPIO_FN(TS_SPSYNC1), \
GPIO_FN(MSIOF0L_MCK0), \
GPIO_FN(D28),
GPIO_FN(TS_SDAT1), \
GPIO_FN(MSIOF0L_MCK1), \
GPIO_FN(D29),
GPIO_FN(TS_SDEN1), \
GPIO_FN(MSIOF0L_RSCK), \
GPIO_FN(D30),
GPIO_FN(TS_SCK1), \
GPIO_FN(MSIOF0L_RSYNC), \
GPIO_FN(D31),
GPIO_FN(DACK2), \
GPIO_FN(MSIOF0L_TSYNC), \
GPIO_FN(VIO2_FIELD3), \
GPIO_FN(DACK3), \
GPIO_FN(PORT218_VIO_CKOR),
GPIO_FN(DREQ3), \
GPIO_FN(MSIOF0L_TSCK), \
GPIO_FN(VIO2_CLK3), \
GPIO_FN(DREQ1), \
GPIO_FN(PWEN), \
GPIO_FN(MSIOF0L_RXD), \
GPIO_FN(VIO2_HD3), \
GPIO_FN(DACK1), \
GPIO_FN(OVCN), \
GPIO_FN(MSIOF0L_TXD), \
GPIO_FN(VIO2_VD3), \
GPIO_FN(OVCN2),
GPIO_FN(EXTLP), \
GPIO_FN(PORT226_VIO_CKO2),
GPIO_FN(IDIN),
GPIO_FN(MFG1_IN1),
GPIO_FN(MSIOF1_TXD), \
GPIO_FN(MSIOF1_TSYNC), \
GPIO_FN(MSIOF1_TSCK), \
GPIO_FN(MSIOF1_RXD), \
GPIO_FN(MSIOF1_RSCK), \
GPIO_FN(VIO2_CLK2), \
GPIO_FN(MSIOF1_RSYNC), \
GPIO_FN(MFG1_IN2), \
GPIO_FN(VIO2_VD2), \
GPIO_FN(MSIOF1_MCK0), \
GPIO_FN(MSIOF1_MCK1), \
GPIO_FN(MSIOF1_SS1), \
GPIO_FN(VIO2_FIELD2), \
GPIO_FN(MSIOF1_SS2), \
GPIO_FN(VIO2_HD2), \
GPIO_FN(PORT241_IROUT), \
GPIO_FN(MFG4_OUT1), \
GPIO_FN(TPU4TO0),
GPIO_FN(MFG4_IN2),
GPIO_FN(PORT243_VIO_CKO2),
GPIO_FN(MFG2_IN1), \
GPIO_FN(MSIOF2R_RXD),
GPIO_FN(MFG2_IN2), \
GPIO_FN(MSIOF2R_TXD),
GPIO_FN(MFG1_OUT1), \
GPIO_FN(TPU1TO0),
GPIO_FN(MFG3_OUT2), \
GPIO_FN(TPU3TO1),
GPIO_FN(MFG2_OUT1), \
GPIO_FN(TPU2TO0), \
GPIO_FN(MSIOF2R_TSCK),
GPIO_FN(PORT249_IROUT), \
GPIO_FN(MFG4_IN1), \
GPIO_FN(MSIOF2R_TSYNC),
GPIO_FN(SDHICLK0),
GPIO_FN(SDHICD0),
GPIO_FN(SDHID0_0),
GPIO_FN(SDHID0_1),
GPIO_FN(SDHID0_2),
GPIO_FN(SDHID0_3),
GPIO_FN(SDHICMD0),
GPIO_FN(SDHIWP0),
GPIO_FN(SDHICLK1),
GPIO_FN(SDHID1_0), \
GPIO_FN(TS_SPSYNC2),
GPIO_FN(SDHID1_1), \
GPIO_FN(TS_SDAT2),
GPIO_FN(SDHID1_2), \
GPIO_FN(TS_SDEN2),
GPIO_FN(SDHID1_3), \
GPIO_FN(TS_SCK2),
GPIO_FN(SDHICMD1),
GPIO_FN(SDHICLK2),
GPIO_FN(SDHID2_0), \
GPIO_FN(TS_SPSYNC4),
GPIO_FN(SDHID2_1), \
GPIO_FN(TS_SDAT4),
GPIO_FN(SDHID2_2), \
GPIO_FN(TS_SDEN4),
GPIO_FN(SDHID2_3), \
GPIO_FN(TS_SCK4),
GPIO_FN(SDHICMD2),
GPIO_FN(MMCCLK0),
GPIO_FN(MMCD0_0),
GPIO_FN(MMCD0_1),
GPIO_FN(MMCD0_2),
GPIO_FN(MMCD0_3),
GPIO_FN(MMCD0_4), \
GPIO_FN(TS_SPSYNC5),
GPIO_FN(MMCD0_5), \
GPIO_FN(TS_SDAT5),
GPIO_FN(MMCD0_6), \
GPIO_FN(TS_SDEN5),
GPIO_FN(MMCD0_7), \
GPIO_FN(TS_SCK5),
GPIO_FN(MMCCMD0),
GPIO_FN(RESETOUTS_), \
GPIO_FN(EXTAL2OUT),
GPIO_FN(MCP_WAIT__MCP_FRB),
GPIO_FN(MCP_CKO), \
GPIO_FN(MMCCLK1),
GPIO_FN(MCP_D15_MCP_NAF15),
GPIO_FN(MCP_D14_MCP_NAF14),
GPIO_FN(MCP_D13_MCP_NAF13),
GPIO_FN(MCP_D12_MCP_NAF12),
GPIO_FN(MCP_D11_MCP_NAF11),
GPIO_FN(MCP_D10_MCP_NAF10),
GPIO_FN(MCP_D9_MCP_NAF9),
GPIO_FN(MCP_D8_MCP_NAF8), \
GPIO_FN(MMCCMD1),
GPIO_FN(MCP_D7_MCP_NAF7), \
GPIO_FN(MMCD1_7),
GPIO_FN(MCP_D6_MCP_NAF6), \
GPIO_FN(MMCD1_6),
GPIO_FN(MCP_D5_MCP_NAF5), \
GPIO_FN(MMCD1_5),
GPIO_FN(MCP_D4_MCP_NAF4), \
GPIO_FN(MMCD1_4),
GPIO_FN(MCP_D3_MCP_NAF3), \
GPIO_FN(MMCD1_3),
GPIO_FN(MCP_D2_MCP_NAF2), \
GPIO_FN(MMCD1_2),
GPIO_FN(MCP_D1_MCP_NAF1), \
GPIO_FN(MMCD1_1),
GPIO_FN(MCP_D0_MCP_NAF0), \
GPIO_FN(MMCD1_0),
GPIO_FN(MCP_NBRSTOUT_),
GPIO_FN(MCP_WE0__MCP_FWE), \
GPIO_FN(MCP_RDWR_MCP_FWE),
/* MSEL2 special cases */
GPIO_FN(TSIF2_TS_XX1),
GPIO_FN(TSIF2_TS_XX2),
GPIO_FN(TSIF2_TS_XX3),
GPIO_FN(TSIF2_TS_XX4),
GPIO_FN(TSIF2_TS_XX5),
GPIO_FN(TSIF1_TS_XX1),
GPIO_FN(TSIF1_TS_XX2),
GPIO_FN(TSIF1_TS_XX3),
GPIO_FN(TSIF1_TS_XX4),
GPIO_FN(TSIF1_TS_XX5),
GPIO_FN(TSIF0_TS_XX1),
GPIO_FN(TSIF0_TS_XX2),
GPIO_FN(TSIF0_TS_XX3),
GPIO_FN(TSIF0_TS_XX4),
GPIO_FN(TSIF0_TS_XX5),
GPIO_FN(MST1_TS_XX1),
GPIO_FN(MST1_TS_XX2),
GPIO_FN(MST1_TS_XX3),
GPIO_FN(MST1_TS_XX4),
GPIO_FN(MST1_TS_XX5),
GPIO_FN(MST0_TS_XX1),
GPIO_FN(MST0_TS_XX2),
GPIO_FN(MST0_TS_XX3),
GPIO_FN(MST0_TS_XX4),
GPIO_FN(MST0_TS_XX5),
/* MSEL3 special cases */
GPIO_FN(SDHI0_VCCQ_MC0_ON),
GPIO_FN(SDHI0_VCCQ_MC0_OFF),
GPIO_FN(DEBUG_MON_VIO),
GPIO_FN(DEBUG_MON_LCDD),
GPIO_FN(LCDC_LCDC0),
GPIO_FN(LCDC_LCDC1),
/* MSEL4 special cases */
GPIO_FN(IRQ9_MEM_INT),
GPIO_FN(IRQ9_MCP_INT),
GPIO_FN(A11),
GPIO_FN(TPU4TO3),
GPIO_FN(RESETA_N_PU_ON),
GPIO_FN(RESETA_N_PU_OFF),
GPIO_FN(EDBGREQ_PD),
GPIO_FN(EDBGREQ_PU),
};
#undef PORTCR
#define PORTCR(nr, reg) \
{ \
@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(9), 308),
};
/* -----------------------------------------------------------------------------
* VCCQ MC0 regulator
*/
static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
{
struct sh_pfc *pfc = reg->reg_data;
void __iomem *addr = pfc->window[1].virt + 4;
unsigned long flags;
u32 value;
spin_lock_irqsave(&pfc->lock, flags);
value = ioread32(addr);
if (enable)
value |= BIT(28);
else
value &= ~BIT(28);
iowrite32(value, addr);
spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
{
sh73a0_vccq_mc0_endisable(reg, true);
return 0;
}
static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
{
sh73a0_vccq_mc0_endisable(reg, false);
return 0;
}
static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
{
struct sh_pfc *pfc = reg->reg_data;
void __iomem *addr = pfc->window[1].virt + 4;
unsigned long flags;
u32 value;
spin_lock_irqsave(&pfc->lock, flags);
value = ioread32(addr);
spin_unlock_irqrestore(&pfc->lock, flags);
return !!(value & BIT(28));
}
static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
{
return 3300000;
}
static struct regulator_ops sh73a0_vccq_mc0_ops = {
.enable = sh73a0_vccq_mc0_enable,
.disable = sh73a0_vccq_mc0_disable,
.is_enabled = sh73a0_vccq_mc0_is_enabled,
.get_voltage = sh73a0_vccq_mc0_get_voltage,
};
static const struct regulator_desc sh73a0_vccq_mc0_desc = {
.owner = THIS_MODULE,
.name = "vccq_mc0",
.type = REGULATOR_VOLTAGE,
.ops = &sh73a0_vccq_mc0_ops,
};
static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
};
static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
.consumer_supplies = sh73a0_vccq_mc0_consumers,
};
/* -----------------------------------------------------------------------------
* Pin bias
*/
#define PORTnCR_PULMD_OFF (0 << 6)
#define PORTnCR_PULMD_DOWN (2 << 6)
#define PORTnCR_PULMD_UP (3 << 6)
@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
iowrite8(value, addr);
}
/* -----------------------------------------------------------------------------
* SoC information
*/
struct sh73a0_pinmux_data {
struct regulator_dev *vccq_mc0;
};
static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
{
struct sh73a0_pinmux_data *data;
struct regulator_config cfg = { };
int ret;
data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
cfg.dev = pfc->dev;
cfg.init_data = &sh73a0_vccq_mc0_init_data;
cfg.driver_data = pfc;
data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
if (IS_ERR(data->vccq_mc0)) {
ret = PTR_ERR(data->vccq_mc0);
dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
ret);
return ret;
}
pfc->soc_data = data;
return 0;
}
static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
{
struct sh73a0_pinmux_data *data = pfc->soc_data;
regulator_unregister(data->vccq_mc0);
}
static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
.init = sh73a0_pinmux_soc_init,
.exit = sh73a0_pinmux_soc_exit,
.get_bias = sh73a0_pinmux_get_bias,
.set_bias = sh73a0_pinmux_set_bias,
};
@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

4
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -11,8 +11,8 @@
#ifndef __SH_PFC_H
#define __SH_PFC_H
#include <linux/bug.h>
#include <linux/stringify.h>
#include <asm-generic/gpio.h>
typedef unsigned short pinmux_enum_t;
@ -129,6 +129,8 @@ struct pinmux_range {
struct sh_pfc;
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
void (*exit)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);

5
include/linux/platform_data/gpio-rcar.h
View File

@ -17,10 +17,13 @@
#define __GPIO_RCAR_H__
struct gpio_rcar_config {
unsigned int gpio_base;
int gpio_base;
unsigned int irq_base;
unsigned int number_of_pins;
const char *pctl_name;
unsigned has_both_edge_trigger:1;
};
#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
#endif /* __GPIO_RCAR_H__ */