[media] drxk: add support for Mpeg output clock drive strength config
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
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6e5caf8493
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@ -69,6 +69,7 @@ static struct drxk_config terratec_h7_drxk = {
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.single_master = true,
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.single_master = true,
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.no_i2c_bridge = false,
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.no_i2c_bridge = false,
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.chunk_size = 64,
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.chunk_size = 64,
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.mpeg_out_clk_strength = 0x02,
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.microcode_name = "dvb-usb-terratec-h7-az6007.fw",
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.microcode_name = "dvb-usb-terratec-h7-az6007.fw",
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};
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};
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@ -278,12 +279,10 @@ static int az6007_led_on_off(struct usb_interface *intf, int onoff)
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{
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{
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struct usb_device *udev = interface_to_usbdev(intf);
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struct usb_device *udev = interface_to_usbdev(intf);
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int ret;
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int ret;
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/* TS through */
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/* TS through */
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ret = az6007_write(udev, AZ6007_POWER, onoff, 0, NULL, 0);
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ret = az6007_write(udev, AZ6007_POWER, onoff, 0, NULL, 0);
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if (ret < 0)
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if (ret < 0)
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err("%s failed with error %d", __func__, ret);
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err("%s failed with error %d", __func__, ret);
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return ret;
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return ret;
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}
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}
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@ -17,6 +17,7 @@
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* @antenna_gpio: GPIO bit used to control the antenna
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* @antenna_gpio: GPIO bit used to control the antenna
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* @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
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* @antenna_dvbt: GPIO bit for changing antenna to DVB-C. A value of 1
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* means that 1=DVBC, 0 = DVBT. Zero means the opposite.
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* means that 1=DVBC, 0 = DVBT. Zero means the opposite.
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* @mpeg_out_clk_strength: DRXK Mpeg output clock drive strength.
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* @microcode_name: Name of the firmware file with the microcode
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* @microcode_name: Name of the firmware file with the microcode
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*
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*
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* On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
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* On the *_gpio vars, bit 0 is UIO-1, bit 1 is UIO-2 and bit 2 is
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@ -32,6 +33,7 @@ struct drxk_config {
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bool antenna_dvbt;
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bool antenna_dvbt;
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u16 antenna_gpio;
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u16 antenna_gpio;
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u8 mpeg_out_clk_strength;
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int chunk_size;
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int chunk_size;
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const char *microcode_name;
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const char *microcode_name;
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@ -91,10 +91,6 @@ bool IsA1WithRomCode(struct drxk_state *state)
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#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
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#define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
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#endif
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#endif
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#ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
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#define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
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#endif
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#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
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#define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
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#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
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#define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
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@ -659,7 +655,6 @@ static int init_state(struct drxk_state *state)
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u32 ulGPIOCfg = 0x0113;
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u32 ulGPIOCfg = 0x0113;
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u32 ulInvertTSClock = 0;
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u32 ulInvertTSClock = 0;
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u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
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u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
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u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
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u32 ulDVBTBitrate = 50000000;
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u32 ulDVBTBitrate = 50000000;
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u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
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u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
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@ -820,7 +815,6 @@ static int init_state(struct drxk_state *state)
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state->m_DVBCBitrate = ulDVBCBitrate;
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state->m_DVBCBitrate = ulDVBCBitrate;
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state->m_TSDataStrength = (ulTSDataStrength & 0x07);
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state->m_TSDataStrength = (ulTSDataStrength & 0x07);
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state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
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/* Maximum bitrate in b/s in case static clockrate is selected */
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/* Maximum bitrate in b/s in case static clockrate is selected */
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state->m_mpegTsStaticBitrate = 19392658;
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state->m_mpegTsStaticBitrate = 19392658;
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@ -6394,6 +6388,12 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config,
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state->m_DVBCStaticCLK = 1;
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state->m_DVBCStaticCLK = 1;
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}
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}
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if (config->mpeg_out_clk_strength)
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state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07;
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else
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state->m_TSClockkStrength = 0x06;
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if (config->parallel_ts)
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if (config->parallel_ts)
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state->m_enableParallel = true;
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state->m_enableParallel = true;
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else
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else
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