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Clean up related changes for v3.10 merge window.

Browse Source 
Mostly clock and PM related with removal of now unused
 DMA channel definitions. The clock change to use SoC
 specific lists will make it a little bit easier to
 add support for new SoCs variants without having to patch
 all over the place.
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Merge tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup

From Tony Lindgren <tony@atomide.com>:

Clean up related changes for v3.10 merge window.
Mostly clock and PM related with removal of now unused
DMA channel definitions. The clock change to use SoC
specific lists will make it a little bit easier to
add support for new SoCs variants without having to patch
all over the place.

* tag 'omap-for-v3.10/cleanup-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP4: Fix the init code to have OMAP4460 errata available in DT build
  ARM: OMAP4: PM: Now remove L4 per clockdomain static depedency with MPU
  ARM: OMAP4: PM: Remove L4 wakeup depedency with MPU since errata fix exist now
  ARM: OMAP4+: Move the CPU wakeup prepare code under smp_prepare_cpus()
  ARM: OMAP4+: Remove out of placed smp_wmb() in secondary wakeup code
  ARM: OMAP4+: Remove un-necessary cacheflush in secondary CPU boot path
  ARM: OMAP4+: Remove the un-necessary cache flush from hotplug code
  ARM: OMAP2+: PM: Remove bogus fiq_[enable/disable] tuple
  ARM: OMAP4+: Use common scratchpad SAR RAM offsets for all architectures
  ARM: OMAP2+: Remove unused DMA channel definitions
  ARM: OMAP1: Remove unused DMA channel definitions
  ARM: OMAP2+: clock data: Remove CK_* flags

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-04-08 18:03:08 +02:00
commit 6fa6183aef
18 changed files with 1065 additions and 1197 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
arch/arm/mach-omap1/dma.h
View File

@ -21,21 +21,10 @@
/* DMA channels for omap1 */
#define OMAP_DMA_NO_DEVICE 0
#define OMAP_DMA_MCSI1_TX 1
#define OMAP_DMA_MCSI1_RX 2
#define OMAP_DMA_I2C_RX 3
#define OMAP_DMA_I2C_TX 4
#define OMAP_DMA_EXT_NDMA_REQ 5
#define OMAP_DMA_EXT_NDMA_REQ2 6
#define OMAP_DMA_UWIRE_TX 7
#define OMAP_DMA_MCBSP1_TX 8
#define OMAP_DMA_MCBSP1_RX 9
#define OMAP_DMA_MCBSP3_TX 10
#define OMAP_DMA_MCBSP3_RX 11
#define OMAP_DMA_UART1_TX 12
#define OMAP_DMA_UART1_RX 13
#define OMAP_DMA_UART2_TX 14
#define OMAP_DMA_UART2_RX 15
#define OMAP_DMA_MCBSP2_TX 16
#define OMAP_DMA_MCBSP2_RX 17
#define OMAP_DMA_UART3_TX 18
@ -43,41 +32,11 @@
#define OMAP_DMA_CAMERA_IF_RX 20
#define OMAP_DMA_MMC_TX 21
#define OMAP_DMA_MMC_RX 22
#define OMAP_DMA_NAND 23
#define OMAP_DMA_IRQ_LCD_LINE 24
#define OMAP_DMA_MEMORY_STICK 25
#define OMAP_DMA_USB_W2FC_RX0 26
#define OMAP_DMA_USB_W2FC_RX1 27
#define OMAP_DMA_USB_W2FC_RX2 28
#define OMAP_DMA_USB_W2FC_TX0 29
#define OMAP_DMA_USB_W2FC_TX1 30
#define OMAP_DMA_USB_W2FC_TX2 31
/* These are only for 1610 */
#define OMAP_DMA_CRYPTO_DES_IN 32
#define OMAP_DMA_SPI_TX 33
#define OMAP_DMA_SPI_RX 34
#define OMAP_DMA_CRYPTO_HASH 35
#define OMAP_DMA_CCP_ATTN 36
#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
#define OMAP_DMA_MMC2_TX 54
#define OMAP_DMA_MMC2_RX 55
#define OMAP_DMA_CRYPTO_DES_OUT 56
#endif /* __OMAP1_DMA_CHANNEL_H */

283
arch/arm/mach-omap2/cclock2420_data.c
View File

@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
static struct omap_clk omap2420_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_242X),
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_242X),
CLK(NULL, "osc_ck", &osc_ck, CK_242X),
CLK(NULL, "sys_ck", &sys_ck, CK_242X),
CLK(NULL, "alt_ck", &alt_ck, CK_242X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X),
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_242X),
CLK(NULL, "apll96_ck", &apll96_ck, CK_242X),
CLK(NULL, "apll54_ck", &apll54_ck, CK_242X),
CLK(NULL, "dpll_ck", &dpll_ck),
CLK(NULL, "apll96_ck", &apll96_ck),
CLK(NULL, "apll54_ck", &apll54_ck),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X),
CLK(NULL, "core_ck", &core_ck, CK_242X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X),
CLK(NULL, "emul_ck", &emul_ck, CK_242X),
CLK(NULL, "func_54m_ck", &func_54m_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "func_96m_ck", &func_96m_ck),
CLK(NULL, "func_48m_ck", &func_48m_ck),
CLK(NULL, "func_12m_ck", &func_12m_ck),
CLK(NULL, "sys_clkout_src", &sys_clkout_src),
CLK(NULL, "sys_clkout", &sys_clkout),
CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
CLK(NULL, "sys_clkout2", &sys_clkout2),
CLK(NULL, "emul_ck", &emul_ck),
/* mpu domain clocks */
CLK(NULL, "mpu_ck", &mpu_ck, CK_242X),
CLK(NULL, "mpu_ck", &mpu_ck),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_242X),
CLK(NULL, "dsp_ick", &dsp_ick, CK_242X),
CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
CLK(NULL, "dsp_fck", &dsp_fck),
CLK(NULL, "dsp_ick", &dsp_ick),
CLK(NULL, "iva1_ifck", &iva1_ifck),
CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_242X),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X),
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
CLK(NULL, "gfx_ick", &gfx_ick),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
CLK(NULL, "dss_ick", &dss_ick, CK_242X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
CLK("omapdss_dss", "ick", &dss_ick),
CLK(NULL, "dss_ick", &dss_ick),
CLK(NULL, "dss1_fck", &dss1_fck),
CLK(NULL, "dss2_fck", &dss2_fck),
CLK(NULL, "dss_54m_fck", &dss_54m_fck),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_242X),
CLK(NULL, "core_l3_ck", &core_l3_ck),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_242X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
CLK(NULL, "l4_ck", &l4_ck),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
CLK(NULL, "virt_prcm_set", &virt_prcm_set),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_242X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_242X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_242X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_242X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_242X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_242X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_242X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_242X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_242X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_242X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_242X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_242X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_242X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_242X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_242X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_242X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_242X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_242X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_242X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_242X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_242X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_242X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_242X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_242X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_242X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_242X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_242X),
CLK(NULL, "uart3_ick", &uart3_ick, CK_242X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_242X),
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_242X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
CLK("omap24xxcam", "fck", &cam_fck, CK_242X),
CLK(NULL, "cam_fck", &cam_fck, CK_242X),
CLK("omap24xxcam", "ick", &cam_ick, CK_242X),
CLK(NULL, "cam_ick", &cam_ick, CK_242X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_242X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_242X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_242X),
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X),
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X),
CLK(NULL, "mspro_ick", &mspro_ick, CK_242X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_242X),
CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X),
CLK(NULL, "mmc_ick", &mmc_ick, CK_242X),
CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X),
CLK(NULL, "mmc_fck", &mmc_fck, CK_242X),
CLK(NULL, "fac_ick", &fac_ick, CK_242X),
CLK(NULL, "fac_fck", &fac_fck, CK_242X),
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_242X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_242X),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_242X),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_242X),
CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X),
CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X),
CLK(NULL, "des_ick", &des_ick, CK_242X),
CLK("omap-sham", "ick", &sha_ick, CK_242X),
CLK(NULL, "sha_ick", &sha_ick, CK_242X),
CLK("omap_rng", "ick", &rng_ick, CK_242X),
CLK(NULL, "rng_ick", &rng_ick, CK_242X),
CLK("omap-aes", "ick", &aes_ick, CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_242X),
CLK("musb-hdrc", "fck", &osc_ck, CK_242X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_242X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_242X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_242X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_242X),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpios_ick", &gpios_ick),
CLK(NULL, "gpios_fck", &gpios_fck),
CLK("omap_wdt", "ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
CLK(NULL, "sync_32k_ick", &sync_32k_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK("omap24xxcam", "fck", &cam_fck),
CLK(NULL, "cam_fck", &cam_fck),
CLK("omap24xxcam", "ick", &cam_ick),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "wdt4_ick", &wdt4_ick),
CLK(NULL, "wdt4_fck", &wdt4_fck),
CLK(NULL, "wdt3_ick", &wdt3_ick),
CLK(NULL, "wdt3_fck", &wdt3_fck),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK("mmci-omap.0", "ick", &mmc_ick),
CLK(NULL, "mmc_ick", &mmc_ick),
CLK("mmci-omap.0", "fck", &mmc_fck),
CLK(NULL, "mmc_fck", &mmc_fck),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "fac_fck", &fac_fck),
CLK(NULL, "eac_ick", &eac_ick),
CLK(NULL, "eac_fck", &eac_fck),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap_hdq.0", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "i2c1_fck", &i2c1_fck),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2c2_fck", &i2c2_fck),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "sdma_fck", &sdma_fck),
CLK(NULL, "sdma_ick", &sdma_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "vlynq_ick", &vlynq_ick),
CLK(NULL, "vlynq_fck", &vlynq_fck),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
CLK(NULL, "sha_ick", &sha_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
CLK(NULL, "aes_ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "usb_fck", &usb_fck),
CLK("musb-hdrc", "fck", &osc_ck),
CLK(NULL, "timer_32k_ck", &func_32k_ck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "timer_ext_ck", &alt_ck),
CLK(NULL, "cpufreq_ck", &virt_prcm_set),
};
@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
int __init omap2420_clk_init(void)
{
struct omap_clk *c;
prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
rate_table = omap2420_rate_table;
@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
omap2xxx_clkt_vps_check_bootloader_rates();
for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
omap2xxx_clkt_vps_late_init();

311
arch/arm/mach-omap2/cclock2430_data.c
View File

@ -1840,168 +1840,168 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
static struct omap_clk omap2430_clks[] = {
/* external root sources */
CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
CLK(NULL, "osc_ck", &osc_ck, CK_243X),
CLK("twl", "fck", &osc_ck, CK_243X),
CLK(NULL, "sys_ck", &sys_ck, CK_243X),
CLK(NULL, "alt_ck", &alt_ck, CK_243X),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X),
CLK(NULL, "func_32k_ck", &func_32k_ck),
CLK(NULL, "secure_32k_ck", &secure_32k_ck),
CLK(NULL, "osc_ck", &osc_ck),
CLK("twl", "fck", &osc_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "alt_ck", &alt_ck),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
/* internal analog sources */
CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
CLK(NULL, "dpll_ck", &dpll_ck),
CLK(NULL, "apll96_ck", &apll96_ck),
CLK(NULL, "apll54_ck", &apll54_ck),
/* internal prcm root sources */
CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
CLK(NULL, "core_ck", &core_ck, CK_243X),
CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
CLK(NULL, "emul_ck", &emul_ck, CK_243X),
CLK(NULL, "func_54m_ck", &func_54m_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "func_96m_ck", &func_96m_ck),
CLK(NULL, "func_48m_ck", &func_48m_ck),
CLK(NULL, "func_12m_ck", &func_12m_ck),
CLK(NULL, "sys_clkout_src", &sys_clkout_src),
CLK(NULL, "sys_clkout", &sys_clkout),
CLK(NULL, "emul_ck", &emul_ck),
/* mpu domain clocks */
CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
CLK(NULL, "mpu_ck", &mpu_ck),
/* dsp domain clocks */
CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
CLK(NULL, "dsp_fck", &dsp_fck),
CLK(NULL, "iva2_1_ick", &iva2_1_ick),
/* GFX domain clocks */
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
CLK(NULL, "gfx_ick", &gfx_ick),
/* Modem domain clocks */
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
CLK(NULL, "mdm_ick", &mdm_ick),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
CLK(NULL, "dss_ick", &dss_ick, CK_243X),
CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
CLK("omapdss_dss", "ick", &dss_ick),
CLK(NULL, "dss_ick", &dss_ick),
CLK(NULL, "dss1_fck", &dss1_fck),
CLK(NULL, "dss2_fck", &dss2_fck),
CLK(NULL, "dss_54m_fck", &dss_54m_fck),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
CLK(NULL, "core_l3_ck", &core_l3_ck),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
/* L4 domain clocks */
CLK(NULL, "l4_ck", &l4_ck, CK_243X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
CLK(NULL, "l4_ck", &l4_ck),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
/* virtual meta-group clock */
CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
CLK(NULL, "virt_prcm_set", &virt_prcm_set),
/* general l4 interface ck, multi-parent functional clk */
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_243X),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick, CK_243X),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_243X),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick, CK_243X),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_243X),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_243X),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_243X),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_243X),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick, CK_243X),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
CLK(NULL, "icr_ick", &icr_ick, CK_243X),
CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
CLK(NULL, "cam_fck", &cam_fck, CK_243X),
CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
CLK(NULL, "cam_ick", &cam_ick, CK_243X),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
CLK(NULL, "fac_ick", &fac_ick, CK_243X),
CLK(NULL, "fac_fck", &fac_fck, CK_243X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK(NULL, "hdq_ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
CLK(NULL, "hdq_fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_243X),
CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_243X),
CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
CLK(NULL, "des_ick", &des_ick, CK_243X),
CLK("omap-sham", "ick", &sha_ick, CK_243X),
CLK("omap_rng", "ick", &rng_ick, CK_243X),
CLK(NULL, "rng_ick", &rng_ick, CK_243X),
CLK("omap-aes", "ick", &aes_ick, CK_243X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_243X),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_243X),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck, CK_243X),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck, CK_243X),
CLK(NULL, "timer_32k_ck", &func_32k_ck, CK_243X),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_243X),
CLK(NULL, "timer_ext_ck", &alt_ck, CK_243X),
CLK(NULL, "cpufreq_ck", &virt_prcm_set, CK_243X),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
CLK(NULL, "mcspi3_ick", &mcspi3_ick),
CLK(NULL, "mcspi3_fck", &mcspi3_fck),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpios_ick", &gpios_ick),
CLK(NULL, "gpios_fck", &gpios_fck),
CLK("omap_wdt", "ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
CLK(NULL, "sync_32k_ick", &sync_32k_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK(NULL, "icr_ick", &icr_ick),
CLK("omap24xxcam", "fck", &cam_fck),
CLK(NULL, "cam_fck", &cam_fck),
CLK("omap24xxcam", "ick", &cam_ick),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "wdt4_ick", &wdt4_ick),
CLK(NULL, "wdt4_fck", &wdt4_fck),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "fac_fck", &fac_fck),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap_hdq.1", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "i2chs1_fck", &i2chs1_fck),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2chs2_fck", &i2chs2_fck),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "sdma_fck", &sdma_fck),
CLK(NULL, "sdma_ick", &sdma_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "des_ick", &des_ick),
CLK("omap-sham", "ick", &sha_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "rng_ick", &rng_ick),
CLK("omap-aes", "ick", &aes_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "usb_fck", &usb_fck),
CLK("musb-omap2430", "ick", &usbhs_ick),
CLK(NULL, "usbhs_ick", &usbhs_ick),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
CLK(NULL, "mmchs1_ick", &mmchs1_ick),
CLK(NULL, "mmchs1_fck", &mmchs1_fck),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
CLK(NULL, "mmchs2_ick", &mmchs2_ick),
CLK(NULL, "mmchs2_fck", &mmchs2_fck),
CLK(NULL, "gpio5_ick", &gpio5_ick),
CLK(NULL, "gpio5_fck", &gpio5_fck),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
CLK(NULL, "timer_32k_ck", &func_32k_ck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "timer_ext_ck", &alt_ck),
CLK(NULL, "cpufreq_ck", &virt_prcm_set),
};
static const char *enable_init_clks[] = {
@ -2019,8 +2019,6 @@ static const char *enable_init_clks[] = {
int __init omap2430_clk_init(void)
{
struct omap_clk *c;
prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
rate_table = omap2430_rate_table;
@ -2029,12 +2027,7 @@ int __init omap2430_clk_init(void)
omap2xxx_clkt_vps_check_bootloader_rates();
for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
omap2xxx_clkt_vps_late_init();

163
arch/arm/mach-omap2/cclock33xx_data.c
View File

@ -838,80 +838,80 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
* clkdev
*/
static struct omap_clk am33xx_clks[] = {
CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
CLK(NULL, "clk_32768_ck", &clk_32768_ck),
CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_24000000_ck", &virt_24000000_ck),
CLK(NULL, "virt_25000000_ck", &virt_25000000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
CLK(NULL, "tclkin_ck", &tclkin_ck),
CLK(NULL, "dpll_core_ck", &dpll_core_ck),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck),
CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck),
CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
CLK("cpu0", NULL, &dpll_mpu_ck),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck),
CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck),
CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck),
CLK(NULL, "dpll_disp_ck", &dpll_disp_ck),
CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck),
CLK(NULL, "dpll_per_ck", &dpll_per_ck),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck),
CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck),
CLK(NULL, "adc_tsc_fck", &adc_tsc_fck),
CLK(NULL, "cefuse_fck", &cefuse_fck),
CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck),
CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick),
CLK(NULL, "dcan0_fck", &dcan0_fck),
CLK("481cc000.d_can", NULL, &dcan0_fck),
CLK(NULL, "dcan1_fck", &dcan1_fck),
CLK("481d0000.d_can", NULL, &dcan1_fck),
CLK(NULL, "debugss_ick", &debugss_ick),
CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk),
CLK(NULL, "mcasp0_fck", &mcasp0_fck),
CLK(NULL, "mcasp1_fck", &mcasp1_fck),
CLK(NULL, "mmu_fck", &mmu_fck),
CLK(NULL, "smartreflex0_fck", &smartreflex0_fck),
CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
CLK(NULL, "timer1_fck", &timer1_fck),
CLK(NULL, "timer2_fck", &timer2_fck),
CLK(NULL, "timer3_fck", &timer3_fck),
CLK(NULL, "timer4_fck", &timer4_fck),
CLK(NULL, "timer5_fck", &timer5_fck),
CLK(NULL, "timer6_fck", &timer6_fck),
CLK(NULL, "timer7_fck", &timer7_fck),
CLK(NULL, "usbotg_fck", &usbotg_fck),
CLK(NULL, "ieee5000_fck", &ieee5000_fck),
CLK(NULL, "wdt1_fck", &wdt1_fck),
CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk),
CLK(NULL, "l3_gclk", &l3_gclk),
CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
CLK(NULL, "l4hs_gclk", &l4hs_gclk),
CLK(NULL, "l3s_gclk", &l3s_gclk),
CLK(NULL, "l4fw_gclk", &l4fw_gclk),
CLK(NULL, "l4ls_gclk", &l4ls_gclk),
CLK(NULL, "clk_24mhz", &clk_24mhz),
CLK(NULL, "sysclk_div_ck", &sysclk_div_ck),
CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk),
CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk),
CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck),
CLK(NULL, "gpio0_dbclk", &gpio0_dbclk),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
CLK(NULL, "lcd_gclk", &lcd_gclk),
CLK(NULL, "mmc_clk", &mmc_clk),
CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck),
CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck),
CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck),
CLK(NULL, "clkout2_div_ck", &clkout2_div_ck),
CLK(NULL, "timer_32k_ck", &clkdiv32k_ick),
CLK(NULL, "timer_sys_ck", &sys_clkin_ck),
};
@ -926,21 +926,10 @@ static const char *enable_init_clks[] = {
int __init am33xx_clk_init(void)
{
struct omap_clk *c;
u32 cpu_clkflg;
if (soc_is_am33xx()) {
if (soc_is_am33xx())
cpu_mask = RATE_IN_AM33XX;
cpu_clkflg = CK_AM33XX;
}
for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
omap2_clk_disable_autoidle_all();

699
arch/arm/mach-omap2/cclock3xxx_data.c
View File

@ -3219,289 +3219,325 @@ static struct clk_hw_omap wdt3_ick_hw = {
DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
/*
* clkdev
* clocks specific to omap3430es1
*/
static struct omap_clk omap3430es1_clks[] = {
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
CLK(NULL, "fshostusb_fck", &fshostusb_fck),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
CLK(NULL, "fac_ick", &fac_ick),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
CLK(NULL, "usb_l4_ick", &usb_l4_ick),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
CLK("omapdss_dss", "ick", &dss_ick_3430es1),
CLK(NULL, "dss_ick", &dss_ick_3430es1),
};
/*
* clocks specific to am35xx
*/
static struct omap_clk am35xx_clks[] = {
CLK(NULL, "ipss_ick", &ipss_ick),
CLK(NULL, "rmii_ck", &rmii_ck),
CLK(NULL, "pclk_ck", &pclk_ck),
CLK(NULL, "emac_ick", &emac_ick),
CLK(NULL, "emac_fck", &emac_fck),
CLK("davinci_emac.0", NULL, &emac_ick),
CLK("davinci_mdio.0", NULL, &emac_fck),
CLK("vpfe-capture", "master", &vpfe_ick),
CLK("vpfe-capture", "slave", &vpfe_fck),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
CLK(NULL, "hecc_ck", &hecc_ck),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
};
/*
* clocks specific to omap36xx
*/
static struct omap_clk omap36xx_clks[] = {
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
CLK(NULL, "uart4_fck", &uart4_fck),
};
/*
* clocks common to omap36xx omap34xx
*/
static struct omap_clk omap34xx_omap36xx_clks[] = {
CLK(NULL, "aes1_ick", &aes1_ick),
CLK("omap_rng", "ick", &rng_ick),
CLK(NULL, "sha11_ick", &sha11_ick),
CLK(NULL, "des1_ick", &des1_ick),
CLK(NULL, "cam_mclk", &cam_mclk),
CLK(NULL, "cam_ick", &cam_ick),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
CLK(NULL, "security_l3_ick", &security_l3_ick),
CLK(NULL, "pka_ick", &pka_ick),
CLK(NULL, "icr_ick", &icr_ick),
CLK("omap-aes", "ick", &aes2_ick),
CLK("omap-sham", "ick", &sha12_ick),
CLK(NULL, "des2_ick", &des2_ick),
CLK(NULL, "mspro_ick", &mspro_ick),
CLK(NULL, "mailboxes_ick", &mailboxes_ick),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
CLK(NULL, "sr1_fck", &sr1_fck),
CLK(NULL, "sr2_fck", &sr2_fck),
CLK(NULL, "sr_l4_ick", &sr_l4_ick),
CLK(NULL, "security_l4_ick2", &security_l4_ick2),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
CLK(NULL, "dpll2_fck", &dpll2_fck),
CLK(NULL, "iva2_ck", &iva2_ck),
CLK(NULL, "modem_fck", &modem_fck),
CLK(NULL, "sad2d_ick", &sad2d_ick),
CLK(NULL, "mad2d_ick", &mad2d_ick),
CLK(NULL, "mspro_fck", &mspro_fck),
CLK(NULL, "dpll2_ck", &dpll2_ck),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
};
/*
* clocks common to omap36xx and omap3430es2plus
*/
static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
CLK(NULL, "usim_fck", &usim_fck),
CLK(NULL, "usim_ick", &usim_ick),
};
/*
* clocks common to am35xx omap36xx and omap3430es2plus
*/
static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
CLK(NULL, "dpll5_ck", &dpll5_ck),
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
CLK(NULL, "sgx_fck", &sgx_fck),
CLK(NULL, "sgx_ick", &sgx_ick),
CLK(NULL, "cpefuse_fck", &cpefuse_fck),
CLK(NULL, "ts_fck", &ts_fck),
CLK(NULL, "usbtll_fck", &usbtll_fck),
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck),
CLK("usbhs_tll", "usbtll_fck", &usbtll_fck),
CLK(NULL, "usbtll_ick", &usbtll_ick),
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick),
CLK("usbhs_tll", "usbtll_ick", &usbtll_ick),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
CLK(NULL, "mmchs3_ick", &mmchs3_ick),
CLK(NULL, "mmchs3_fck", &mmchs3_fck),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
CLK("omapdss_dss", "ick", &dss_ick_3430es2),
CLK(NULL, "dss_ick", &dss_ick_3430es2),
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
CLK(NULL, "usbhost_ick", &usbhost_ick),
CLK("usbhs_omap", "usbhost_ick", &usbhost_ick),
};
/*
* common clocks
*/
static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
CLK(NULL, "core_ck", &core_ck, CK_3XXX),
CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
CLK(NULL, "apb_pclk", &dummy_apb_pclk),
CLK(NULL, "omap_32k_fck", &omap_32k_fck),
CLK(NULL, "virt_12m_ck", &virt_12m_ck),
CLK(NULL, "virt_13m_ck", &virt_13m_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
CLK(NULL, "osc_sys_ck", &osc_sys_ck),
CLK("twl", "fck", &osc_sys_ck),
CLK(NULL, "sys_ck", &sys_ck),
CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
CLK(NULL, "sys_altclk", &sys_altclk),
CLK(NULL, "mcbsp_clks", &mcbsp_clks),
CLK(NULL, "sys_clkout1", &sys_clkout1),
CLK(NULL, "dpll1_ck", &dpll1_ck),
CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
CLK(NULL, "dpll3_ck", &dpll3_ck),
CLK(NULL, "core_ck", &core_ck),
CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
CLK(NULL, "dpll4_ck", &dpll4_ck),
CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
CLK(NULL, "omap_96m_fck", &omap_96m_fck),
CLK(NULL, "cm_96m_fck", &cm_96m_fck),
CLK(NULL, "omap_54m_fck", &omap_54m_fck),
CLK(NULL, "omap_48m_fck", &omap_48m_fck),
CLK(NULL, "omap_12m_fck", &omap_12m_fck),
CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
CLK(NULL, "sys_clkout2", &sys_clkout2),
CLK(NULL, "corex2_fck", &corex2_fck),
CLK(NULL, "dpll1_fck", &dpll1_fck),
CLK(NULL, "mpu_ck", &mpu_ck),
CLK(NULL, "arm_fck", &arm_fck),
CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
CLK(NULL, "l3_ick", &l3_ick),
CLK(NULL, "l4_ick", &l4_ick),
CLK(NULL, "rm_ick", &rm_ick),
CLK(NULL, "gpt10_fck", &gpt10_fck),
CLK(NULL, "gpt11_fck", &gpt11_fck),
CLK(NULL, "core_96m_fck", &core_96m_fck),
CLK(NULL, "mmchs2_fck", &mmchs2_fck),
CLK(NULL, "mmchs1_fck", &mmchs1_fck),
CLK(NULL, "i2c3_fck", &i2c3_fck),
CLK(NULL, "i2c2_fck", &i2c2_fck),
CLK(NULL, "i2c1_fck", &i2c1_fck),
CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
CLK(NULL, "core_48m_fck", &core_48m_fck),
CLK(NULL, "mcspi4_fck", &mcspi4_fck),
CLK(NULL, "mcspi3_fck", &mcspi3_fck),
CLK(NULL, "mcspi2_fck", &mcspi2_fck),
CLK(NULL, "mcspi1_fck", &mcspi1_fck),
CLK(NULL, "uart2_fck", &uart2_fck),
CLK(NULL, "uart1_fck", &uart1_fck),
CLK(NULL, "core_12m_fck", &core_12m_fck),
CLK("omap_hdq.0", "fck", &hdq_fck),
CLK(NULL, "hdq_fck", &hdq_fck),
CLK(NULL, "core_l3_ick", &core_l3_ick),
CLK(NULL, "sdrc_ick", &sdrc_ick),
CLK(NULL, "gpmc_fck", &gpmc_fck),
CLK(NULL, "core_l4_ick", &core_l4_ick),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
CLK(NULL, "mmchs2_ick", &mmchs2_ick),
CLK(NULL, "mmchs1_ick", &mmchs1_ick),
CLK("omap_hdq.0", "ick", &hdq_ick),
CLK(NULL, "hdq_ick", &hdq_ick),
CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
CLK(NULL, "mcspi4_ick", &mcspi4_ick),
CLK(NULL, "mcspi3_ick", &mcspi3_ick),
CLK(NULL, "mcspi2_ick", &mcspi2_ick),
CLK(NULL, "mcspi1_ick", &mcspi1_ick),
CLK("omap_i2c.3", "ick", &i2c3_ick),
CLK("omap_i2c.2", "ick", &i2c2_ick),
CLK("omap_i2c.1", "ick", &i2c1_ick),
CLK(NULL, "i2c3_ick", &i2c3_ick),
CLK(NULL, "i2c2_ick", &i2c2_ick),
CLK(NULL, "i2c1_ick", &i2c1_ick),
CLK(NULL, "uart2_ick", &uart2_ick),
CLK(NULL, "uart1_ick", &uart1_ick),
CLK(NULL, "gpt11_ick", &gpt11_ick),
CLK(NULL, "gpt10_ick", &gpt10_ick),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
CLK(NULL, "omapctrl_ick", &omapctrl_ick),
CLK(NULL, "dss_tv_fck", &dss_tv_fck),
CLK(NULL, "dss_96m_fck", &dss_96m_fck),
CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
CLK(NULL, "utmi_p1_gfclk", &dummy_ck),
CLK(NULL, "utmi_p2_gfclk", &dummy_ck),
CLK(NULL, "xclk60mhsp1_ck", &dummy_ck),
CLK(NULL, "xclk60mhsp2_ck", &dummy_ck),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck),
CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck),
CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck),
CLK(NULL, "init_60m_fclk", &dummy_ck),
CLK(NULL, "gpt1_fck", &gpt1_fck),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
CLK(NULL, "gpio1_dbck", &gpio1_dbck),
CLK(NULL, "wdt2_fck", &wdt2_fck),
CLK("omap_wdt", "ick", &wdt2_ick),
CLK(NULL, "wdt2_ick", &wdt2_ick),
CLK(NULL, "wdt1_ick", &wdt1_ick),
CLK(NULL, "gpio1_ick", &gpio1_ick),
CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
CLK(NULL, "gpt12_ick", &gpt12_ick),
CLK(NULL, "gpt1_ick", &gpt1_ick),
CLK(NULL, "per_96m_fck", &per_96m_fck),
CLK(NULL, "per_48m_fck", &per_48m_fck),
CLK(NULL, "uart3_fck", &uart3_fck),
CLK(NULL, "gpt2_fck", &gpt2_fck),
CLK(NULL, "gpt3_fck", &gpt3_fck),
CLK(NULL, "gpt4_fck", &gpt4_fck),
CLK(NULL, "gpt5_fck", &gpt5_fck),
CLK(NULL, "gpt6_fck", &gpt6_fck),
CLK(NULL, "gpt7_fck", &gpt7_fck),
CLK(NULL, "gpt8_fck", &gpt8_fck),
CLK(NULL, "gpt9_fck", &gpt9_fck),
CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
CLK(NULL, "gpio6_dbck", &gpio6_dbck),
CLK(NULL, "gpio5_dbck", &gpio5_dbck),
CLK(NULL, "gpio4_dbck", &gpio4_dbck),
CLK(NULL, "gpio3_dbck", &gpio3_dbck),
CLK(NULL, "gpio2_dbck", &gpio2_dbck),
CLK(NULL, "wdt3_fck", &wdt3_fck),
CLK(NULL, "per_l4_ick", &per_l4_ick),
CLK(NULL, "gpio6_ick", &gpio6_ick),
CLK(NULL, "gpio5_ick", &gpio5_ick),
CLK(NULL, "gpio4_ick", &gpio4_ick),
CLK(NULL, "gpio3_ick", &gpio3_ick),
CLK(NULL, "gpio2_ick", &gpio2_ick),
CLK(NULL, "wdt3_ick", &wdt3_ick),
CLK(NULL, "uart3_ick", &uart3_ick),
CLK(NULL, "uart4_ick", &uart4_ick),
CLK(NULL, "gpt9_ick", &gpt9_ick),
CLK(NULL, "gpt8_ick", &gpt8_ick),
CLK(NULL, "gpt7_ick", &gpt7_ick),
CLK(NULL, "gpt6_ick", &gpt6_ick),
CLK(NULL, "gpt5_ick", &gpt5_ick),
CLK(NULL, "gpt4_ick", &gpt4_ick),
CLK(NULL, "gpt3_ick", &gpt3_ick),
CLK(NULL, "gpt2_ick", &gpt2_ick),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
CLK(NULL, "mcbsp4_ick", &mcbsp2_ick),
CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
CLK(NULL, "mcbsp2_ick", &mcbsp4_ick),
CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
CLK("etb", "emu_src_ck", &emu_src_ck),
CLK(NULL, "emu_src_ck", &emu_src_ck),
CLK(NULL, "pclk_fck", &pclk_fck),
CLK(NULL, "pclkx2_fck", &pclkx2_fck),
CLK(NULL, "atclk_fck", &atclk_fck),
CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
CLK(NULL, "traceclk_fck", &traceclk_fck),
CLK(NULL, "secure_32k_fck", &secure_32k_fck),
CLK(NULL, "gpt12_fck", &gpt12_fck),
CLK(NULL, "wdt1_fck", &wdt1_fck),
CLK(NULL, "timer_32k_ck", &omap_32k_fck),
CLK(NULL, "timer_sys_ck", &sys_ck),
CLK(NULL, "cpufreq_ck", &dpll1_ck),
};
static const char *enable_init_clks[] = {
@ -3512,44 +3548,6 @@ static const char *enable_init_clks[] = {
int __init omap3xxx_clk_init(void)
{
struct omap_clk *c;
u32 cpu_clkflg = 0;
/*
* 3505 must be tested before 3517, since 3517 returns true
* for both AM3517 chips and AM3517 family chips, which
* includes 3505. Unfortunately there's no obvious family
* test for 3517/3505 :-(
*/
if (soc_is_am35xx()) {
cpu_mask = RATE_IN_34XX;
cpu_clkflg = CK_AM35XX;
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
cpu_clkflg = CK_36XX;
} else if (cpu_is_ti816x()) {
cpu_mask = RATE_IN_TI816X;
cpu_clkflg = CK_TI816X;
} else if (soc_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
} else if (cpu_is_ti814x()) {
cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
cpu_clkflg = CK_3430ES1;
} else {
/*
* Assume that anything that we haven't matched yet
* has 3430ES2-type clocks.
*/
cpu_mask = RATE_IN_3430ES2PLUS;
cpu_clkflg = CK_3430ES2PLUS;
}
} else {
WARN(1, "clock: could not identify OMAP3 variant\n");
}
if (omap3_has_192mhz_clk())
omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
@ -3571,15 +3569,62 @@ int __init omap3xxx_clk_init(void)
else
dpll4_dd = dpll4_dd_34xx;
for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
c++)
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
omap2_clk_disable_autoidle_all();
/*
* 3505 must be tested before 3517, since 3517 returns true
* for both AM3517 chips and AM3517 family chips, which
* includes 3505. Unfortunately there's no obvious family
* test for 3517/3505 :-(
*/
if (soc_is_am35xx()) {
cpu_mask = RATE_IN_34XX;
omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (cpu_is_omap3630()) {
cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
omap_clocks_register(omap36xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
} else if (soc_is_am33xx()) {
cpu_mask = RATE_IN_AM33XX;
} else if (cpu_is_ti814x()) {
cpu_mask = RATE_IN_TI814X;
} else if (cpu_is_omap34xx()) {
if (omap_rev() == OMAP3430_REV_ES1_0) {
cpu_mask = RATE_IN_3430ES1;
omap_clocks_register(omap3430es1_clks,
ARRAY_SIZE(omap3430es1_clks));
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap3xxx_clks,
ARRAY_SIZE(omap3xxx_clks));
} else {
/*
* Assume that anything that we haven't matched yet
* has 3430ES2-type clocks.
*/
cpu_mask = RATE_IN_3430ES2PLUS;
omap_clocks_register(omap34xx_omap36xx_clks,
ARRAY_SIZE(omap34xx_omap36xx_clks));
omap_clocks_register(omap36xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
omap_clocks_register(omap3xxx_clks,
ARRAY_SIZE(omap3xxx_clks));
}
} else {
WARN(1, "clock: could not identify OMAP3 variant\n");
}
omap2_clk_disable_autoidle_all();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));

515
arch/arm/mach-omap2/cclock44xx_data.c
View File

@ -1413,283 +1413,284 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
0x0, NULL);
/*
* clkdev
* clocks specific to omap4460
*/
static struct omap_clk omap446x_clks[] = {
CLK(NULL, "div_ts_ck", &div_ts_ck),
CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk),
};
/*
* clocks specific to omap4430
*/
static struct omap_clk omap443x_clks[] = {
CLK(NULL, "bandgap_fclk", &bandgap_fclk),
};
/*
* clocks common to omap44xx
*/
static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck, CK_443X),
CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
CLK(NULL, "slimbus_src_clk", &slimbus_src_clk, CK_443X),
CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
CLK(NULL, "abe_clk", &abe_clk, CK_443X),
CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X),
CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
CLK(NULL, "dss_fck", &dss_fck, CK_443X),
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X),
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X),
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X),
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X),
CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X),
CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X),
CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X),
CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X),
CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X),
CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X),
CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X),
CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X),
CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X),
CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck),
CLK(NULL, "pad_clks_src_ck", &pad_clks_src_ck),
CLK(NULL, "pad_clks_ck", &pad_clks_ck),
CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck),
CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck),
CLK(NULL, "slimbus_src_clk", &slimbus_src_clk),
CLK(NULL, "slimbus_clk", &slimbus_clk),
CLK(NULL, "sys_32k_ck", &sys_32k_ck),
CLK(NULL, "virt_12000000_ck", &virt_12000000_ck),
CLK(NULL, "virt_13000000_ck", &virt_13000000_ck),
CLK(NULL, "virt_16800000_ck", &virt_16800000_ck),
CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
CLK(NULL, "virt_27000000_ck", &virt_27000000_ck),
CLK(NULL, "virt_38400000_ck", &virt_38400000_ck),
CLK(NULL, "sys_clkin_ck", &sys_clkin_ck),
CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck),
CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck),
CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck),
CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck),
CLK(NULL, "xclk60motg_ck", &xclk60motg_ck),
CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck),
CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck),
CLK(NULL, "dpll_abe_ck", &dpll_abe_ck),
CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck),
CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck),
CLK(NULL, "abe_24m_fclk", &abe_24m_fclk),
CLK(NULL, "abe_clk", &abe_clk),
CLK(NULL, "aess_fclk", &aess_fclk),
CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck),
CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck),
CLK(NULL, "dpll_core_ck", &dpll_core_ck),
CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck),
CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck),
CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck),
CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck),
CLK(NULL, "ddrphy_ck", &ddrphy_ck),
CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck),
CLK(NULL, "div_core_ck", &div_core_ck),
CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk),
CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk),
CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck),
CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck),
CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck),
CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck),
CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck),
CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck),
CLK(NULL, "dpll_iva_ck", &dpll_iva_ck),
CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck),
CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck),
CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck),
CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck),
CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck),
CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck),
CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck),
CLK(NULL, "dpll_per_ck", &dpll_per_ck),
CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck),
CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck),
CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck),
CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck),
CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck),
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck),
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck),
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck),
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck),
CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck),
CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck),
CLK(NULL, "func_12m_fclk", &func_12m_fclk),
CLK(NULL, "func_24m_clk", &func_24m_clk),
CLK(NULL, "func_24mc_fclk", &func_24mc_fclk),
CLK(NULL, "func_48m_fclk", &func_48m_fclk),
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk),
CLK(NULL, "func_64m_fclk", &func_64m_fclk),
CLK(NULL, "func_96m_fclk", &func_96m_fclk),
CLK(NULL, "init_60m_fclk", &init_60m_fclk),
CLK(NULL, "l3_div_ck", &l3_div_ck),
CLK(NULL, "l4_div_ck", &l4_div_ck),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck),
CLK("smp_twd", NULL, &mpu_periphclk),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk),
CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck),
CLK(NULL, "aes1_fck", &aes1_fck),
CLK(NULL, "aes2_fck", &aes2_fck),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck),
CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk),
CLK(NULL, "dss_sys_clk", &dss_sys_clk),
CLK(NULL, "dss_tv_clk", &dss_tv_clk),
CLK(NULL, "dss_dss_clk", &dss_dss_clk),
CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk),
CLK(NULL, "dss_fck", &dss_fck),
CLK("omapdss_dss", "ick", &dss_fck),
CLK(NULL, "fdif_fck", &fdif_fck),
CLK(NULL, "gpio1_dbclk", &gpio1_dbclk),
CLK(NULL, "gpio2_dbclk", &gpio2_dbclk),
CLK(NULL, "gpio3_dbclk", &gpio3_dbclk),
CLK(NULL, "gpio4_dbclk", &gpio4_dbclk),
CLK(NULL, "gpio5_dbclk", &gpio5_dbclk),
CLK(NULL, "gpio6_dbclk", &gpio6_dbclk),
CLK(NULL, "sgx_clk_mux", &sgx_clk_mux),
CLK(NULL, "hsi_fck", &hsi_fck),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk),
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck),
CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck),
CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk),
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck),
CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk),
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck),
CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck),
CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk),
CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk),
CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk),
CLK(NULL, "sha2md5_fck", &sha2md5_fck),
CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1),
CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0),
CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2),
CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk),
CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1),
CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0),
CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk),
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck),
CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux),
CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux),
CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux),
CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux),
CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux),
CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux),
CLK(NULL, "timer5_sync_mux", &timer5_sync_mux),
CLK(NULL, "timer6_sync_mux", &timer6_sync_mux),
CLK(NULL, "timer7_sync_mux", &timer7_sync_mux),
CLK(NULL, "timer8_sync_mux", &timer8_sync_mux),
CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux),
CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck),
CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk),
CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk),
CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk),
CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk),
CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk),
CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk),
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk),
CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck),
CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk),
CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick),
CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k),
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk),
CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick),
CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick),
CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick),
CLK(NULL, "usim_ck", &usim_ck),
CLK(NULL, "usim_fclk", &usim_fclk),
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck),
CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck),
CLK(NULL, "auxclk0_ck", &auxclk0_ck),
CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck),
CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck),
CLK(NULL, "auxclk1_ck", &auxclk1_ck),
CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck),
CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck),
CLK(NULL, "auxclk2_ck", &auxclk2_ck),
CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck),
CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck),
CLK(NULL, "auxclk3_ck", &auxclk3_ck),
CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck),
CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck),
CLK(NULL, "auxclk4_ck", &auxclk4_ck),
CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck),
CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
CLK(NULL, "auxclk5_ck", &auxclk5_ck),
CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
CLK("omap-gpmc", "fck", &dummy_ck),
CLK("omap_i2c.1", "ick", &dummy_ck),
CLK("omap_i2c.2", "ick", &dummy_ck),
CLK("omap_i2c.3", "ick", &dummy_ck),
CLK("omap_i2c.4", "ick", &dummy_ck),
CLK(NULL, "mailboxes_ick", &dummy_ck),
CLK("omap_hsmmc.0", "ick", &dummy_ck),
CLK("omap_hsmmc.1", "ick", &dummy_ck),
CLK("omap_hsmmc.2", "ick", &dummy_ck),
CLK("omap_hsmmc.3", "ick", &dummy_ck),
CLK("omap_hsmmc.4", "ick", &dummy_ck),
CLK("omap-mcbsp.1", "ick", &dummy_ck),
CLK("omap-mcbsp.2", "ick", &dummy_ck),
CLK("omap-mcbsp.3", "ick", &dummy_ck),
CLK("omap-mcbsp.4", "ick", &dummy_ck),
CLK("omap2_mcspi.1", "ick", &dummy_ck),
CLK("omap2_mcspi.2", "ick", &dummy_ck),
CLK("omap2_mcspi.3", "ick", &dummy_ck),
CLK("omap2_mcspi.4", "ick", &dummy_ck),
CLK(NULL, "uart1_ick", &dummy_ck),
CLK(NULL, "uart2_ick", &dummy_ck),
CLK(NULL, "uart3_ick", &dummy_ck),
CLK(NULL, "uart4_ick", &dummy_ck),
CLK("usbhs_omap", "usbhost_ick", &dummy_ck),
CLK("usbhs_omap", "usbtll_fck", &dummy_ck),
CLK("usbhs_tll", "usbtll_fck", &dummy_ck),
CLK("omap_wdt", "ick", &dummy_ck),
CLK(NULL, "timer_32k_ck", &sys_32k_ck),
/* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck),
CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck),
CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck),
CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck),
CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck),
CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck),
CLK("40138000.timer", "timer_sys_ck", &syc_clk_div_ck),
CLK("4013a000.timer", "timer_sys_ck", &syc_clk_div_ck),
CLK("4013c000.timer", "timer_sys_ck", &syc_clk_div_ck),
CLK("4013e000.timer", "timer_sys_ck", &syc_clk_div_ck),
CLK(NULL, "cpufreq_ck", &dpll_mpu_ck),
};
int __init omap4xxx_clk_init(void)
{
u32 cpu_clkflg;
struct omap_clk *c;
int rc;
if (cpu_is_omap443x()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
} else if (cpu_is_omap446x() || cpu_is_omap447x()) {
cpu_mask = RATE_IN_4460 | RATE_IN_4430;
cpu_clkflg = CK_446X | CK_443X;
omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
if (cpu_is_omap447x())
pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
} else {
return 0;
}
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
c++) {
if (c->cpu & cpu_clkflg) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
omap2_clk_disable_autoidle_all();

17
arch/arm/mach-omap2/clock.c
View File

@ -23,7 +23,7 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/clk-private.h>
#include <asm/cpu.h>
@ -568,6 +568,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
.find_companion = omap2_clk_dflt_find_companion,
};
/**
* omap_clocks_register - register an array of omap_clk
* @ocs: pointer to an array of omap_clk to register
*/
void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
{
struct omap_clk *c;
for (c = oclks; c < oclks + cnt; c++) {
clkdev_add(&c->lk);
if (!__clk_init(NULL, c->lk.clk))
omap2_init_clk_hw_omap_clocks(c->lk.clk);
}
}
/**
* omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
* @mpurate_ck_name: clk name of the clock to change rate

20
arch/arm/mach-omap2/clock.h
View File

@ -27,9 +27,8 @@ struct omap_clk {
struct clk_lookup lk;
};
#define CLK(dev, con, ck, cp) \
#define CLK(dev, con, ck) \
{ \
.cpu = cp, \
.lk = { \
.dev_id = dev, \
.con_id = con, \
@ -37,22 +36,6 @@ struct omap_clk {
}, \
}
/* Platform flags for the clkdev-OMAP integration code */
#define CK_242X (1 << 0)
#define CK_243X (1 << 1) /* 243x, 253x */
#define CK_3430ES1 (1 << 2) /* 34xxES1 only */
#define CK_3430ES2PLUS (1 << 3) /* 34xxES2, ES3, non-Sitara 35xx only */
#define CK_AM35XX (1 << 4) /* Sitara AM35xx */
#define CK_36XX (1 << 5) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 6)
#define CK_TI816X (1 << 7)
#define CK_446X (1 << 8)
#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
#define CK_3XXX (CK_34XX | CK_AM35XX | CK_36XX)
struct clockdomain;
#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
#endif

3
arch/arm/mach-omap2/cpuidle34xx.c
View File

@ -107,8 +107,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
{
struct omap3_idle_statedata *cx = &omap3_idle_data[index];
local_fiq_disable();
if (omap_irq_pending() || need_resched())
goto return_sleep_time;
@ -143,7 +141,6 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
return_sleep_time:
local_fiq_enable();
return index;
}

7
arch/arm/mach-omap2/cpuidle44xx.c
View File

@ -70,10 +70,7 @@ static int omap4_enter_idle_simple(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
local_fiq_disable();
omap_do_wfi();
local_fiq_enable();
return index;
}
@ -84,8 +81,6 @@ static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
struct omap4_idle_statedata *cx = &omap4_idle_data[index];
int cpu_id = smp_processor_id();
local_fiq_disable();
/*
* CPU0 has to wait and stay ON until CPU1 is OFF state.
* This is necessary to honour hardware recommondation
@ -158,8 +153,6 @@ fail:
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
cpu_done[dev->cpu] = false;
local_fiq_enable();
return index;
}

70
arch/arm/mach-omap2/dma.h
View File

@ -22,69 +22,20 @@
/* DMA channels for 24xx */
#define OMAP24XX_DMA_NO_DEVICE 0
#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
@ -93,33 +44,12 @@
#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
#define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */
#define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */

6
arch/arm/mach-omap2/omap-hotplug.c
View File

@ -19,11 +19,8 @@
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include "omap-wakeupgen.h"
#include "common.h"
#include "powerdomain.h"
/*
@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
unsigned int boot_cpu = 0;
void __iomem *base = omap_get_wakeupgen_base();
flush_cache_all();
dsb();
/*
* we're ready for shutdown now, so do it
*/

57
arch/arm/mach-omap2/omap-smp.c
View File

@ -21,7 +21,6 @@
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <asm/cacheflush.h>
#include <asm/smp_scu.h>
#include "omap-secure.h"
@ -96,9 +95,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
else
__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
flush_cache_all();
smp_wmb();
if (!cpu1_clkdm)
cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@ -161,38 +157,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
return 0;
}
static void __init wakeup_secondary(void)
{
void *startup_addr = omap_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base();
if (cpu_is_omap446x()) {
startup_addr = omap_secondary_startup_4460;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
}
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
smp_wmb();
/*
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb_sev();
mb();
}
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
@ -228,6 +192,8 @@ static void __init omap4_smp_init_cpus(void)
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
{
void *startup_addr = omap_secondary_startup;
void __iomem *base = omap_get_wakeupgen_base();
/*
* Initialise the SCU and wake up the secondary core using
@ -235,7 +201,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
*/
if (scu_base)
scu_enable(scu_base);
wakeup_secondary();
if (cpu_is_omap446x()) {
startup_addr = omap_secondary_startup_4460;
pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
}
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
if (omap_secure_apis_support())
omap_auxcoreboot_addr(virt_to_phys(startup_addr));
else
__raw_writel(virt_to_phys(omap5_secondary_startup),
base + OMAP_AUX_CORE_BOOT_1);
}
struct smp_operations omap4_smp_ops __initdata = {

16
arch/arm/mach-omap2/omap4-common.c
View File

@ -22,6 +22,7 @@
#include <linux/of_platform.h>
#include <linux/export.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_address.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
@ -258,6 +259,21 @@ omap_early_initcall(omap4_sar_ram_init);
void __init omap_gic_of_init(void)
{
struct device_node *np;
/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
if (!cpu_is_omap446x())
goto skip_errata_init;
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
gic_dist_base_addr = of_iomap(np, 0);
WARN_ON(!gic_dist_base_addr);
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
twd_base = of_iomap(np, 0);
WARN_ON(!twd_base);
skip_errata_init:
omap_wakeupgen_init();
irqchip_init();
}

14
arch/arm/mach-omap2/omap4-sar-layout.h
View File

@ -20,13 +20,13 @@
#define SAR_BANK4_OFFSET 0x3000
/* Scratch pad memory offsets from SAR_BANK1 */
#define SCU_OFFSET0 0xd00
#define SCU_OFFSET1 0xd04
#define OMAP_TYPE_OFFSET 0xd10
#define L2X0_SAVE_OFFSET0 0xd14
#define L2X0_SAVE_OFFSET1 0xd18
#define L2X0_AUXCTRL_OFFSET 0xd1c
#define L2X0_PREFETCH_CTRL_OFFSET 0xd20
#define SCU_OFFSET0 0xfe4
#define SCU_OFFSET1 0xfe8
#define OMAP_TYPE_OFFSET 0xfec
#define L2X0_SAVE_OFFSET0 0xff0
#define L2X0_SAVE_OFFSET1 0xff4
#define L2X0_AUXCTRL_OFFSET 0xff8
#define L2X0_PREFETCH_CTRL_OFFSET 0xffc
/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04

11
arch/arm/mach-omap2/pm24xx.c
View File

@ -200,22 +200,17 @@ static int omap2_can_sleep(void)
static void omap2_pm_idle(void)
{
local_fiq_disable();
if (!omap2_can_sleep()) {
if (omap_irq_pending())
goto out;
return;
omap2_enter_mpu_retention();
goto out;
return;
}
if (omap_irq_pending())
goto out;
return;
omap2_enter_full_retention();
out:
local_fiq_enable();
}
static void __init prcm_setup_regs(void)

9
arch/arm/mach-omap2/pm34xx.c
View File

@ -346,19 +346,14 @@ void omap_sram_idle(void)
static void omap3_pm_idle(void)
{
local_fiq_disable();
if (omap_irq_pending())
goto out;
return;
trace_cpu_idle(1, smp_processor_id());
omap_sram_idle();
trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
out:
local_fiq_enable();
}
#ifdef CONFIG_SUSPEND
@ -757,14 +752,12 @@ int __init omap3_pm_init(void)
pr_err("Memory allocation failed when allocating for secure sram context\n");
local_irq_disable();
local_fiq_disable();
omap_dma_global_context_save();
omap3_save_secure_ram_context();
omap_dma_global_context_restore();
local_irq_enable();
local_fiq_enable();
}
omap3_save_scratchpad_contents();

20
arch/arm/mach-omap2/pm44xx.c
View File

@ -131,11 +131,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
*/
static void omap_default_idle(void)
{
local_fiq_disable();
omap_do_wfi();
local_fiq_enable();
}
/**
@ -147,8 +143,8 @@ static void omap_default_idle(void)
int __init omap4_pm_init(void)
{
int ret;
struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
struct clockdomain *ducati_clkdm, *l3_2_clkdm;
if (omap_rev() == OMAP4430_REV_ES1_0) {
WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@ -175,27 +171,19 @@ int __init omap4_pm_init(void)
* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
* expected. The hardware recommendation is to enable static
* dependencies for these to avoid system lock ups or random crashes.
* The L4 wakeup depedency is added to workaround the OCP sync hardware
* BUG with 32K synctimer which lead to incorrect timer value read
* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
* are part of L4 wakeup clockdomain.
*/
mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
emif_clkdm = clkdm_lookup("l3_emif_clkdm");
l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
l4wkup = clkdm_lookup("l4_wkup_clkdm");
ducati_clkdm = clkdm_lookup("ducati_clkdm");
if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
(!l3_2_clkdm) || (!ducati_clkdm))
goto err2;
ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
if (ret) {