leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

serial: 8250_fintek: Add resource check for Fintek F81504/508/512

Browse Source 
Add resource type check for Fintek F81504/508/512, BAR3/4/5 must be
IORESOURCE_IO.

Fintek is trying to make F81504/508/512 works on MMIO interface, but
it's still in progress. We found some issue when the experiment IC
when the BAR3/4/5 is IORESOURCE_MEM. It'll cause wrong operation with
IO resource. So we'll add the resource check for this.

Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ji-Ze Hong (Peter Hong)
2016-12-23 09:41:20 +08:00
committed by Greg Kroah-Hartman
parent 732dbf3a61
commit 6def047c29
1 changed files with 9 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/tty/serial/8250/8250_pci.c
View File

@@ -1477,11 +1477,16 @@ static int pci_fintek_init(struct pci_dev *dev)
{ {
unsigned long iobase; unsigned long iobase;
u32 max_port, i; u32 max_port, i;
u32 bar_data[3]; resource_size_t bar_data[3];
u8 config_base; u8 config_base;
struct serial_private *priv = pci_get_drvdata(dev); struct serial_private *priv = pci_get_drvdata(dev);
struct uart_8250_port *port; struct uart_8250_port *port;
if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
!(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
!(pci_resource_flags(dev, 3) & IORESOURCE_IO))
return -ENODEV;
switch (dev->device) { switch (dev->device) {
case 0x1104: /* 4 ports */ case 0x1104: /* 4 ports */
case 0x1108: /* 8 ports */ case 0x1108: /* 8 ports */
@@ -1495,9 +1500,9 @@ static int pci_fintek_init(struct pci_dev *dev)
} }
/* Get the io address dispatch from the BIOS */ /* Get the io address dispatch from the BIOS */
pci_read_config_dword(dev, 0x24, &bar_data[0]); bar_data[0] = pci_resource_start(dev, 5);
pci_read_config_dword(dev, 0x20, &bar_data[1]); bar_data[1] = pci_resource_start(dev, 4);
pci_read_config_dword(dev, 0x1c, &bar_data[2]); bar_data[2] = pci_resource_start(dev, 3);
for (i = 0; i < max_port; ++i) { for (i = 0; i < max_port; ++i) {
/* UART0 configuration offset start from 0x40 */ /* UART0 configuration offset start from 0x40 */