i2c: mlxcpld: add master driver for mellanox systems
Device driver for Mellanox I2C controller logic, implemented in Lattice CPLD device. Device supports: - Master mode - One physical bus - Polling mode The Kconfig currently controlling compilation of this code is: drivers/i2c/busses/Kconfig:config I2C_MLXCPLD Signed-off-by: Michael Shych <michaelsh@mellanox.com> Signed-off-by: Vadim Pasternak <vadimp@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Vadim Pasternak
Wolfram Sang
parent
254df038e5
commit
6bec23bff9
47
Documentation/i2c/busses/i2c-mlxcpld
Normal file
47
Documentation/i2c/busses/i2c-mlxcpld
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@ -0,0 +1,47 @@
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Driver i2c-mlxcpld
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Author: Michael Shych <michaelsh@mellanox.com>
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This is the Mellanox I2C controller logic, implemented in Lattice CPLD
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device.
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Device supports:
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- Master mode.
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- One physical bus.
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- Polling mode.
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This controller is equipped within the next Mellanox systems:
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"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",
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"msn2740", "msn2100".
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The next transaction types are supported:
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- Receive Byte/Block.
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- Send Byte/Block.
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- Read Byte/Block.
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- Write Byte/Block.
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Registers:
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CTRL 0x1 - control reg.
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Resets all the registers.
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HALF_CYC 0x4 - cycle reg.
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Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
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units).
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I2C_HOLD 0x5 - hold reg.
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OE (output enable) is delayed by value set to this register
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(in LPC_CLK units)
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CMD 0x6 - command reg.
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Bit 0, 0 = write, 1 = read.
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Bits [7:1] - the 7bit Address of the I2C device.
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It should be written last as it triggers an I2C transaction.
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NUM_DATA 0x7 - data size reg.
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Number of data bytes to write in read transaction
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NUM_ADDR 0x8 - address reg.
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Number of address bytes to write in read transaction.
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STATUS 0x9 - status reg.
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Bit 0 - transaction is completed.
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Bit 4 - ACK/NACK.
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DATAx 0xa - 0x54 - 68 bytes data buffer regs.
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For write transaction address is specified in four first bytes
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(DATA1 - DATA4), data starting from DATA4.
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For read transactions address is sent in a separate transaction and
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specified in the four first bytes (DATA0 - DATA3). Data is read
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starting from DATA0.
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@ -7881,12 +7881,14 @@ W: http://www.mellanox.com
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Q: http://patchwork.ozlabs.org/project/netdev/list/
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Q: http://patchwork.ozlabs.org/project/netdev/list/
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F: drivers/net/ethernet/mellanox/mlxsw/
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F: drivers/net/ethernet/mellanox/mlxsw/
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MELLANOX MLXCPLD I2C MUX DRIVER
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MELLANOX MLXCPLD I2C AND MUX DRIVER
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M: Vadim Pasternak <vadimp@mellanox.com>
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M: Vadim Pasternak <vadimp@mellanox.com>
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M: Michael Shych <michaelsh@mellanox.com>
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M: Michael Shych <michaelsh@mellanox.com>
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L: linux-i2c@vger.kernel.org
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L: linux-i2c@vger.kernel.org
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S: Supported
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S: Supported
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F: drivers/i2c/busses/i2c-mlxcpld.c
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F: drivers/i2c/muxes/i2c-mux-mlxcpld.c
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F: drivers/i2c/muxes/i2c-mux-mlxcpld.c
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F: Documentation/i2c/busses/i2c-mlxcpld
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MELLANOX MLXCPLD LED DRIVER
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MELLANOX MLXCPLD LED DRIVER
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M: Vadim Pasternak <vadimp@mellanox.com>
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M: Vadim Pasternak <vadimp@mellanox.com>
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@ -1150,6 +1150,17 @@ config I2C_ELEKTOR
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This support is also available as a module. If so, the module
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This support is also available as a module. If so, the module
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will be called i2c-elektor.
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will be called i2c-elektor.
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config I2C_MLXCPLD
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tristate "Mellanox I2C driver"
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depends on X86_64
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help
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This exposes the Mellanox platform I2C busses to the linux I2C layer
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for X86 based systems.
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Controller is implemented as CPLD logic.
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This driver can also be built as a module. If so, the module will be
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called as i2c-mlxcpld.
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config I2C_PCA_ISA
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config I2C_PCA_ISA
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tristate "PCA9564/PCA9665 on an ISA bus"
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tristate "PCA9564/PCA9665 on an ISA bus"
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depends on ISA
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depends on ISA
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@ -116,6 +116,7 @@ obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
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obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
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obj-$(CONFIG_I2C_BRCMSTB) += i2c-brcmstb.o
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obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
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obj-$(CONFIG_I2C_CROS_EC_TUNNEL) += i2c-cros-ec-tunnel.o
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obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
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obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
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obj-$(CONFIG_I2C_MLXCPLD) += i2c-mlxcpld.o
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obj-$(CONFIG_I2C_OPAL) += i2c-opal.o
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obj-$(CONFIG_I2C_OPAL) += i2c-opal.o
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obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
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obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
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obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
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obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
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504
drivers/i2c/busses/i2c-mlxcpld.c
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504
drivers/i2c/busses/i2c-mlxcpld.c
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@ -0,0 +1,504 @@
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/*
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* Copyright (c) 2016 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2016 Michael Shych <michaels@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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/* General defines */
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#define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR 0x2000
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#define MLXCPLD_I2C_DEVICE_NAME "i2c_mlxcpld"
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#define MLXCPLD_I2C_VALID_FLAG (I2C_M_RECV_LEN | I2C_M_RD)
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#define MLXCPLD_I2C_BUS_NUM 1
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#define MLXCPLD_I2C_DATA_REG_SZ 36
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#define MLXCPLD_I2C_MAX_ADDR_LEN 4
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#define MLXCPLD_I2C_RETR_NUM 2
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#define MLXCPLD_I2C_XFER_TO 500000 /* usec */
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#define MLXCPLD_I2C_POLL_TIME 2000 /* usec */
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/* LPC I2C registers */
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#define MLXCPLD_LPCI2C_LPF_REG 0x0
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#define MLXCPLD_LPCI2C_CTRL_REG 0x1
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#define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
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#define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
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#define MLXCPLD_LPCI2C_CMD_REG 0x6
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#define MLXCPLD_LPCI2C_NUM_DAT_REG 0x7
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#define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
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#define MLXCPLD_LPCI2C_STATUS_REG 0x9
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#define MLXCPLD_LPCI2C_DATA_REG 0xa
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/* LPC I2C masks and parametres */
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#define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
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#define MLXCPLD_LPCI2C_TRANS_END 0x1
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#define MLXCPLD_LPCI2C_STATUS_NACK 0x10
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#define MLXCPLD_LPCI2C_NO_IND 0
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#define MLXCPLD_LPCI2C_ACK_IND 1
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#define MLXCPLD_LPCI2C_NACK_IND 2
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struct mlxcpld_i2c_curr_xfer {
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u8 cmd;
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u8 addr_width;
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u8 data_len;
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u8 msg_num;
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struct i2c_msg *msg;
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};
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struct mlxcpld_i2c_priv {
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struct i2c_adapter adap;
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u32 base_addr;
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struct mutex lock;
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struct mlxcpld_i2c_curr_xfer xfer;
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struct device *dev;
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};
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static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
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{
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int i;
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for (i = 0; i < len - len % 4; i += 4)
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outl(*(u32 *)(data + i), addr + i);
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for (; i < len; ++i)
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outb(*(data + i), addr + i);
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}
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static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
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{
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int i;
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for (i = 0; i < len - len % 4; i += 4)
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*(u32 *)(data + i) = inl(addr + i);
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for (; i < len; ++i)
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*(data + i) = inb(addr + i);
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}
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static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
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u8 *data, u8 datalen)
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{
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u32 addr = priv->base_addr + offs;
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switch (datalen) {
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case 1:
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*(data) = inb(addr);
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break;
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case 2:
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*((u16 *)data) = inw(addr);
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break;
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case 3:
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*((u16 *)data) = inw(addr);
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*(data + 2) = inb(addr + 2);
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break;
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case 4:
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*((u32 *)data) = inl(addr);
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break;
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default:
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mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
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break;
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}
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}
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static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
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u8 *data, u8 datalen)
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{
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u32 addr = priv->base_addr + offs;
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switch (datalen) {
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case 1:
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outb(*(data), addr);
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break;
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case 2:
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outw(*((u16 *)data), addr);
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break;
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case 3:
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outw(*((u16 *)data), addr);
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outb(*(data + 2), addr + 2);
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break;
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case 4:
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outl(*((u32 *)data), addr);
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break;
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default:
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mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
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break;
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}
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}
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/*
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* Check validity of received i2c messages parameters.
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* Returns 0 if OK, other - in case of invalid parameters.
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*/
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static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
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struct i2c_msg *msgs, int num)
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{
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int i;
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if (!num) {
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dev_err(priv->dev, "Incorrect 0 num of messages\n");
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return -EINVAL;
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}
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if (unlikely(msgs[0].addr > 0x7f)) {
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dev_err(priv->dev, "Invalid address 0x%03x\n",
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msgs[0].addr);
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return -EINVAL;
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}
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for (i = 0; i < num; ++i) {
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if (unlikely(!msgs[i].buf)) {
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dev_err(priv->dev, "Invalid buf in msg[%d]\n",
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i);
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return -EINVAL;
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}
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if (unlikely(msgs[0].addr != msgs[i].addr)) {
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dev_err(priv->dev, "Invalid addr in msg[%d]\n",
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i);
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return -EINVAL;
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}
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}
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return 0;
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}
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/*
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* Check if transfer is completed and status of operation.
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* Returns 0 - transfer completed (both ACK or NACK),
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* negative - transfer isn't finished.
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*/
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static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
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{
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u8 val;
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mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
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if (val & MLXCPLD_LPCI2C_TRANS_END) {
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if (val & MLXCPLD_LPCI2C_STATUS_NACK)
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/*
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* The slave is unable to accept the data. No such
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* slave, command not understood, or unable to accept
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* any more data.
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*/
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*status = MLXCPLD_LPCI2C_NACK_IND;
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else
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*status = MLXCPLD_LPCI2C_ACK_IND;
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return 0;
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}
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*status = MLXCPLD_LPCI2C_NO_IND;
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return -EIO;
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}
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static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
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struct i2c_msg *msgs, int num,
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u8 comm_len)
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{
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priv->xfer.msg = msgs;
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priv->xfer.msg_num = num;
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/*
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* All upper layers currently are never use transfer with more than
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* 2 messages. Actually, it's also not so relevant in Mellanox systems
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* because of HW limitation. Max size of transfer is not more than 32
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|
* bytes in the current x86 LPCI2C bridge.
|
||||||
|
*/
|
||||||
|
priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
|
||||||
|
|
||||||
|
if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
|
||||||
|
priv->xfer.addr_width = msgs[0].len;
|
||||||
|
priv->xfer.data_len = comm_len - priv->xfer.addr_width;
|
||||||
|
} else {
|
||||||
|
priv->xfer.addr_width = 0;
|
||||||
|
priv->xfer.data_len = comm_len;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset CPLD LPCI2C block */
|
||||||
|
static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
|
||||||
|
{
|
||||||
|
u8 val;
|
||||||
|
|
||||||
|
mutex_lock(&priv->lock);
|
||||||
|
|
||||||
|
mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
|
||||||
|
val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
|
||||||
|
mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
|
||||||
|
|
||||||
|
mutex_unlock(&priv->lock);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Make sure the CPLD is ready to start transmitting. */
|
||||||
|
static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
|
||||||
|
{
|
||||||
|
u8 val;
|
||||||
|
|
||||||
|
mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
|
||||||
|
|
||||||
|
if (val & MLXCPLD_LPCI2C_TRANS_END)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
|
||||||
|
{
|
||||||
|
int timeout = 0;
|
||||||
|
|
||||||
|
do {
|
||||||
|
if (!mlxcpld_i2c_check_busy(priv))
|
||||||
|
break;
|
||||||
|
usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
|
||||||
|
timeout += MLXCPLD_I2C_POLL_TIME;
|
||||||
|
} while (timeout <= MLXCPLD_I2C_XFER_TO);
|
||||||
|
|
||||||
|
if (timeout > MLXCPLD_I2C_XFER_TO)
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Wait for master transfer to complete.
|
||||||
|
* It puts current process to sleep until we get interrupt or timeout expires.
|
||||||
|
* Returns the number of transferred or read bytes or error (<0).
|
||||||
|
*/
|
||||||
|
static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
|
||||||
|
{
|
||||||
|
int status, i, timeout = 0;
|
||||||
|
u8 datalen;
|
||||||
|
|
||||||
|
do {
|
||||||
|
usleep_range(MLXCPLD_I2C_POLL_TIME / 2, MLXCPLD_I2C_POLL_TIME);
|
||||||
|
if (!mlxcpld_i2c_check_status(priv, &status))
|
||||||
|
break;
|
||||||
|
timeout += MLXCPLD_I2C_POLL_TIME;
|
||||||
|
} while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
|
||||||
|
|
||||||
|
switch (status) {
|
||||||
|
case MLXCPLD_LPCI2C_NO_IND:
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
|
||||||
|
case MLXCPLD_LPCI2C_ACK_IND:
|
||||||
|
if (priv->xfer.cmd != I2C_M_RD)
|
||||||
|
return (priv->xfer.addr_width + priv->xfer.data_len);
|
||||||
|
|
||||||
|
if (priv->xfer.msg_num == 1)
|
||||||
|
i = 0;
|
||||||
|
else
|
||||||
|
i = 1;
|
||||||
|
|
||||||
|
if (!priv->xfer.msg[i].buf)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Actual read data len will be always the same as
|
||||||
|
* requested len. 0xff (line pull-up) will be returned
|
||||||
|
* if slave has no data to return. Thus don't read
|
||||||
|
* MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD.
|
||||||
|
*/
|
||||||
|
datalen = priv->xfer.data_len;
|
||||||
|
|
||||||
|
mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
|
||||||
|
priv->xfer.msg[i].buf, datalen);
|
||||||
|
|
||||||
|
return datalen;
|
||||||
|
|
||||||
|
case MLXCPLD_LPCI2C_NACK_IND:
|
||||||
|
return -ENXIO;
|
||||||
|
|
||||||
|
default:
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
|
||||||
|
{
|
||||||
|
int i, len = 0;
|
||||||
|
u8 cmd;
|
||||||
|
|
||||||
|
mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
|
||||||
|
&priv->xfer.data_len, 1);
|
||||||
|
mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG,
|
||||||
|
&priv->xfer.addr_width, 1);
|
||||||
|
|
||||||
|
for (i = 0; i < priv->xfer.msg_num; i++) {
|
||||||
|
if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
|
||||||
|
/* Don't write to CPLD buffer in read transaction */
|
||||||
|
mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
|
||||||
|
len, priv->xfer.msg[i].buf,
|
||||||
|
priv->xfer.msg[i].len);
|
||||||
|
len += priv->xfer.msg[i].len;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set target slave address with command for master transfer.
|
||||||
|
* It should be latest executed function before CPLD transaction.
|
||||||
|
*/
|
||||||
|
cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
|
||||||
|
mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Generic lpc-i2c transfer.
|
||||||
|
* Returns the number of processed messages or error (<0).
|
||||||
|
*/
|
||||||
|
static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
||||||
|
int num)
|
||||||
|
{
|
||||||
|
struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
|
||||||
|
u8 comm_len = 0;
|
||||||
|
int i, err;
|
||||||
|
|
||||||
|
err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
|
||||||
|
if (err) {
|
||||||
|
dev_err(priv->dev, "Incorrect message\n");
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < num; ++i)
|
||||||
|
comm_len += msgs[i].len;
|
||||||
|
|
||||||
|
/* Check bus state */
|
||||||
|
if (mlxcpld_i2c_wait_for_free(priv)) {
|
||||||
|
dev_err(priv->dev, "LPCI2C bridge is busy\n");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Usually it means something serious has happened.
|
||||||
|
* We can not have unfinished previous transfer
|
||||||
|
* so it doesn't make any sense to try to stop it.
|
||||||
|
* Probably we were not able to recover from the
|
||||||
|
* previous error.
|
||||||
|
* The only reasonable thing - is soft reset.
|
||||||
|
*/
|
||||||
|
mlxcpld_i2c_reset(priv);
|
||||||
|
if (mlxcpld_i2c_check_busy(priv)) {
|
||||||
|
dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
|
||||||
|
|
||||||
|
mutex_lock(&priv->lock);
|
||||||
|
|
||||||
|
/* Do real transfer. Can't fail */
|
||||||
|
mlxcpld_i2c_xfer_msg(priv);
|
||||||
|
|
||||||
|
/* Wait for transaction complete */
|
||||||
|
err = mlxcpld_i2c_wait_for_tc(priv);
|
||||||
|
|
||||||
|
mutex_unlock(&priv->lock);
|
||||||
|
|
||||||
|
return err < 0 ? err : num;
|
||||||
|
}
|
||||||
|
|
||||||
|
static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
|
||||||
|
{
|
||||||
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct i2c_algorithm mlxcpld_i2c_algo = {
|
||||||
|
.master_xfer = mlxcpld_i2c_xfer,
|
||||||
|
.functionality = mlxcpld_i2c_func
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
|
||||||
|
.flags = I2C_AQ_COMB_WRITE_THEN_READ,
|
||||||
|
.max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
|
||||||
|
.max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
|
||||||
|
.max_comb_1st_msg_len = 4,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct i2c_adapter mlxcpld_i2c_adapter = {
|
||||||
|
.owner = THIS_MODULE,
|
||||||
|
.name = "i2c-mlxcpld",
|
||||||
|
.class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
|
||||||
|
.algo = &mlxcpld_i2c_algo,
|
||||||
|
.quirks = &mlxcpld_i2c_quirks,
|
||||||
|
.retries = MLXCPLD_I2C_RETR_NUM,
|
||||||
|
.nr = MLXCPLD_I2C_BUS_NUM,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int mlxcpld_i2c_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct mlxcpld_i2c_priv *priv;
|
||||||
|
int err;
|
||||||
|
|
||||||
|
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||||
|
if (!priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
mutex_init(&priv->lock);
|
||||||
|
platform_set_drvdata(pdev, priv);
|
||||||
|
|
||||||
|
priv->dev = &pdev->dev;
|
||||||
|
|
||||||
|
/* Register with i2c layer */
|
||||||
|
mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
|
||||||
|
priv->adap = mlxcpld_i2c_adapter;
|
||||||
|
priv->adap.dev.parent = &pdev->dev;
|
||||||
|
priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
|
||||||
|
i2c_set_adapdata(&priv->adap, priv);
|
||||||
|
|
||||||
|
err = i2c_add_numbered_adapter(&priv->adap);
|
||||||
|
if (err)
|
||||||
|
mutex_destroy(&priv->lock);
|
||||||
|
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mlxcpld_i2c_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
i2c_del_adapter(&priv->adap);
|
||||||
|
mutex_destroy(&priv->lock);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct platform_driver mlxcpld_i2c_driver = {
|
||||||
|
.probe = mlxcpld_i2c_probe,
|
||||||
|
.remove = mlxcpld_i2c_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = MLXCPLD_I2C_DEVICE_NAME,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
module_platform_driver(mlxcpld_i2c_driver);
|
||||||
|
|
||||||
|
MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
|
||||||
|
MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
|
||||||
|
MODULE_LICENSE("Dual BSD/GPL");
|
||||||
|
MODULE_ALIAS("platform:i2c-mlxcpld");
|
||||||
Loading…
Reference in New Issue
Block a user