drm/tegra: Add eDP support
Add support for eDP functionality found on Tegra124 and later SoCs. Only fast link training is currently supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
64400c3791
commit
6b6b604215
@ -190,6 +190,48 @@ of the following host1x client modules:
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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- sor: serial output resource
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Required properties:
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- compatible: "nvidia,tegra124-sor"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- sor: clock input for the SOR hardware
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- parent: input for the pixel clock
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- dp: reference clock for the SOR clock
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- safe: safe reference for the SOR clock during power up
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- sor
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Optional properties:
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- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
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- nvidia,edid: supplies a binary EDID blob
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- nvidia,panel: phandle of a display panel
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Optional properties when driving an eDP output:
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- nvidia,dpaux: phandle to a DispayPort AUX interface
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- dpaux: DisplayPort AUX interface
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- compatible: "nvidia,tegra124-dpaux"
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- dpaux: clock input for the DPAUX hardware
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- parent: reference clock
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- dpaux
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- vdd-supply: phandle of a supply that powers the DisplayPort link
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Example:
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/ {
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@ -11,6 +11,8 @@ tegra-drm-y := \
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hdmi.o \
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mipi-phy.o \
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dsi.o \
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sor.o \
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dpaux.o \
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gr2d.o \
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gr3d.o
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@ -118,6 +118,7 @@
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DSI_ENABLE (1 << 29)
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#define SOR_ENABLE (1 << 25)
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#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
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#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
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544
drivers/gpu/drm/tegra/dpaux.c
Normal file
544
drivers/gpu/drm/tegra/dpaux.c
Normal file
@ -0,0 +1,544 @@
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/*
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* Copyright (C) 2013 NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/regulator/consumer.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_panel.h>
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#include "dpaux.h"
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#include "drm.h"
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static DEFINE_MUTEX(dpaux_lock);
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static LIST_HEAD(dpaux_list);
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struct tegra_dpaux {
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struct drm_dp_aux aux;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct tegra_output *output;
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struct reset_control *rst;
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struct clk *clk_parent;
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struct clk *clk;
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struct regulator *vdd;
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struct completion complete;
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struct list_head list;
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};
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static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
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{
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return container_of(aux, struct tegra_dpaux, aux);
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}
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static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
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unsigned long offset)
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{
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return readl(dpaux->regs + (offset << 2));
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}
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static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
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unsigned long value,
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unsigned long offset)
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{
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writel(value, dpaux->regs + (offset << 2));
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}
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static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
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size_t size)
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{
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unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
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size_t i, j;
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for (i = 0; i < size; i += 4) {
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size_t num = min_t(size_t, size - i, 4);
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unsigned long value = 0;
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for (j = 0; j < num; j++)
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value |= buffer[i + j] << (j * 8);
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tegra_dpaux_writel(dpaux, value, offset++);
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}
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}
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static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
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size_t size)
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{
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unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
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size_t i, j;
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for (i = 0; i < size; i += 4) {
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size_t num = min_t(size_t, size - i, 4);
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unsigned long value;
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value = tegra_dpaux_readl(dpaux, offset++);
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for (j = 0; j < num; j++)
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buffer[i + j] = value >> (j * 8);
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}
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}
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static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
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struct drm_dp_aux_msg *msg)
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{
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unsigned long value = DPAUX_DP_AUXCTL_TRANSACTREQ;
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unsigned long timeout = msecs_to_jiffies(250);
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struct tegra_dpaux *dpaux = to_dpaux(aux);
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unsigned long status;
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ssize_t ret = 0;
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if (msg->size < 1 || msg->size > 16)
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return -EINVAL;
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tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_I2C_WRITE:
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if (msg->request & DP_AUX_I2C_MOT)
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value = DPAUX_DP_AUXCTL_CMD_MOT_WR;
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else
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value = DPAUX_DP_AUXCTL_CMD_I2C_WR;
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break;
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case DP_AUX_I2C_READ:
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if (msg->request & DP_AUX_I2C_MOT)
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value = DPAUX_DP_AUXCTL_CMD_MOT_RD;
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else
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value = DPAUX_DP_AUXCTL_CMD_I2C_RD;
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break;
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case DP_AUX_I2C_STATUS:
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if (msg->request & DP_AUX_I2C_MOT)
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value = DPAUX_DP_AUXCTL_CMD_MOT_RQ;
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else
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value = DPAUX_DP_AUXCTL_CMD_I2C_RQ;
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break;
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case DP_AUX_NATIVE_WRITE:
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value = DPAUX_DP_AUXCTL_CMD_AUX_WR;
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break;
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case DP_AUX_NATIVE_READ:
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value = DPAUX_DP_AUXCTL_CMD_AUX_RD;
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break;
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default:
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return -EINVAL;
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}
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value |= DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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if ((msg->request & DP_AUX_I2C_READ) == 0) {
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tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
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ret = msg->size;
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}
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/* start transaction */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
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value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
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tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
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status = wait_for_completion_timeout(&dpaux->complete, timeout);
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if (!status)
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return -ETIMEDOUT;
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/* read status and clear errors */
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value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
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tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
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if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
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return -ETIMEDOUT;
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if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
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(value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
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return -EIO;
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switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
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case 0x00:
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msg->reply = DP_AUX_NATIVE_REPLY_ACK;
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break;
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case 0x01:
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msg->reply = DP_AUX_NATIVE_REPLY_NACK;
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break;
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case 0x02:
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msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
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break;
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case 0x04:
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msg->reply = DP_AUX_I2C_REPLY_NACK;
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break;
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case 0x08:
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msg->reply = DP_AUX_I2C_REPLY_DEFER;
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break;
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}
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if (msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
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if (msg->request & DP_AUX_I2C_READ) {
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size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
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if (WARN_ON(count != msg->size))
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count = min_t(size_t, count, msg->size);
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tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
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ret = count;
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}
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}
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return ret;
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}
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static irqreturn_t tegra_dpaux_irq(int irq, void *data)
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{
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struct tegra_dpaux *dpaux = data;
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irqreturn_t ret = IRQ_HANDLED;
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unsigned long value;
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/* clear interrupts */
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value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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if (value & DPAUX_INTR_PLUG_EVENT) {
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if (dpaux->output) {
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drm_helper_hpd_irq_event(dpaux->output->connector.dev);
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}
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}
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if (value & DPAUX_INTR_UNPLUG_EVENT) {
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if (dpaux->output)
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drm_helper_hpd_irq_event(dpaux->output->connector.dev);
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}
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if (value & DPAUX_INTR_IRQ_EVENT) {
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/* TODO: handle this */
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}
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if (value & DPAUX_INTR_AUX_DONE)
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complete(&dpaux->complete);
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return ret;
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}
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static int tegra_dpaux_probe(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux;
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struct resource *regs;
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unsigned long value;
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int err;
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dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
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if (!dpaux)
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return -ENOMEM;
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init_completion(&dpaux->complete);
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INIT_LIST_HEAD(&dpaux->list);
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dpaux->dev = &pdev->dev;
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regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
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if (IS_ERR(dpaux->regs))
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return PTR_ERR(dpaux->regs);
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dpaux->irq = platform_get_irq(pdev, 0);
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if (dpaux->irq < 0) {
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dev_err(&pdev->dev, "failed to get IRQ\n");
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return -ENXIO;
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}
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dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
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if (IS_ERR(dpaux->rst))
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return PTR_ERR(dpaux->rst);
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dpaux->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(dpaux->clk))
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return PTR_ERR(dpaux->clk);
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err = clk_prepare_enable(dpaux->clk);
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if (err < 0)
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return err;
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reset_control_deassert(dpaux->rst);
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dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
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if (IS_ERR(dpaux->clk_parent))
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return PTR_ERR(dpaux->clk_parent);
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err = clk_prepare_enable(dpaux->clk_parent);
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if (err < 0)
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return err;
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err = clk_set_rate(dpaux->clk_parent, 270000000);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
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err);
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return err;
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}
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dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(dpaux->vdd))
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return PTR_ERR(dpaux->vdd);
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err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
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dev_name(dpaux->dev), dpaux);
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if (err < 0) {
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dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
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dpaux->irq, err);
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return err;
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}
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dpaux->aux.transfer = tegra_dpaux_transfer;
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dpaux->aux.dev = &pdev->dev;
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err = drm_dp_aux_register_i2c_bus(&dpaux->aux);
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if (err < 0)
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return err;
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/* enable and clear all interrupts */
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value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
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DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
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tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
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mutex_lock(&dpaux_lock);
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list_add_tail(&dpaux->list, &dpaux_list);
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mutex_unlock(&dpaux_lock);
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platform_set_drvdata(pdev, dpaux);
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return 0;
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}
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static int tegra_dpaux_remove(struct platform_device *pdev)
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{
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struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
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drm_dp_aux_unregister_i2c_bus(&dpaux->aux);
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mutex_lock(&dpaux_lock);
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list_del(&dpaux->list);
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mutex_unlock(&dpaux_lock);
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clk_disable_unprepare(dpaux->clk_parent);
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reset_control_assert(dpaux->rst);
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clk_disable_unprepare(dpaux->clk);
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return 0;
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}
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static const struct of_device_id tegra_dpaux_of_match[] = {
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{ .compatible = "nvidia,tegra124-dpaux", },
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{ },
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};
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struct platform_driver tegra_dpaux_driver = {
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.driver = {
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.name = "tegra-dpaux",
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.of_match_table = tegra_dpaux_of_match,
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},
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.probe = tegra_dpaux_probe,
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.remove = tegra_dpaux_remove,
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};
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struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
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{
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struct tegra_dpaux *dpaux;
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mutex_lock(&dpaux_lock);
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list_for_each_entry(dpaux, &dpaux_list, list)
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if (np == dpaux->dev->of_node) {
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mutex_unlock(&dpaux_lock);
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return dpaux;
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}
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mutex_unlock(&dpaux_lock);
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return NULL;
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}
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int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
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{
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unsigned long timeout;
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int err;
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dpaux->output = output;
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err = regulator_enable(dpaux->vdd);
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if (err < 0)
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return err;
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timeout = jiffies + msecs_to_jiffies(250);
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while (time_before(jiffies, timeout)) {
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enum drm_connector_status status;
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status = tegra_dpaux_detect(dpaux);
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if (status == connector_status_connected)
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
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{
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unsigned long timeout;
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int err;
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|
||||
err = regulator_disable(dpaux->vdd);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
timeout = jiffies + msecs_to_jiffies(250);
|
||||
|
||||
while (time_before(jiffies, timeout)) {
|
||||
enum drm_connector_status status;
|
||||
|
||||
status = tegra_dpaux_detect(dpaux);
|
||||
if (status == connector_status_disconnected) {
|
||||
dpaux->output = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
usleep_range(1000, 2000);
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
|
||||
|
||||
if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
|
||||
return connector_status_connected;
|
||||
|
||||
return connector_status_disconnected;
|
||||
}
|
||||
|
||||
int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
|
||||
DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
|
||||
DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
|
||||
DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
|
||||
DPAUX_HYBRID_PADCTL_MODE_AUX;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
|
||||
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
||||
value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
|
||||
value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
|
||||
tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
|
||||
encoding);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
|
||||
u8 pattern)
|
||||
{
|
||||
u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
|
||||
u8 status[DP_LINK_STATUS_SIZE], values[4];
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
if (tp == DP_TRAINING_PATTERN_DISABLE)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < link->num_lanes; i++)
|
||||
values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
|
||||
DP_TRAIN_PRE_EMPHASIS_0 |
|
||||
DP_TRAIN_MAX_SWING_REACHED |
|
||||
DP_TRAIN_VOLTAGE_SWING_400;
|
||||
|
||||
err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
|
||||
link->num_lanes);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
usleep_range(500, 1000);
|
||||
|
||||
err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
switch (tp) {
|
||||
case DP_TRAINING_PATTERN_1:
|
||||
if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
|
||||
return -EAGAIN;
|
||||
|
||||
break;
|
||||
|
||||
case DP_TRAINING_PATTERN_2:
|
||||
if (!drm_dp_channel_eq_ok(status, link->num_lanes))
|
||||
return -EAGAIN;
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
73
drivers/gpu/drm/tegra/dpaux.h
Normal file
73
drivers/gpu/drm/tegra/dpaux.h
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (C) 2013 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef DRM_TEGRA_DPAUX_H
|
||||
#define DRM_TEGRA_DPAUX_H
|
||||
|
||||
#define DPAUX_CTXSW 0x00
|
||||
|
||||
#define DPAUX_INTR_EN_AUX 0x01
|
||||
#define DPAUX_INTR_AUX 0x05
|
||||
#define DPAUX_INTR_AUX_DONE (1 << 3)
|
||||
#define DPAUX_INTR_IRQ_EVENT (1 << 2)
|
||||
#define DPAUX_INTR_UNPLUG_EVENT (1 << 1)
|
||||
#define DPAUX_INTR_PLUG_EVENT (1 << 0)
|
||||
|
||||
#define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2))
|
||||
#define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2))
|
||||
#define DPAUX_DP_AUXADDR 0x29
|
||||
|
||||
#define DPAUX_DP_AUXCTL 0x2d
|
||||
#define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16)
|
||||
#define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12)
|
||||
#define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff)
|
||||
|
||||
#define DPAUX_DP_AUXSTAT 0x31
|
||||
#define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28)
|
||||
#define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000)
|
||||
#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11)
|
||||
#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10)
|
||||
#define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9)
|
||||
#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8)
|
||||
#define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff)
|
||||
|
||||
#define DPAUX_DP_AUX_SINKSTAT_LO 0x35
|
||||
#define DPAUX_DP_AUX_SINKSTAT_HI 0x39
|
||||
|
||||
#define DPAUX_HPD_CONFIG 0x3d
|
||||
#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16)
|
||||
#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff)
|
||||
|
||||
#define DPAUX_HPD_IRQ_CONFIG 0x41
|
||||
#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff)
|
||||
|
||||
#define DPAUX_DP_AUX_CONFIG 0x45
|
||||
|
||||
#define DPAUX_HYBRID_PADCTL 0x49
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2)
|
||||
#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1)
|
||||
#define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0)
|
||||
#define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0)
|
||||
|
||||
#define DPAUX_HYBRID_SPARE 0x4d
|
||||
#define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0)
|
||||
|
||||
#define DPAUX_SCRATCH_REG0 0x51
|
||||
#define DPAUX_SCRATCH_REG1 0x55
|
||||
#define DPAUX_SCRATCH_REG2 0x59
|
||||
|
||||
#endif
|
||||
@ -665,6 +665,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
|
||||
{ .compatible = "nvidia,tegra114-hdmi", },
|
||||
{ .compatible = "nvidia,tegra114-gr3d", },
|
||||
{ .compatible = "nvidia,tegra124-dc", },
|
||||
{ .compatible = "nvidia,tegra124-sor", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
@ -691,14 +692,22 @@ static int __init host1x_drm_init(void)
|
||||
if (err < 0)
|
||||
goto unregister_dc;
|
||||
|
||||
err = platform_driver_register(&tegra_hdmi_driver);
|
||||
err = platform_driver_register(&tegra_sor_driver);
|
||||
if (err < 0)
|
||||
goto unregister_dsi;
|
||||
|
||||
err = platform_driver_register(&tegra_gr2d_driver);
|
||||
err = platform_driver_register(&tegra_hdmi_driver);
|
||||
if (err < 0)
|
||||
goto unregister_sor;
|
||||
|
||||
err = platform_driver_register(&tegra_dpaux_driver);
|
||||
if (err < 0)
|
||||
goto unregister_hdmi;
|
||||
|
||||
err = platform_driver_register(&tegra_gr2d_driver);
|
||||
if (err < 0)
|
||||
goto unregister_dpaux;
|
||||
|
||||
err = platform_driver_register(&tegra_gr3d_driver);
|
||||
if (err < 0)
|
||||
goto unregister_gr2d;
|
||||
@ -707,8 +716,12 @@ static int __init host1x_drm_init(void)
|
||||
|
||||
unregister_gr2d:
|
||||
platform_driver_unregister(&tegra_gr2d_driver);
|
||||
unregister_dpaux:
|
||||
platform_driver_unregister(&tegra_dpaux_driver);
|
||||
unregister_hdmi:
|
||||
platform_driver_unregister(&tegra_hdmi_driver);
|
||||
unregister_sor:
|
||||
platform_driver_unregister(&tegra_sor_driver);
|
||||
unregister_dsi:
|
||||
platform_driver_unregister(&tegra_dsi_driver);
|
||||
unregister_dc:
|
||||
@ -723,7 +736,9 @@ static void __exit host1x_drm_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_gr3d_driver);
|
||||
platform_driver_unregister(&tegra_gr2d_driver);
|
||||
platform_driver_unregister(&tegra_dpaux_driver);
|
||||
platform_driver_unregister(&tegra_hdmi_driver);
|
||||
platform_driver_unregister(&tegra_sor_driver);
|
||||
platform_driver_unregister(&tegra_dsi_driver);
|
||||
platform_driver_unregister(&tegra_dc_driver);
|
||||
host1x_driver_unregister(&host1x_drm_driver);
|
||||
|
||||
@ -179,12 +179,14 @@ struct tegra_output_ops {
|
||||
int (*check_mode)(struct tegra_output *output,
|
||||
struct drm_display_mode *mode,
|
||||
enum drm_mode_status *status);
|
||||
enum drm_connector_status (*detect)(struct tegra_output *output);
|
||||
};
|
||||
|
||||
enum tegra_output_type {
|
||||
TEGRA_OUTPUT_RGB,
|
||||
TEGRA_OUTPUT_HDMI,
|
||||
TEGRA_OUTPUT_DSI,
|
||||
TEGRA_OUTPUT_EDP,
|
||||
};
|
||||
|
||||
struct tegra_output {
|
||||
@ -265,6 +267,22 @@ extern int tegra_output_remove(struct tegra_output *output);
|
||||
extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
|
||||
extern int tegra_output_exit(struct tegra_output *output);
|
||||
|
||||
/* from dpaux.c */
|
||||
|
||||
struct tegra_dpaux;
|
||||
struct drm_dp_link;
|
||||
struct drm_dp_aux;
|
||||
|
||||
struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np);
|
||||
enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux);
|
||||
int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output);
|
||||
int tegra_dpaux_detach(struct tegra_dpaux *dpaux);
|
||||
int tegra_dpaux_enable(struct tegra_dpaux *dpaux);
|
||||
int tegra_dpaux_disable(struct tegra_dpaux *dpaux);
|
||||
int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding);
|
||||
int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
|
||||
u8 pattern);
|
||||
|
||||
/* from fb.c */
|
||||
struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
|
||||
unsigned int index);
|
||||
@ -278,7 +296,9 @@ extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
|
||||
|
||||
extern struct platform_driver tegra_dc_driver;
|
||||
extern struct platform_driver tegra_dsi_driver;
|
||||
extern struct platform_driver tegra_sor_driver;
|
||||
extern struct platform_driver tegra_hdmi_driver;
|
||||
extern struct platform_driver tegra_dpaux_driver;
|
||||
extern struct platform_driver tegra_gr2d_driver;
|
||||
extern struct platform_driver tegra_gr3d_driver;
|
||||
|
||||
|
||||
@ -77,6 +77,9 @@ tegra_connector_detect(struct drm_connector *connector, bool force)
|
||||
struct tegra_output *output = connector_to_output(connector);
|
||||
enum drm_connector_status status = connector_status_unknown;
|
||||
|
||||
if (output->ops->detect)
|
||||
return output->ops->detect(output);
|
||||
|
||||
if (gpio_is_valid(output->hpd_gpio)) {
|
||||
if (gpio_get_value(output->hpd_gpio) == 0)
|
||||
status = connector_status_disconnected;
|
||||
@ -292,6 +295,11 @@ int tegra_output_init(struct drm_device *drm, struct tegra_output *output)
|
||||
encoder = DRM_MODE_ENCODER_DSI;
|
||||
break;
|
||||
|
||||
case TEGRA_OUTPUT_EDP:
|
||||
connector = DRM_MODE_CONNECTOR_eDP;
|
||||
encoder = DRM_MODE_ENCODER_TMDS;
|
||||
break;
|
||||
|
||||
default:
|
||||
connector = DRM_MODE_CONNECTOR_Unknown;
|
||||
encoder = DRM_MODE_ENCODER_NONE;
|
||||
|
||||
1092
drivers/gpu/drm/tegra/sor.c
Normal file
1092
drivers/gpu/drm/tegra/sor.c
Normal file
File diff suppressed because it is too large
Load Diff
278
drivers/gpu/drm/tegra/sor.h
Normal file
278
drivers/gpu/drm/tegra/sor.h
Normal file
@ -0,0 +1,278 @@
|
||||
/*
|
||||
* Copyright (C) 2013 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef DRM_TEGRA_SOR_H
|
||||
#define DRM_TEGRA_SOR_H
|
||||
|
||||
#define SOR_CTXSW 0x00
|
||||
|
||||
#define SOR_SUPER_STATE_0 0x01
|
||||
|
||||
#define SOR_SUPER_STATE_1 0x02
|
||||
#define SOR_SUPER_STATE_ATTACHED (1 << 3)
|
||||
#define SOR_SUPER_STATE_MODE_NORMAL (1 << 2)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_MASK (3 << 0)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_AWAKE (2 << 0)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_SNOOZE (1 << 0)
|
||||
#define SOR_SUPER_STATE_HEAD_MODE_SLEEP (0 << 0)
|
||||
|
||||
#define SOR_STATE_0 0x03
|
||||
|
||||
#define SOR_STATE_1 0x04
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_MASK (0xf << 17)
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_BPP_18_444 (0x2 << 17)
|
||||
#define SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 (0x5 << 17)
|
||||
#define SOR_STATE_ASY_VSYNCPOL (1 << 13)
|
||||
#define SOR_STATE_ASY_HSYNCPOL (1 << 12)
|
||||
#define SOR_STATE_ASY_PROTOCOL_MASK (0xf << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_CUSTOM (0xf << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_DP_A (0x8 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_DP_B (0x9 << 8)
|
||||
#define SOR_STATE_ASY_PROTOCOL_LVDS (0x0 << 8)
|
||||
#define SOR_STATE_ASY_CRC_MODE_MASK (0x3 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_NON_ACTIVE (0x2 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_COMPLETE (0x1 << 6)
|
||||
#define SOR_STATE_ASY_CRC_MODE_ACTIVE (0x0 << 6)
|
||||
#define SOR_STATE_ASY_OWNER(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define SOR_HEAD_STATE_0(x) (0x05 + (x))
|
||||
#define SOR_HEAD_STATE_1(x) (0x07 + (x))
|
||||
#define SOR_HEAD_STATE_2(x) (0x09 + (x))
|
||||
#define SOR_HEAD_STATE_3(x) (0x0b + (x))
|
||||
#define SOR_HEAD_STATE_4(x) (0x0d + (x))
|
||||
#define SOR_HEAD_STATE_5(x) (0x0f + (x))
|
||||
#define SOR_CRC_CNTRL 0x11
|
||||
#define SOR_DP_DEBUG_MVID 0x12
|
||||
|
||||
#define SOR_CLK_CNTRL 0x13
|
||||
#define SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2)
|
||||
#define SOR_CLK_CNTRL_DP_LINK_SPEED(x) (((x) & 0x1f) << 2)
|
||||
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (0x06 << 2)
|
||||
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70 (0x0a << 2)
|
||||
#define SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40 (0x14 << 2)
|
||||
#define SOR_CLK_CNTRL_DP_CLK_SEL_MASK (3 << 0)
|
||||
#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0 << 0)
|
||||
#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1 << 0)
|
||||
#define SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2 << 0)
|
||||
#define SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3 << 0)
|
||||
|
||||
#define SOR_CAP 0x14
|
||||
|
||||
#define SOR_PWR 0x15
|
||||
#define SOR_PWR_TRIGGER (1 << 31)
|
||||
#define SOR_PWR_MODE_SAFE (1 << 28)
|
||||
#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
|
||||
|
||||
#define SOR_TEST 0x16
|
||||
#define SOR_TEST_ATTACHED (1 << 10)
|
||||
#define SOR_TEST_HEAD_MODE_MASK (3 << 8)
|
||||
#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8)
|
||||
|
||||
#define SOR_PLL_0 0x17
|
||||
#define SOR_PLL_0_ICHPMP_MASK (0xf << 24)
|
||||
#define SOR_PLL_0_ICHPMP(x) (((x) & 0xf) << 24)
|
||||
#define SOR_PLL_0_VCOCAP_MASK (0xf << 8)
|
||||
#define SOR_PLL_0_VCOCAP(x) (((x) & 0xf) << 8)
|
||||
#define SOR_PLL_0_VCOCAP_RST SOR_PLL_0_VCOCAP(3)
|
||||
#define SOR_PLL_0_PLLREG_MASK (0x3 << 6)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL(x) (((x) & 0x3) << 6)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V25 SOR_PLL_0_PLLREG_LEVEL(0)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V15 SOR_PLL_0_PLLREG_LEVEL(1)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V35 SOR_PLL_0_PLLREG_LEVEL(2)
|
||||
#define SOR_PLL_0_PLLREG_LEVEL_V45 SOR_PLL_0_PLLREG_LEVEL(3)
|
||||
#define SOR_PLL_0_PULLDOWN (1 << 5)
|
||||
#define SOR_PLL_0_RESISTOR_EXT (1 << 4)
|
||||
#define SOR_PLL_0_VCOPD (1 << 2)
|
||||
#define SOR_PLL_0_POWER_OFF (1 << 0)
|
||||
|
||||
#define SOR_PLL_1 0x18
|
||||
/* XXX: read-only bit? */
|
||||
#define SOR_PLL_1_TERM_COMPOUT (1 << 15)
|
||||
#define SOR_PLL_1_TMDS_TERM (1 << 8)
|
||||
|
||||
#define SOR_PLL_2 0x19
|
||||
#define SOR_PLL_2_LVDS_ENABLE (1 << 25)
|
||||
#define SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE (1 << 24)
|
||||
#define SOR_PLL_2_PORT_POWERDOWN (1 << 23)
|
||||
#define SOR_PLL_2_BANDGAP_POWERDOWN (1 << 22)
|
||||
#define SOR_PLL_2_POWERDOWN_OVERRIDE (1 << 18)
|
||||
#define SOR_PLL_2_SEQ_PLLCAPPD (1 << 17)
|
||||
|
||||
#define SOR_PLL_3 0x1a
|
||||
#define SOR_PLL_3_PLL_VDD_MODE_V1_8 (0 << 13)
|
||||
#define SOR_PLL_3_PLL_VDD_MODE_V3_3 (1 << 13)
|
||||
|
||||
#define SOR_CSTM 0x1b
|
||||
#define SOR_CSTM_LVDS (1 << 16)
|
||||
#define SOR_CSTM_LINK_ACT_B (1 << 15)
|
||||
#define SOR_CSTM_LINK_ACT_A (1 << 14)
|
||||
#define SOR_CSTM_UPPER (1 << 11)
|
||||
|
||||
#define SOR_LVDS 0x1c
|
||||
#define SOR_CRC_A 0x1d
|
||||
#define SOR_CRC_B 0x1e
|
||||
#define SOR_BLANK 0x1f
|
||||
#define SOR_SEQ_CTL 0x20
|
||||
|
||||
#define SOR_LANE_SEQ_CTL 0x21
|
||||
#define SOR_LANE_SEQ_CTL_TRIGGER (1 << 31)
|
||||
#define SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20)
|
||||
#define SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20)
|
||||
#define SOR_LANE_SEQ_CTL_POWER_STATE_UP (0 << 16)
|
||||
#define SOR_LANE_SEQ_CTL_POWER_STATE_DOWN (1 << 16)
|
||||
|
||||
#define SOR_SEQ_INST(x) (0x22 + (x))
|
||||
|
||||
#define SOR_PWM_DIV 0x32
|
||||
#define SOR_PWM_DIV_MASK 0xffffff
|
||||
|
||||
#define SOR_PWM_CTL 0x33
|
||||
#define SOR_PWM_CTL_TRIGGER (1 << 31)
|
||||
#define SOR_PWM_CTL_CLK_SEL (1 << 30)
|
||||
#define SOR_PWM_CTL_DUTY_CYCLE_MASK 0xffffff
|
||||
|
||||
#define SOR_VCRC_A_0 0x34
|
||||
#define SOR_VCRC_A_1 0x35
|
||||
#define SOR_VCRC_B_0 0x36
|
||||
#define SOR_VCRC_B_1 0x37
|
||||
#define SOR_CCRC_A_0 0x38
|
||||
#define SOR_CCRC_A_1 0x39
|
||||
#define SOR_CCRC_B_0 0x3a
|
||||
#define SOR_CCRC_B_1 0x3b
|
||||
#define SOR_EDATA_A_0 0x3c
|
||||
#define SOR_EDATA_A_1 0x3d
|
||||
#define SOR_EDATA_B_0 0x3e
|
||||
#define SOR_EDATA_B_1 0x3f
|
||||
#define SOR_COUNT_A_0 0x40
|
||||
#define SOR_COUNT_A_1 0x41
|
||||
#define SOR_COUNT_B_0 0x42
|
||||
#define SOR_COUNT_B_1 0x43
|
||||
#define SOR_DEBUG_A_0 0x44
|
||||
#define SOR_DEBUG_A_1 0x45
|
||||
#define SOR_DEBUG_B_0 0x46
|
||||
#define SOR_DEBUG_B_1 0x47
|
||||
#define SOR_TRIG 0x48
|
||||
#define SOR_MSCHECK 0x49
|
||||
#define SOR_XBAR_CTRL 0x4a
|
||||
#define SOR_XBAR_POL 0x4b
|
||||
|
||||
#define SOR_DP_LINKCTL_0 0x4c
|
||||
#define SOR_DP_LINKCTL_LANE_COUNT_MASK (0x1f << 16)
|
||||
#define SOR_DP_LINKCTL_LANE_COUNT(x) (((1 << (x)) - 1) << 16)
|
||||
#define SOR_DP_LINKCTL_ENHANCED_FRAME (1 << 14)
|
||||
#define SOR_DP_LINKCTL_TU_SIZE_MASK (0x7f << 2)
|
||||
#define SOR_DP_LINKCTL_TU_SIZE(x) (((x) & 0x7f) << 2)
|
||||
#define SOR_DP_LINKCTL_ENABLE (1 << 0)
|
||||
|
||||
#define SOR_DP_LINKCTL_1 0x4d
|
||||
|
||||
#define SOR_LANE_DRIVE_CURRENT_0 0x4e
|
||||
#define SOR_LANE_DRIVE_CURRENT_1 0x4f
|
||||
#define SOR_LANE4_DRIVE_CURRENT_0 0x50
|
||||
#define SOR_LANE4_DRIVE_CURRENT_1 0x51
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_DRIVE_CURRENT_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_LANE_PREEMPHASIS_0 0x52
|
||||
#define SOR_LANE_PREEMPHASIS_1 0x53
|
||||
#define SOR_LANE4_PREEMPHASIS_0 0x54
|
||||
#define SOR_LANE4_PREEMPHASIS_1 0x55
|
||||
#define SOR_LANE_PREEMPHASIS_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_PREEMPHASIS_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_LANE_POST_CURSOR_0 0x56
|
||||
#define SOR_LANE_POST_CURSOR_1 0x57
|
||||
#define SOR_LANE_POST_CURSOR_LANE3(x) (((x) & 0xff) << 24)
|
||||
#define SOR_LANE_POST_CURSOR_LANE2(x) (((x) & 0xff) << 16)
|
||||
#define SOR_LANE_POST_CURSOR_LANE1(x) (((x) & 0xff) << 8)
|
||||
#define SOR_LANE_POST_CURSOR_LANE0(x) (((x) & 0xff) << 0)
|
||||
|
||||
#define SOR_DP_CONFIG_0 0x58
|
||||
#define SOR_DP_CONFIG_DISPARITY_NEGATIVE (1 << 31)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_ENABLE (1 << 26)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_POLARITY (1 << 24)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK (0xf << 16)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_FRAC(x) (((x) & 0xf) << 16)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK (0x7f << 8)
|
||||
#define SOR_DP_CONFIG_ACTIVE_SYM_COUNT(x) (((x) & 0x7f) << 8)
|
||||
#define SOR_DP_CONFIG_WATERMARK_MASK (0x3f << 0)
|
||||
#define SOR_DP_CONFIG_WATERMARK(x) (((x) & 0x3f) << 0)
|
||||
|
||||
#define SOR_DP_CONFIG_1 0x59
|
||||
#define SOR_DP_MN_0 0x5a
|
||||
#define SOR_DP_MN_1 0x5b
|
||||
|
||||
#define SOR_DP_PADCTL_0 0x5c
|
||||
#define SOR_DP_PADCTL_PAD_CAL_PD (1 << 23)
|
||||
#define SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22)
|
||||
#define SOR_DP_PADCTL_TX_PU_MASK (0xff << 8)
|
||||
#define SOR_DP_PADCTL_TX_PU(x) (((x) & 0xff) << 8)
|
||||
#define SOR_DP_PADCTL_CM_TXD_3 (1 << 7)
|
||||
#define SOR_DP_PADCTL_CM_TXD_2 (1 << 6)
|
||||
#define SOR_DP_PADCTL_CM_TXD_1 (1 << 5)
|
||||
#define SOR_DP_PADCTL_CM_TXD_0 (1 << 4)
|
||||
#define SOR_DP_PADCTL_PD_TXD_3 (1 << 3)
|
||||
#define SOR_DP_PADCTL_PD_TXD_0 (1 << 2)
|
||||
#define SOR_DP_PADCTL_PD_TXD_1 (1 << 1)
|
||||
#define SOR_DP_PADCTL_PD_TXD_2 (1 << 0)
|
||||
|
||||
#define SOR_DP_PADCTL_1 0x5d
|
||||
|
||||
#define SOR_DP_DEBUG_0 0x5e
|
||||
#define SOR_DP_DEBUG_1 0x5f
|
||||
|
||||
#define SOR_DP_SPARE_0 0x60
|
||||
#define SOR_DP_SPARE_MACRO_SOR_CLK (1 << 2)
|
||||
#define SOR_DP_SPARE_PANEL_INTERNAL (1 << 1)
|
||||
#define SOR_DP_SPARE_SEQ_ENABLE (1 << 0)
|
||||
|
||||
#define SOR_DP_SPARE_1 0x61
|
||||
#define SOR_DP_AUDIO_CTRL 0x62
|
||||
|
||||
#define SOR_DP_AUDIO_HBLANK_SYMBOLS 0x63
|
||||
#define SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x01ffff << 0)
|
||||
|
||||
#define SOR_DP_AUDIO_VBLANK_SYMBOLS 0x64
|
||||
#define SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1fffff << 0)
|
||||
|
||||
#define SOR_DP_GENERIC_INFOFRAME_HEADER 0x65
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_0 0x66
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_1 0x67
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_2 0x68
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_3 0x69
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_4 0x6a
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_5 0x6b
|
||||
#define SOR_DP_GENERIC_INFOFRAME_SUBPACK_6 0x6c
|
||||
|
||||
#define SOR_DP_TPG 0x6d
|
||||
#define SOR_DP_TPG_CHANNEL_CODING (1 << 6)
|
||||
#define SOR_DP_TPG_SCRAMBLER_MASK (3 << 4)
|
||||
#define SOR_DP_TPG_SCRAMBLER_FIBONACCI (2 << 4)
|
||||
#define SOR_DP_TPG_SCRAMBLER_GALIOS (1 << 4)
|
||||
#define SOR_DP_TPG_SCRAMBLER_NONE (0 << 4)
|
||||
#define SOR_DP_TPG_PATTERN_MASK (0xf << 0)
|
||||
#define SOR_DP_TPG_PATTERN_HBR2 (0x8 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_CSTM (0x7 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_PRBS7 (0x6 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_SBLERRRATE (0x5 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_D102 (0x4 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_TRAIN3 (0x3 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_TRAIN2 (0x2 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_TRAIN1 (0x1 << 0)
|
||||
#define SOR_DP_TPG_PATTERN_NONE (0x0 << 0)
|
||||
|
||||
#define SOR_DP_TPG_CONFIG 0x6e
|
||||
#define SOR_DP_LQ_CSTM_0 0x6f
|
||||
#define SOR_DP_LQ_CSTM_1 0x70
|
||||
#define SOR_DP_LQ_CSTM_2 0x71
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user