forked from Minki/linux
[POWERPC] 85xxCDS: MPC8548 DTS cleanup.
Added the P2P bridge present on the Arcadia base board and moved the VIA Southbridge behind the bridge to reflect its actual position in the bus organization. Added the RTC that's in the VIA Southbridge and expanded the ranges array for the SOC node to allow proper address translation of the RTC registers. Signed-off-by: Randy Vinson <rvinson@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Randy Vinson
Kumar Gala
parent
8d7bc8f9d1
commit
6af0125742
@ -44,8 +44,14 @@
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00100000>; // CCSRBAR 1M
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ranges = <00001000 e0001000 000ff000
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80000000 80000000 10000000
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e2000000 e2000000 00800000
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90000000 90000000 10000000
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e2800000 e2800000 00800000
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a0000000 a0000000 20000000
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e3000000 e3000000 01000000>;
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reg = <e0000000 00001000>; // CCSRBAR
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bus-frequency = <0>;
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memory-controller@2000 {
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@ -162,8 +168,8 @@
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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reg = <4500 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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@ -172,7 +178,7 @@
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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@ -183,8 +189,8 @@
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fsl,has-rstcr;
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};
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pci1: pci@8000 {
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interrupt-map-mask = <1f800 0 0 7>;
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pci@8000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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02000 0 0 1 &mpic 0 1
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@ -244,19 +250,7 @@
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0E000 0 0 1 &mpic 0 1
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0E000 0 0 2 &mpic 1 1
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0E000 0 0 3 &mpic 2 1
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0E000 0 0 4 &mpic 3 1
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/* bus 1 , idsel 0x2 Tsi310 bridge secondary */
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11000 0 0 1 &mpic 2 1
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11000 0 0 2 &mpic 3 1
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11000 0 0 3 &mpic 0 1
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11000 0 0 4 &mpic 1 1
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/* VIA chip */
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12000 0 0 1 &mpic 0 1
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12000 0 0 2 &mpic 1 1
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12000 0 0 3 &mpic 2 1
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12000 0 0 4 &mpic 3 1>;
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0E000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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@ -271,18 +265,78 @@
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compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
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device_type = "pci";
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i8259@4 {
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clock-frequency = <0>;
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <12000 0 0 0 1>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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built-in;
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compatible = "chrp,iic";
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big-endian;
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interrupts = <1>;
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interrupt-parent = <&pci1>;
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pci_bridge@1c {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0 0 1 &mpic 0 1
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0000 0 0 2 &mpic 1 1
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0000 0 0 3 &mpic 2 1
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0000 0 0 4 &mpic 3 1
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/* IDSEL 0x04 (VIA chip) */
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2000 0 0 1 &mpic 0 1
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2000 0 0 2 &mpic 1 1
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2000 0 0 3 &mpic 2 1
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2000 0 0 4 &mpic 3 1
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/* IDSEL 0x05 (8139) */
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2800 0 0 1 &mpic 1 1
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/* IDSEL 0x06 (Slot 6) */
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3000 0 0 1 &mpic 2 1
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3000 0 0 2 &mpic 3 1
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3000 0 0 3 &mpic 0 1
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3000 0 0 4 &mpic 1 1
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/* IDESL 0x07 (Slot 7) */
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3800 0 0 1 &mpic 3 1
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3800 0 0 2 &mpic 0 1
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3800 0 0 3 &mpic 1 1
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3800 0 0 4 &mpic 2 1>;
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reg = <e000 0 0 0 0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <02000000 0 80000000
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02000000 0 80000000
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0 20000000
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01000000 0 00000000
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01000000 0 00000000
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0 00080000>;
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clock-frequency = <1fca055>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <2000 0 0 0 0>;
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ranges = <1 0 01000000 0 0 00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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clock-frequency = <0>;
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <1 20 2
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1 a0 2
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1 4d0 2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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built-in;
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compatible = "chrp,iic";
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interrupts = <0 1>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <1 70 2>;
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};
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};
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};
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};
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@ -292,9 +346,9 @@
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic b 1
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a800 0 0 2 &mpic b 1
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a800 0 0 3 &mpic b 1
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a800 0 0 4 &mpic b 1>;
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a800 0 0 2 &mpic 1 1
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a800 0 0 3 &mpic 2 1
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a800 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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