forked from Minki/linux
Merge branch 'for-3.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata fixes from Tejun Heo: "Mostly device-specific fixes. The only thing which isn't is the fix for zpodd oops-on-detach bug" * 'for-3.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: imx: PLL clock needs 100us to settle down ata: pata_at91 only works on sam9 libata: clean up ZPODD when a port is detached ahci: imx: software workaround for phy reset issue in resume ahci: imx: add namespace for register enums ahci: disable DEVSLP for Intel Valleyview
This commit is contained in:
Linus Torvalds
commit
6ab9028d00
@ -815,7 +815,7 @@ config PATA_AT32
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config PATA_AT91
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tristate "PATA support for AT91SAM9260"
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depends on ARM && ARCH_AT91
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depends on ARM && SOC_AT91SAM9
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help
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This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
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@ -1115,6 +1115,17 @@ static bool ahci_broken_online(struct pci_dev *pdev)
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return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
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}
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static bool ahci_broken_devslp(struct pci_dev *pdev)
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{
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/* device with broken DEVSLP but still showing SDS capability */
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static const struct pci_device_id ids[] = {
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{ PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
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{}
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};
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return pci_match_id(ids, pdev);
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}
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#ifdef CONFIG_ATA_ACPI
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static void ahci_gtf_filter_workaround(struct ata_host *host)
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{
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@ -1364,6 +1375,10 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
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/* must set flag prior to save config in order to take effect */
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if (ahci_broken_devslp(pdev))
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hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
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/* save initial config */
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ahci_pci_save_initial_config(pdev, hpriv);
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@ -236,6 +236,7 @@ enum {
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port start (wait until
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error-handling stage) */
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AHCI_HFLAG_MULTI_MSI = (1 << 16), /* multiple PCI MSIs */
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AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
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/* ap->flags bits */
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@ -29,9 +29,25 @@
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#include "ahci.h"
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enum {
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PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
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PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
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HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
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/* Timer 1-ms Register */
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IMX_TIMER1MS = 0x00e0,
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/* Port0 PHY Control Register */
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IMX_P0PHYCR = 0x0178,
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IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
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IMX_P0PHYCR_CR_READ = 1 << 19,
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IMX_P0PHYCR_CR_WRITE = 1 << 18,
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IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
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IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
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/* Port0 PHY Status Register */
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IMX_P0PHYSR = 0x017c,
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IMX_P0PHYSR_CR_ACK = 1 << 18,
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IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
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/* Lane0 Output Status Register */
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IMX_LANE0_OUT_STAT = 0x2003,
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IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
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/* Clock Reset Register */
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IMX_CLOCK_RESET = 0x7f3f,
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IMX_CLOCK_RESET_RESET = 1 << 0,
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};
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enum ahci_imx_type {
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@ -54,9 +70,149 @@ MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support
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static void ahci_imx_host_stop(struct ata_host *host);
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static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
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{
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int timeout = 10;
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u32 crval;
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u32 srval;
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/* Assert or deassert the bit */
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crval = readl(mmio + IMX_P0PHYCR);
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if (assert)
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crval |= bit;
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else
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crval &= ~bit;
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writel(crval, mmio + IMX_P0PHYCR);
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/* Wait for the cr_ack signal */
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do {
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srval = readl(mmio + IMX_P0PHYSR);
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if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
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break;
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usleep_range(100, 200);
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
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{
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u32 crval = addr;
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int ret;
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/* Supply the address on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_addr signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_addr */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_phy_reg_write(u16 val, void __iomem *mmio)
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{
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u32 crval = val;
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int ret;
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/* Supply the data on cr_data_in */
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writel(crval, mmio + IMX_P0PHYCR);
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/* Assert the cr_cap_data signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
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if (ret)
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return ret;
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/* Deassert cr_cap_data */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
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if (ret)
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return ret;
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if (val & IMX_CLOCK_RESET_RESET) {
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/*
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* In case we're resetting the phy, it's unable to acknowledge,
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* so we return immediately here.
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*/
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crval |= IMX_P0PHYCR_CR_WRITE;
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writel(crval, mmio + IMX_P0PHYCR);
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goto out;
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}
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/* Assert the cr_write signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
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if (ret)
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return ret;
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/* Deassert cr_write */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
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if (ret)
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return ret;
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out:
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return 0;
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}
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static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
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{
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int ret;
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/* Assert the cr_read signal */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
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if (ret)
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return ret;
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/* Capture the data from cr_data_out[] */
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*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
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/* Deassert cr_read */
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ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
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if (ret)
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return ret;
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return 0;
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}
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static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
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{
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void __iomem *mmio = hpriv->mmio;
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int timeout = 10;
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u16 val;
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int ret;
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/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
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ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
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if (ret)
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return ret;
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/* Wait for PHY RX_PLL to be stable */
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do {
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usleep_range(100, 200);
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ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
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if (ret)
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return ret;
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ret = imx_phy_reg_read(&val, mmio);
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if (ret)
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return ret;
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if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
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break;
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} while (--timeout);
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return timeout ? 0 : -ETIMEDOUT;
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}
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static int imx_sata_enable(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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struct device *dev = &imxpriv->ahci_pdev->dev;
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int ret;
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if (imxpriv->no_device)
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@ -101,6 +257,14 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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usleep_range(100, 200);
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ret = imx_sata_phy_reset(hpriv);
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if (ret) {
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dev_err(dev, "failed to reset phy: %d\n", ret);
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goto disable_regulator;
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}
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}
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usleep_range(1000, 2000);
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@ -156,8 +320,8 @@ static void ahci_imx_error_handler(struct ata_port *ap)
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* without full reset once the pddq mode is enabled making it
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* impossible to use as part of libata LPM.
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*/
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reg_val = readl(mmio + PORT_PHY_CTL);
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writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
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reg_val = readl(mmio + IMX_P0PHYCR);
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writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
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imx_sata_disable(hpriv);
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imxpriv->no_device = true;
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}
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@ -217,6 +381,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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if (!imxpriv)
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return -ENOMEM;
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imxpriv->ahci_pdev = pdev;
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imxpriv->no_device = false;
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imxpriv->first_time = true;
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imxpriv->type = (enum ahci_imx_type)of_id->data;
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@ -248,7 +413,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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/*
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* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
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* and IP vendor specific register HOST_TIMER1MS.
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* and IP vendor specific register IMX_TIMER1MS.
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* Configure CAP_SSS (support stagered spin up).
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* Implement the port0.
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* Get the ahb clock rate, and configure the TIMER1MS register.
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@ -265,7 +430,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
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}
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reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
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writel(reg_val, hpriv->mmio + HOST_TIMER1MS);
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writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
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ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
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if (ret)
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@ -452,6 +452,13 @@ void ahci_save_initial_config(struct device *dev,
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cap &= ~HOST_CAP_SNTF;
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}
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if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
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dev_info(dev,
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"controller can't do DEVSLP, turning off\n");
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cap2 &= ~HOST_CAP2_SDS;
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cap2 &= ~HOST_CAP2_SADM;
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}
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if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
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dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
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cap |= HOST_CAP_FBS;
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@ -6314,6 +6314,8 @@ int ata_host_activate(struct ata_host *host, int irq,
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static void ata_port_detach(struct ata_port *ap)
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{
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unsigned long flags;
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struct ata_link *link;
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struct ata_device *dev;
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if (!ap->ops->error_handler)
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goto skip_eh;
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@ -6333,6 +6335,13 @@ static void ata_port_detach(struct ata_port *ap)
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cancel_delayed_work_sync(&ap->hotplug_task);
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skip_eh:
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/* clean up zpodd on port removal */
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ata_for_each_link(link, ap, HOST_FIRST) {
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ata_for_each_dev(dev, link, ALL) {
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if (zpodd_dev_enabled(dev))
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zpodd_exit(dev);
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}
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}
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if (ap->pmp_link) {
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int i;
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for (i = 0; i < SATA_PMP_MAX_PORTS; i++)
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