Merge branch 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac
Pull EDAC updates from Mauro Carvalho Chehab. * 'linux_next' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: sb_edac: add support for Haswell based systems sb_edac: Fix mix tab/spaces alignments edac: add DDR4 and RDDR4 sb_edac: remove bogus assumption on mc ordering sb_edac: make minimal use of channel_mask sb_edac: fix socket detection on Ivy Bridge controllers sb_edac: update Kconfig description sb_edac: search devices using product id sb_edac: make RIR limit retrieval per model sb_edac: make node id retrieval per model sb_edac: make memory type detection per memory controller
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68ffeca4f4
@ -253,12 +253,12 @@ config EDAC_I7300
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Clarksboro MCH (Intel 7300 chipset).
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Clarksboro MCH (Intel 7300 chipset).
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config EDAC_SBRIDGE
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config EDAC_SBRIDGE
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tristate "Intel Sandy-Bridge Integrated MC"
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI_MMCONFIG
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depends on PCI_MMCONFIG
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help
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help
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Support for error detection and correction the Intel
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Support for error detection and correction the Intel
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Sandy Bridge Integrated Memory Controller.
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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config EDAC_MPC85XX
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config EDAC_MPC85XX
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tristate "Freescale MPC83xx / MPC85xx"
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tristate "Freescale MPC83xx / MPC85xx"
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@ -108,7 +108,9 @@ static const char * const mem_types[] = {
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[MEM_RDDR2] = "Registered-DDR2",
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[MEM_RDDR2] = "Registered-DDR2",
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[MEM_XDR] = "XDR",
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[MEM_XDR] = "XDR",
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[MEM_DDR3] = "Unbuffered-DDR3",
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[MEM_DDR3] = "Unbuffered-DDR3",
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[MEM_RDDR3] = "Registered-DDR3"
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[MEM_RDDR3] = "Registered-DDR3",
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[MEM_DDR4] = "Unbuffered-DDR4",
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[MEM_RDDR4] = "Registered-DDR4"
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};
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};
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static const char * const dev_types[] = {
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static const char * const dev_types[] = {
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File diff suppressed because it is too large
Load Diff
@ -194,6 +194,9 @@ static inline char *mc_event_error_type(const unsigned int err_type)
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* @MEM_DDR3: DDR3 RAM
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* @MEM_DDR3: DDR3 RAM
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* @MEM_RDDR3: Registered DDR3 RAM
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* @MEM_RDDR3: Registered DDR3 RAM
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* This is a variant of the DDR3 memories.
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* This is a variant of the DDR3 memories.
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* @MEM_DDR4: DDR4 RAM
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* @MEM_RDDR4: Registered DDR4 RAM
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* This is a variant of the DDR4 memories.
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*/
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*/
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enum mem_type {
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enum mem_type {
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MEM_EMPTY = 0,
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MEM_EMPTY = 0,
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@ -213,6 +216,8 @@ enum mem_type {
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MEM_XDR,
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MEM_XDR,
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MEM_DDR3,
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MEM_DDR3,
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MEM_RDDR3,
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MEM_RDDR3,
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MEM_DDR4,
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MEM_RDDR4,
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};
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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