leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid

Browse Source 
Only disable 3D pipe 1 on navi1x, enable 3D pipe 1 on Sienna_Cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao
2020-03-03 10:40:32 +08:00
committed by Alex Deucher
parent 1f5d9cad08
commit 689dede0a0
1 changed files with 13 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@@ -55,6 +55,7 @@
* 2. Async ring * 2. Async ring
*/ */
#define GFX10_NUM_GFX_RINGS_NV1X 1 #define GFX10_NUM_GFX_RINGS_NV1X 1
#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
#define GFX10_MEC_HPD_SIZE 2048 #define GFX10_MEC_HPD_SIZE 2048
#define F32_CE_PROGRAM_RAM_SIZE 65536 #define F32_CE_PROGRAM_RAM_SIZE 65536
@@ -7057,7 +7058,18 @@ static int gfx_v10_0_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
break;
case CHIP_SIENNA_CICHLID:
adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
break;
default:
break;
}
adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;