forked from Minki/linux
b43: Port spec bugfixes for the LP baseband init
A few bugs were fixed in the LP baseband init specs. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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c970314615
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@ -70,6 +70,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
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static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
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{
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struct ssb_bus *bus = dev->dev->bus;
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struct b43_phy_lp *lpphy = dev->phy.lp;
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b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
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@ -89,7 +90,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
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b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
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b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
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b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
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b43_phy_maskset(dev, B43_LPPHY_CCKLMSSTEPSIZE, 0xFF01, 0x10);
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b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
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b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
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b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
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b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
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@ -101,8 +102,13 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
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b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
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b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
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b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
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b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
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if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
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b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
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b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
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} else {
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b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
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b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
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}
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b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
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b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
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b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
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@ -114,17 +120,8 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
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b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
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b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
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if (dev->phy.rev < 2) {
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//FIXME this will never execute.
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//FIXME 32bit?
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b43_lptab_write(dev, B43_LPTAB32(0x11, 0x14), 0);
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b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
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} else {
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//FIXME 32bit?
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b43_lptab_write(dev, B43_LPTAB32(0x08, 0x14), 0);
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b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
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}
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b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
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b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
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if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
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b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
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