DM9000B: driver initialization upgrade
Fix bug for DM9000 revision B which contain a DSP PHY DM9000B use DSP PHY instead previouse DM9000 revisions' analog PHY, So need extra change in initialization, For explicity PHY Reset and PHY init parameter, and first DM9000_NCR reset need NCR_MAC_LBK bit by dm9000_probe(). Following DM9000_NCR reset cause by dm9000_open() clear the NCR_MAC_LBK bit. Without this fix, Power-up FIFO pointers error happen around 2% rate among Davicom's customers' boards. With this fix, All above cases can be solved. Signed-off-by: Joseph CHANG <josright123@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Joseph CHANG
David S. Miller
parent
3340d2aae3
commit
6741f40d19
@ -257,6 +257,107 @@ static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
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tmp = readl(reg);
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}
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/*
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* Sleep, either by using msleep() or if we are suspending, then
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* use mdelay() to sleep.
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*/
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static void dm9000_msleep(board_info_t *db, unsigned int ms)
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{
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if (db->in_suspend)
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mdelay(ms);
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else
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msleep(ms);
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}
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/* Read a word from phyxcer */
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static int
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dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
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{
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board_info_t *db = netdev_priv(dev);
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unsigned long flags;
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unsigned int reg_save;
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int ret;
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock, flags);
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/* Save previous register address */
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reg_save = readb(db->io_addr);
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/* Fill the phyxcer register into REG_0C */
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iow(db, DM9000_EPAR, DM9000_PHY | reg);
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/* Issue phyxcer read command */
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iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS);
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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dm9000_msleep(db, 1); /* Wait read complete */
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spin_lock_irqsave(&db->lock, flags);
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reg_save = readb(db->io_addr);
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iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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/* The read data keeps on REG_0D & REG_0E */
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ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
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/* restore the previous address */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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mutex_unlock(&db->addr_lock);
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dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
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return ret;
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}
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/* Write a word to phyxcer */
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static void
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dm9000_phy_write(struct net_device *dev,
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int phyaddr_unused, int reg, int value)
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{
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board_info_t *db = netdev_priv(dev);
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unsigned long flags;
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unsigned long reg_save;
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dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock, flags);
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/* Save previous register address */
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reg_save = readb(db->io_addr);
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/* Fill the phyxcer register into REG_0C */
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iow(db, DM9000_EPAR, DM9000_PHY | reg);
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/* Fill the written data into REG_0D & REG_0E */
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iow(db, DM9000_EPDRL, value);
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iow(db, DM9000_EPDRH, value >> 8);
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/* Issue phyxcer write command */
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iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW);
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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dm9000_msleep(db, 1); /* Wait write complete */
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spin_lock_irqsave(&db->lock, flags);
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reg_save = readb(db->io_addr);
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iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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/* restore the previous address */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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mutex_unlock(&db->addr_lock);
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}
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/* dm9000_set_io
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*
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* select the specified set of io routines to use with the
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@ -795,6 +896,9 @@ dm9000_init_dm9000(struct net_device *dev)
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iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
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dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
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dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */
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ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
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/* if wol is needed, then always set NCR_WAKEEN otherwise we end
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@ -1201,109 +1305,6 @@ dm9000_open(struct net_device *dev)
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return 0;
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}
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/*
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* Sleep, either by using msleep() or if we are suspending, then
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* use mdelay() to sleep.
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*/
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static void dm9000_msleep(board_info_t *db, unsigned int ms)
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{
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if (db->in_suspend)
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mdelay(ms);
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else
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msleep(ms);
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}
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/*
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* Read a word from phyxcer
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*/
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static int
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dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
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{
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board_info_t *db = netdev_priv(dev);
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unsigned long flags;
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unsigned int reg_save;
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int ret;
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock,flags);
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/* Save previous register address */
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reg_save = readb(db->io_addr);
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/* Fill the phyxcer register into REG_0C */
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iow(db, DM9000_EPAR, DM9000_PHY | reg);
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iow(db, DM9000_EPCR, EPCR_ERPRR | EPCR_EPOS); /* Issue phyxcer read command */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock,flags);
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dm9000_msleep(db, 1); /* Wait read complete */
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spin_lock_irqsave(&db->lock,flags);
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reg_save = readb(db->io_addr);
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iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
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/* The read data keeps on REG_0D & REG_0E */
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ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
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/* restore the previous address */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock,flags);
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mutex_unlock(&db->addr_lock);
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dm9000_dbg(db, 5, "phy_read[%02x] -> %04x\n", reg, ret);
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return ret;
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}
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/*
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* Write a word to phyxcer
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*/
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static void
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dm9000_phy_write(struct net_device *dev,
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int phyaddr_unused, int reg, int value)
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{
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board_info_t *db = netdev_priv(dev);
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unsigned long flags;
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unsigned long reg_save;
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dm9000_dbg(db, 5, "phy_write[%02x] = %04x\n", reg, value);
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mutex_lock(&db->addr_lock);
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spin_lock_irqsave(&db->lock,flags);
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/* Save previous register address */
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reg_save = readb(db->io_addr);
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/* Fill the phyxcer register into REG_0C */
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iow(db, DM9000_EPAR, DM9000_PHY | reg);
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/* Fill the written data into REG_0D & REG_0E */
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iow(db, DM9000_EPDRL, value);
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iow(db, DM9000_EPDRH, value >> 8);
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iow(db, DM9000_EPCR, EPCR_EPOS | EPCR_ERPRW); /* Issue phyxcer write command */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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dm9000_msleep(db, 1); /* Wait write complete */
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spin_lock_irqsave(&db->lock,flags);
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reg_save = readb(db->io_addr);
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iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
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/* restore the previous address */
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writeb(reg_save, db->io_addr);
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spin_unlock_irqrestore(&db->lock, flags);
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mutex_unlock(&db->addr_lock);
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}
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static void
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dm9000_shutdown(struct net_device *dev)
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{
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@ -1502,7 +1503,12 @@ dm9000_probe(struct platform_device *pdev)
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db->flags |= DM9000_PLATF_SIMPLE_PHY;
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#endif
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dm9000_reset(db);
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/* Fixing bug on dm9000_probe, takeover dm9000_reset(db),
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* Need 'NCR_MAC_LBK' bit to indeed stable our DM9000 fifo
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* while probe stage.
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*/
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iow(db, DM9000_NCR, NCR_MAC_LBK | NCR_RST);
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/* try multiple times, DM9000 sometimes gets the read wrong */
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for (i = 0; i < 8; i++) {
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@ -69,7 +69,9 @@
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#define NCR_WAKEEN (1<<6)
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#define NCR_FCOL (1<<4)
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#define NCR_FDX (1<<3)
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#define NCR_LBK (3<<1)
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#define NCR_RESERVED (3<<1)
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#define NCR_MAC_LBK (1<<1)
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#define NCR_RST (1<<0)
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#define NSR_SPEED (1<<7)
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@ -167,5 +169,12 @@
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#define ISR_LNKCHNG (1<<5)
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#define ISR_UNDERRUN (1<<4)
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/* Davicom MII registers.
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*/
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#define MII_DM_DSPCR 0x1b /* DSP Control Register */
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#define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
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#endif /* _DM9000X_H_ */
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