forked from Minki/linux
MIPS: Netlogic: Merge some of XLR/XLP wakup code
Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C
Ralf Baechle
parent
8da24631e6
commit
66d29985fa
@ -38,19 +38,39 @@
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/*
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* Common SMP definitions
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*/
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#define RESET_VEC_PHYS 0x1fc00000
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#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
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#define BOOT_THREAD_MODE 0
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#define BOOT_NMI_LOCK 4
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#define BOOT_NMI_HANDLER 8
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#ifndef __ASSEMBLY__
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struct irq_desc;
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extern struct plat_smp_ops nlm_smp_ops;
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extern char nlm_reset_entry[], nlm_reset_entry_end[];
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void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc);
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void nlm_smp_irq_init(void);
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void prom_pre_boot_secondary_cpus(void);
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void nlm_boot_secondary_cpus(void);
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int nlm_wakeup_secondary_cpus(u32 wakeup_mask);
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void nlm_boot_smp_nmi(void);
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void nlm_rmiboot_preboot(void);
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static inline void
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nlm_set_nmi_handler(void *handler)
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{
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char *reset_data;
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reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
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*(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler;
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}
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/*
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* Misc.
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*/
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unsigned int nlm_get_cpu_frequency(void);
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extern unsigned long nlm_common_ebase;
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unsigned int nlm_get_cpu_frequency(void);
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extern int nlm_threads_per_core;
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extern uint32_t nlm_cpumask, nlm_coremask;
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#endif
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#endif /* _NETLOGIC_COMMON_H_ */
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@ -35,17 +35,14 @@
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#ifndef _NLM_HAL_XLP_H
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#define _NLM_HAL_XLP_H
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#define RESET_VEC_PHYS 0x1fc00000
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#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
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#define BOOT_THREAD_MODE 0
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#define PIC_UART_0_IRQ 17
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#define PIC_UART_1_IRQ 18
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#ifndef __ASSEMBLY__
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/* SMP support functions */
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void nlm_boot_core0_siblings(void);
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void xlp_boot_core0_siblings(void);
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void xlp_wakeup_secondary_cpus(void);
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void xlp_mmu_init(void);
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void nlm_hal_init(void);
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@ -40,6 +40,8 @@ struct uart_port;
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unsigned int nlm_xlr_uart_in(struct uart_port *, int);
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void nlm_xlr_uart_out(struct uart_port *, int, int);
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/* SMP helpers */
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void xlr_wakeup_secondary_cpus(void);
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/* XLS B silicon "Rook" */
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static inline unsigned int nlm_chip_is_xls_b(void)
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@ -1,3 +1,3 @@
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obj-y += irq.o time.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SMP) += smp.o smpboot.o
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obj-$(CONFIG_EARLY_PRINTK) += earlycons.o
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@ -47,10 +47,12 @@
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#include <asm/netlogic/xlr/xlr.h>
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#else
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#error "Unknown CPU"
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#endif
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@ -125,10 +127,10 @@ void nlm_cpus_done(void)
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* Boot all other cpus in the system, initialize them, and bring them into
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* the boot function
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*/
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int nlm_cpu_unblock[NR_CPUS];
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int nlm_cpu_ready[NR_CPUS];
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unsigned long nlm_next_gp;
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unsigned long nlm_next_sp;
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cpumask_t phys_cpu_present_map;
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void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
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@ -142,7 +144,7 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
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/* barrier */
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__sync();
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nlm_cpu_unblock[cpu] = 1;
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nlm_pic_send_ipi(nlm_pic_base, cpu, 1, 1);
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}
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void __init nlm_smp_setup(void)
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@ -178,12 +180,81 @@ void __init nlm_smp_setup(void)
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(unsigned long)cpu_possible_map.bits[0]);
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pr_info("Detected %i Slave CPU(s)\n", num_cpus);
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nlm_set_nmi_handler(nlm_boot_secondary_cpus);
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}
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void nlm_prepare_cpus(unsigned int max_cpus)
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{
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}
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static int nlm_parse_cpumask(u32 cpu_mask)
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{
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uint32_t core0_thr_mask, core_thr_mask;
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int threadmode, i;
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core0_thr_mask = cpu_mask & 0xf;
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switch (core0_thr_mask) {
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case 1:
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nlm_threads_per_core = 1;
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threadmode = 0;
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break;
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case 3:
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nlm_threads_per_core = 2;
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threadmode = 2;
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break;
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case 0xf:
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nlm_threads_per_core = 4;
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threadmode = 3;
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break;
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default:
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goto unsupp;
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}
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/* Verify other cores CPU masks */
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nlm_coremask = 1;
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nlm_cpumask = core0_thr_mask;
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for (i = 1; i < 8; i++) {
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core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
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if (core_thr_mask) {
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if (core_thr_mask != core0_thr_mask)
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goto unsupp;
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nlm_coremask |= 1 << i;
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nlm_cpumask |= core0_thr_mask << (4 * i);
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}
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}
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return threadmode;
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unsupp:
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panic("Unsupported CPU mask %x\n", cpu_mask);
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return 0;
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}
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int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
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{
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unsigned long reset_vec;
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char *reset_data;
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int threadmode;
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/* Update reset entry point with CPU init code */
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reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
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memcpy((void *)reset_vec, (void *)nlm_reset_entry,
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(nlm_reset_entry_end - nlm_reset_entry));
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/* verify the mask and setup core config variables */
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threadmode = nlm_parse_cpumask(wakeup_mask);
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/* Setup CPU init parameters */
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reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS);
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*(int *)(reset_data + BOOT_THREAD_MODE) = threadmode;
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#ifdef CONFIG_CPU_XLP
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xlp_wakeup_secondary_cpus();
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#else
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xlr_wakeup_secondary_cpus();
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#endif
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return 0;
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}
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struct plat_smp_ops nlm_smp_ops = {
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.send_ipi_single = nlm_send_ipi_single,
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.send_ipi_mask = nlm_send_ipi_mask,
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@ -42,6 +42,8 @@
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#include <asm/asmmacro.h>
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#include <asm/addrspace.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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@ -67,11 +69,37 @@
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mtcr t1, t0
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.endm
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/*
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* The cores can come start when they are woken up. This is also the NMI
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* entry, so check that first.
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*
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* The data corresponding to reset is stored at RESET_DATA_PHYS location,
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* this will have the thread mask (used when core is woken up) and the
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* current NMI handler in case we reached here for an NMI.
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*
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* When a core or thread is newly woken up, it loops in a 'wait'. When
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* the CPU really needs waking up, we send an NMI to it, with the NMI
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* handler set to prom_boot_secondary_cpus
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*/
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.set noreorder
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.set noat
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.set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
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__CPUINIT
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EXPORT(nlm_reset_entry)
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FEXPORT(nlm_reset_entry)
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dmtc0 k0, $22, 6
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dmtc0 k1, $22, 7
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mfc0 k0, CP0_STATUS
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li k1, 0x80000
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and k1, k0, k1
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beqz k1, 1f /* go to real reset entry */
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nop
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li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
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ld k0, BOOT_NMI_HANDLER(k1)
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jr k0
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nop
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1: /* Entry point on core wakeup */
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mfc0 t0, CP0_EBASE, 1
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mfc0 t1, CP0_EBASE, 1
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srl t1, 5
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@ -128,7 +156,7 @@ EXPORT(nlm_boot_siblings)
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ehb
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#endif
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2: beqz v0, 3f
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2: beqz v0, 4f
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nop
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/* setup status reg */
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@ -140,17 +168,22 @@ EXPORT(nlm_boot_siblings)
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ori t1, ST0_KX
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#endif
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mtc0 t1, CP0_STATUS
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/* SETUP TLBs for a mapped kernel here */
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PTR_LA t0, prom_pre_boot_secondary_cpus
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jalr t0
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/* mark CPU ready */
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PTR_LA t1, nlm_cpu_ready
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sll v1, v0, 2
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PTR_ADDU t1, v1
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li t2, 1
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sw t2, 0(t1)
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/* Wait until NMI hits */
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3: wait
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j 3b
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nop
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/*
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* For the boot CPU, we have to restore registers and
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* return
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*/
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3: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
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li t1, 0xfadebeef
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dmtc0 t1, $4, 2 /* restore SP from UserLocal */
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PTR_SUBU sp, t0, PT_SIZE
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@ -159,7 +192,7 @@ EXPORT(nlm_boot_siblings)
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nop
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EXPORT(nlm_reset_entry_end)
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EXPORT(nlm_boot_core0_siblings) /* "Master" (n0c0t0) cpu starts from here */
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FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
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__config_lsu
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dmtc0 sp, $4, 2 /* SP saved in UserLocal */
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SAVE_ALL
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@ -173,34 +206,11 @@ EXPORT(nlm_boot_core0_siblings) /* "Master" (n0c0t0) cpu starts from here */
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/* call it */
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jr t2
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nop
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__FINIT
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/* not reached */
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__CPUINIT
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NESTED(prom_pre_boot_secondary_cpus, 16, sp)
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.set mips64
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mfc0 a0, CP0_EBASE, 1 /* read ebase */
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andi a0, 0x3ff /* a0 has the processor_id() */
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sll t0, a0, 2 /* offset in cpu array */
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PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
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PTR_ADDU t1, t0
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li t2, 1
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sw t2, 0(t1)
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PTR_LA t1, nlm_cpu_unblock
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PTR_ADDU t1, t0
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1: lw t2, 0(t1) /* wait till unblocked */
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bnez t2, 2f
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nop
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nop
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nop
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nop
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nop
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nop
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j 1b
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nop
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2: PTR_LA t1, nlm_next_sp
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NESTED(nlm_boot_secondary_cpus, 16, sp)
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PTR_LA t1, nlm_next_sp
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PTR_L sp, 0(t1)
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PTR_LA t1, nlm_next_gp
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PTR_L gp, 0(t1)
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@ -213,5 +223,50 @@ NESTED(prom_pre_boot_secondary_cpus, 16, sp)
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PTR_LA t0, smp_bootstrap
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jr t0
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nop
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END(prom_pre_boot_secondary_cpus)
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END(nlm_boot_secondary_cpus)
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__FINIT
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/*
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* In case of RMIboot bootloader which is used on XLR boards, the CPUs
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* be already woken up and waiting in bootloader code.
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* This will get them out of the bootloader code and into linux. Needed
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* because the bootloader area will be taken and initialized by linux.
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*/
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__CPUINIT
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NESTED(nlm_rmiboot_preboot, 16, sp)
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mfc0 t0, $15, 1 # read ebase
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andi t0, 0x1f # t0 has the processor_id()
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andi t2, t0, 0x3 # thread no
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sll t0, 2 # offset in cpu array
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PTR_LA t1, nlm_cpu_ready # mark CPU ready
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PTR_ADDU t1, t0
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li t3, 1
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sw t3, 0(t1)
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bnez t2, 1f # skip thread programming
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nop # for non zero hw threads
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/*
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* MMU setup only for first thread in core
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*/
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li t0, 0x400
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mfcr t1, t0
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li t2, 6 # XLR thread mode mask
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nor t3, t2, zero
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and t2, t1, t2 # t2 - current thread mode
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li v0, CKSEG1ADDR(RESET_DATA_PHYS)
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lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
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sll v1, 1
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beq v1, t2, 1f # same as request value
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nop # nothing to do */
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and t2, t1, t3 # mask out old thread mode
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or t1, t2, v1 # put in new value
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mtcr t1, t0 # update core control
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1: wait
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j 1b
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nop
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END(nlm_rmiboot_preboot)
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__FINIT
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@ -1,2 +1,2 @@
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obj-y += setup.o platform.o nlm_hal.o
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obj-$(CONFIG_SMP) += smpboot.o wakeup.o
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obj-$(CONFIG_SMP) += wakeup.o
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@ -51,6 +51,10 @@
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unsigned long nlm_common_ebase = 0x0;
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/* default to uniprocessor */
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uint32_t nlm_coremask = 1, nlm_cpumask = 1;
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int nlm_threads_per_core = 1;
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static void nlm_linux_exit(void)
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{
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nlm_write_sys_reg(nlm_sys_base, SYS_CHIP_RESET, 1);
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@ -51,18 +51,20 @@
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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unsigned long secondary_entry;
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uint32_t nlm_coremask;
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unsigned int nlm_threads_per_core;
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unsigned int nlm_threadmode;
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static void nlm_enable_secondary_cores(unsigned int cores_bitmap)
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static void xlp_enable_secondary_cores(void)
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{
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uint32_t core, value, coremask;
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uint32_t core, value, coremask, syscoremask;
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int count;
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/* read cores in reset from SYS block */
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syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
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/* update user specified */
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nlm_coremask = nlm_coremask & (syscoremask | 1);
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for (core = 1; core < 8; core++) {
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coremask = 1 << core;
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if ((cores_bitmap & coremask) == 0)
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if ((nlm_coremask & coremask) == 0)
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continue;
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/* Enable CPU clock */
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@ -76,74 +78,25 @@ static void nlm_enable_secondary_cores(unsigned int cores_bitmap)
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nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
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/* Poll for CPU to mark itself coherent */
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count = 100000;
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do {
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value = nlm_read_sys_reg(nlm_sys_base,
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SYS_CPU_NONCOHERENT_MODE);
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} while ((value & coremask) != 0);
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} while ((value & coremask) != 0 && count-- > 0);
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if (count == 0)
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pr_err("Failed to enable core %d\n", core);
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}
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}
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static void nlm_parse_cpumask(u32 cpu_mask)
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void xlp_wakeup_secondary_cpus(void)
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{
|
||||
uint32_t core0_thr_mask, core_thr_mask;
|
||||
int i;
|
||||
/*
|
||||
* In case of u-boot, the secondaries are in reset
|
||||
* first wakeup core 0 threads
|
||||
*/
|
||||
xlp_boot_core0_siblings();
|
||||
|
||||
core0_thr_mask = cpu_mask & 0xf;
|
||||
switch (core0_thr_mask) {
|
||||
case 1:
|
||||
nlm_threads_per_core = 1;
|
||||
nlm_threadmode = 0;
|
||||
break;
|
||||
case 3:
|
||||
nlm_threads_per_core = 2;
|
||||
nlm_threadmode = 2;
|
||||
break;
|
||||
case 0xf:
|
||||
nlm_threads_per_core = 4;
|
||||
nlm_threadmode = 3;
|
||||
break;
|
||||
default:
|
||||
goto unsupp;
|
||||
}
|
||||
|
||||
/* Verify other cores CPU masks */
|
||||
nlm_coremask = 1;
|
||||
for (i = 1; i < 8; i++) {
|
||||
core_thr_mask = (cpu_mask >> (i * 4)) & 0xf;
|
||||
if (core_thr_mask) {
|
||||
if (core_thr_mask != core0_thr_mask)
|
||||
goto unsupp;
|
||||
nlm_coremask |= 1 << i;
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
unsupp:
|
||||
panic("Unsupported CPU mask %x\n", cpu_mask);
|
||||
}
|
||||
|
||||
int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
|
||||
{
|
||||
unsigned long reset_vec;
|
||||
unsigned int *reset_data;
|
||||
|
||||
/* Update reset entry point with CPU init code */
|
||||
reset_vec = CKSEG1ADDR(RESET_VEC_PHYS);
|
||||
memcpy((void *)reset_vec, (void *)nlm_reset_entry,
|
||||
(nlm_reset_entry_end - nlm_reset_entry));
|
||||
|
||||
/* verify the mask and setup core config variables */
|
||||
nlm_parse_cpumask(wakeup_mask);
|
||||
|
||||
/* Setup CPU init parameters */
|
||||
reset_data = (unsigned int *)CKSEG1ADDR(RESET_DATA_PHYS);
|
||||
reset_data[BOOT_THREAD_MODE] = nlm_threadmode;
|
||||
|
||||
/* first wakeup core 0 siblings */
|
||||
nlm_boot_core0_siblings();
|
||||
|
||||
/* enable the reset of the cores */
|
||||
nlm_enable_secondary_cores(nlm_coremask);
|
||||
return 0;
|
||||
/* now get other cores out of reset */
|
||||
xlp_enable_secondary_cores();
|
||||
}
|
||||
|
||||
@ -1,2 +1,2 @@
|
||||
obj-y += setup.o platform.o
|
||||
obj-$(CONFIG_SMP) += smpboot.o wakeup.o
|
||||
obj-$(CONFIG_SMP) += wakeup.o
|
||||
|
||||
@ -52,9 +52,14 @@
|
||||
|
||||
uint64_t nlm_io_base = DEFAULT_NETLOGIC_IO_BASE;
|
||||
uint64_t nlm_pic_base;
|
||||
unsigned long nlm_common_ebase = 0x0;
|
||||
struct psb_info nlm_prom_info;
|
||||
|
||||
unsigned long nlm_common_ebase = 0x0;
|
||||
|
||||
/* default to uniprocessor */
|
||||
uint32_t nlm_coremask = 1, nlm_cpumask = 1;
|
||||
int nlm_threads_per_core = 1;
|
||||
|
||||
static void __init nlm_early_serial_setup(void)
|
||||
{
|
||||
struct uart_port s;
|
||||
|
||||
@ -1,100 +0,0 @@
|
||||
/*
|
||||
* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
|
||||
* reserved.
|
||||
*
|
||||
* This software is available to you under a choice of one of two
|
||||
* licenses. You may choose to be licensed under the terms of the GNU
|
||||
* General Public License (GPL) Version 2, available from the file
|
||||
* COPYING in the main directory of this source tree, or the NetLogic
|
||||
* license below:
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* Early code for secondary CPUs. This will get them out of the bootloader
|
||||
* code and into linux. Needed because the bootloader area will be taken
|
||||
* and initialized by linux.
|
||||
*/
|
||||
__CPUINIT
|
||||
NESTED(prom_pre_boot_secondary_cpus, 16, sp)
|
||||
.set mips64
|
||||
mfc0 t0, $15, 1 # read ebase
|
||||
andi t0, 0x1f # t0 has the processor_id()
|
||||
sll t0, 2 # offset in cpu array
|
||||
|
||||
PTR_LA t1, nlm_cpu_ready # mark CPU ready
|
||||
PTR_ADDU t1, t0
|
||||
li t2, 1
|
||||
sw t2, 0(t1)
|
||||
|
||||
PTR_LA t1, nlm_cpu_unblock
|
||||
PTR_ADDU t1, t0
|
||||
1: lw t2, 0(t1) # wait till unblocked
|
||||
beqz t2, 1b
|
||||
nop
|
||||
|
||||
PTR_LA t1, nlm_next_sp
|
||||
PTR_L sp, 0(t1)
|
||||
PTR_LA t1, nlm_next_gp
|
||||
PTR_L gp, 0(t1)
|
||||
|
||||
PTR_LA t0, nlm_early_init_secondary
|
||||
jalr t0
|
||||
nop
|
||||
|
||||
PTR_LA t0, smp_bootstrap
|
||||
jr t0
|
||||
nop
|
||||
END(prom_pre_boot_secondary_cpus)
|
||||
|
||||
/*
|
||||
* NMI code, used for CPU wakeup, copied to reset entry
|
||||
*/
|
||||
EXPORT(nlm_reset_entry)
|
||||
.set push
|
||||
.set noat
|
||||
.set mips64
|
||||
.set noreorder
|
||||
|
||||
/* Clear the NMI and BEV bits */
|
||||
MFC0 k0, CP0_STATUS
|
||||
li k1, 0xffb7ffff
|
||||
and k0, k0, k1
|
||||
MTC0 k0, CP0_STATUS
|
||||
|
||||
PTR_LA k1, secondary_entry_point
|
||||
PTR_L k0, 0(k1)
|
||||
jr k0
|
||||
nop
|
||||
.set pop
|
||||
EXPORT(nlm_reset_entry_end)
|
||||
__FINIT
|
||||
@ -48,21 +48,18 @@
|
||||
#include <asm/netlogic/xlr/iomap.h>
|
||||
#include <asm/netlogic/xlr/pic.h>
|
||||
|
||||
unsigned long secondary_entry_point;
|
||||
|
||||
int __cpuinit nlm_wakeup_secondary_cpus(u32 wakeup_mask)
|
||||
int __cpuinit xlr_wakeup_secondary_cpus(void)
|
||||
{
|
||||
unsigned int i, boot_cpu;
|
||||
void *reset_vec;
|
||||
|
||||
secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
|
||||
reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
|
||||
memcpy(reset_vec, (void *)nlm_reset_entry,
|
||||
(nlm_reset_entry_end - nlm_reset_entry));
|
||||
/*
|
||||
* In case of RMI boot, hit with NMI to get the cores
|
||||
* from bootloader to linux code.
|
||||
*/
|
||||
boot_cpu = hard_smp_processor_id();
|
||||
|
||||
nlm_set_nmi_handler(nlm_rmiboot_preboot);
|
||||
for (i = 0; i < NR_CPUS; i++) {
|
||||
if (i == boot_cpu || (wakeup_mask & (1u << i)) == 0)
|
||||
if (i == boot_cpu || (nlm_cpumask & (1u << i)) == 0)
|
||||
continue;
|
||||
nlm_pic_send_ipi(nlm_pic_base, i, 1, 1); /* send NMI */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user