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drm/amd/powerplay: add pstate mclk(uclk) support for navi10

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add pstate mclk(uclk) support.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Kevin Wang 2019-07-12 11:27:50 +08:00 committed by Alex Deucher
parent d36893362d
commit 64974ab249
2 changed files with 8 additions and 1 deletions
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1
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -136,6 +136,7 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
return -EINVAL; return -EINVAL;
switch (clk_type) { switch (clk_type) {
case SMU_MCLK:
case SMU_UCLK: case SMU_UCLK:
if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
pr_warn("uclk dpm is not enabled\n"); pr_warn("uclk dpm is not enabled\n");

8
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -709,7 +709,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
static int navi10_populate_umd_state_clk(struct smu_context *smu) static int navi10_populate_umd_state_clk(struct smu_context *smu)
{ {
int ret = 0; int ret = 0;
uint32_t min_sclk_freq = 0; uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL); ret = smu_get_dpm_freq_range(smu, SMU_SCLK, &min_sclk_freq, NULL);
if (ret) if (ret)
@ -717,6 +717,12 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu)
smu->pstate_sclk = min_sclk_freq * 100; smu->pstate_sclk = min_sclk_freq * 100;
ret = smu_get_dpm_freq_range(smu, SMU_MCLK, &min_mclk_freq, NULL);
if (ret)
return ret;
smu->pstate_mclk = min_mclk_freq * 100;
return ret; return ret;
} }