remoteproc: mss: q6v5-mss: Add modem support on SC7180
Add the out of reset sequence support for modem sub-system on SC7180 SoCs. It requires access to an additional halt nav register to put the modem back into reset. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20191219054506.20565-3-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sibi Sankar
Bjorn Andersson
parent
65518e9cf5
commit
6439b5276b
@ -68,6 +68,9 @@
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#define AXI_HALTREQ_REG 0x0
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#define AXI_HALTACK_REG 0x4
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#define AXI_IDLE_REG 0x8
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#define NAV_AXI_HALTREQ_BIT BIT(0)
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#define NAV_AXI_HALTACK_BIT BIT(1)
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#define NAV_AXI_IDLE_BIT BIT(2)
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#define HALT_ACK_TIMEOUT_MS 100
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@ -101,9 +104,11 @@
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#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
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/* QDSP6v65 parameters */
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#define QDSP6SS_CORE_CBCR 0x20
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#define QDSP6SS_SLEEP 0x3C
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#define QDSP6SS_BOOT_CORE_START 0x400
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#define QDSP6SS_BOOT_CMD 0x404
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#define QDSP6SS_BOOT_STATUS 0x408
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#define SLEEP_CHECK_MAX_LOOPS 200
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#define BOOT_FSM_TIMEOUT 10000
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@ -131,6 +136,7 @@ struct rproc_hexagon_res {
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int version;
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bool need_mem_protection;
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bool has_alt_reset;
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bool has_halt_nav;
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};
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struct q6v5 {
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@ -141,9 +147,14 @@ struct q6v5 {
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void __iomem *rmb_base;
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struct regmap *halt_map;
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struct regmap *halt_nav_map;
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struct regmap *conn_map;
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u32 halt_q6;
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u32 halt_modem;
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u32 halt_nc;
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u32 halt_nav;
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u32 conn_box;
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struct reset_control *mss_restart;
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struct reset_control *pdc_reset;
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@ -187,6 +198,7 @@ struct q6v5 {
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struct qcom_sysmon *sysmon;
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bool need_mem_protection;
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bool has_alt_reset;
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bool has_halt_nav;
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int mpss_perm;
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int mba_perm;
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const char *hexagon_mdt_image;
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@ -198,6 +210,7 @@ enum {
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MSS_MSM8974,
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MSS_MSM8996,
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MSS_MSM8998,
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MSS_SC7180,
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MSS_SDM845,
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};
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@ -396,6 +409,18 @@ static int q6v5_reset_assert(struct q6v5 *qproc)
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reset_control_assert(qproc->pdc_reset);
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ret = reset_control_reset(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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} else if (qproc->has_halt_nav) {
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/* SWAR using CONN_BOX_SPARE_0 for pipeline glitch issue */
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reset_control_assert(qproc->pdc_reset);
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regmap_update_bits(qproc->conn_map, qproc->conn_box,
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BIT(0), BIT(0));
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regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav,
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NAV_AXI_HALTREQ_BIT, 0);
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reset_control_assert(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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regmap_update_bits(qproc->conn_map, qproc->conn_box,
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BIT(0), 0);
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ret = reset_control_deassert(qproc->mss_restart);
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} else {
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ret = reset_control_assert(qproc->mss_restart);
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}
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@ -413,6 +438,8 @@ static int q6v5_reset_deassert(struct q6v5 *qproc)
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ret = reset_control_reset(qproc->mss_restart);
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writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
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reset_control_deassert(qproc->pdc_reset);
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} else if (qproc->has_halt_nav) {
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ret = reset_control_reset(qproc->mss_restart);
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} else {
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ret = reset_control_deassert(qproc->mss_restart);
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}
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@ -499,6 +526,54 @@ static int q6v5proc_reset(struct q6v5 *qproc)
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return ret;
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}
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goto pbl_wait;
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} else if (qproc->version == MSS_SC7180) {
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val = readl(qproc->reg_base + QDSP6SS_SLEEP);
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val |= 0x1;
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writel(val, qproc->reg_base + QDSP6SS_SLEEP);
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ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
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val, !(val & BIT(31)), 1,
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SLEEP_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
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return -ETIMEDOUT;
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}
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/* Turn on the XO clock needed for PLL setup */
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val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
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val |= 0x1;
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writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
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ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
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val, !(val & BIT(31)), 1,
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SLEEP_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
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return -ETIMEDOUT;
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}
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/* Configure Q6 core CBCR to auto-enable after reset sequence */
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val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
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val |= 0x1;
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writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
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/* De-assert the Q6 stop core signal */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
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/* Trigger the boot FSM to start the Q6 out-of-reset sequence */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
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/* Poll the QDSP6SS_BOOT_STATUS for FSM completion */
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ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_BOOT_STATUS,
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val, (val & BIT(0)) != 0, 1,
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SLEEP_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(qproc->dev, "Boot FSM failed to complete.\n");
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/* Reset the modem so that boot FSM is in reset state */
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q6v5_reset_deassert(qproc);
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return ret;
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}
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goto pbl_wait;
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} else if (qproc->version == MSS_MSM8996 ||
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qproc->version == MSS_MSM8998) {
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@ -667,6 +742,39 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
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regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
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}
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static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc,
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struct regmap *halt_map,
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u32 offset)
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{
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unsigned long timeout;
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unsigned int val;
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int ret;
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/* Check if we're already idle */
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ret = regmap_read(halt_map, offset, &val);
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if (!ret && (val & NAV_AXI_IDLE_BIT))
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return;
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/* Assert halt request */
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regmap_update_bits(halt_map, offset, NAV_AXI_HALTREQ_BIT,
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NAV_AXI_HALTREQ_BIT);
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/* Wait for halt ack*/
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timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
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for (;;) {
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ret = regmap_read(halt_map, offset, &val);
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if (ret || (val & NAV_AXI_HALTACK_BIT) ||
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time_after(jiffies, timeout))
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break;
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udelay(5);
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}
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ret = regmap_read(halt_map, offset, &val);
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if (ret || !(val & NAV_AXI_IDLE_BIT))
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dev_err(qproc->dev, "port failed halt\n");
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}
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static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
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{
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unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
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@ -829,6 +937,9 @@ static int q6v5_mba_load(struct q6v5 *qproc)
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halt_axi_ports:
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
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if (qproc->has_halt_nav)
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q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map,
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qproc->halt_nav);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
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reclaim_mba:
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@ -876,6 +987,9 @@ static void q6v5_mba_reclaim(struct q6v5 *qproc)
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
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if (qproc->has_halt_nav)
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q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map,
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qproc->halt_nav);
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q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
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if (qproc->version == MSS_MSM8996) {
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/*
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@ -1253,6 +1367,47 @@ static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
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qproc->halt_modem = args.args[1];
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qproc->halt_nc = args.args[2];
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if (qproc->has_halt_nav) {
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struct platform_device *nav_pdev;
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,halt-nav-regs",
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1, 0, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse halt-nav-regs\n");
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return -EINVAL;
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}
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nav_pdev = of_find_device_by_node(args.np);
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of_node_put(args.np);
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if (!nav_pdev) {
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dev_err(&pdev->dev, "failed to get mss clock device\n");
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return -EPROBE_DEFER;
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}
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qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, NULL);
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if (!qproc->halt_nav_map) {
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dev_err(&pdev->dev, "failed to get map from device\n");
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return -EINVAL;
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}
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qproc->halt_nav = args.args[0];
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ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
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"qcom,halt-nav-regs",
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1, 1, &args);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to parse halt-nav-regs\n");
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return -EINVAL;
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}
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qproc->conn_map = syscon_node_to_regmap(args.np);
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of_node_put(args.np);
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if (IS_ERR(qproc->conn_map))
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return PTR_ERR(qproc->conn_map);
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qproc->conn_box = args.args[0];
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}
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return 0;
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}
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@ -1327,7 +1482,7 @@ static int q6v5_init_reset(struct q6v5 *qproc)
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return PTR_ERR(qproc->mss_restart);
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}
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if (qproc->has_alt_reset) {
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if (qproc->has_alt_reset || qproc->has_halt_nav) {
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qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
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"pdc_reset");
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if (IS_ERR(qproc->pdc_reset)) {
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@ -1426,6 +1581,7 @@ static int q6v5_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, qproc);
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qproc->has_halt_nav = desc->has_halt_nav;
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ret = q6v5_init_mem(qproc, pdev);
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if (ret)
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goto free_rproc;
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@ -1549,6 +1705,41 @@ static int q6v5_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct rproc_hexagon_res sc7180_mss = {
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.hexagon_mba_image = "mba.mbn",
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.proxy_clk_names = (char*[]){
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"xo",
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NULL
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},
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.reset_clk_names = (char*[]){
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"iface",
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"bus",
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"snoc_axi",
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NULL
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},
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.active_clk_names = (char*[]){
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"mnoc_axi",
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"nav",
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"mss_nav",
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"mss_crypto",
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NULL
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},
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.active_pd_names = (char*[]){
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"load_state",
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NULL
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},
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.proxy_pd_names = (char*[]){
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"cx",
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"mx",
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"mss",
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NULL
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},
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.need_mem_protection = true,
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.has_alt_reset = false,
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.has_halt_nav = true,
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.version = MSS_SC7180,
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};
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static const struct rproc_hexagon_res sdm845_mss = {
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.hexagon_mba_image = "mba.mbn",
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.proxy_clk_names = (char*[]){
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@ -1580,6 +1771,7 @@ static const struct rproc_hexagon_res sdm845_mss = {
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},
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.need_mem_protection = true,
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.has_alt_reset = true,
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.has_halt_nav = false,
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.version = MSS_SDM845,
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};
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@ -1606,6 +1798,7 @@ static const struct rproc_hexagon_res msm8998_mss = {
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},
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.need_mem_protection = true,
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.has_alt_reset = false,
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.has_halt_nav = false,
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.version = MSS_MSM8998,
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};
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@ -1635,6 +1828,7 @@ static const struct rproc_hexagon_res msm8996_mss = {
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},
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.need_mem_protection = true,
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.has_alt_reset = false,
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.has_halt_nav = false,
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.version = MSS_MSM8996,
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};
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@ -1667,6 +1861,7 @@ static const struct rproc_hexagon_res msm8916_mss = {
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},
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.need_mem_protection = false,
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.has_alt_reset = false,
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.has_halt_nav = false,
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.version = MSS_MSM8916,
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};
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@ -1707,6 +1902,7 @@ static const struct rproc_hexagon_res msm8974_mss = {
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},
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.need_mem_protection = false,
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.has_alt_reset = false,
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.has_halt_nav = false,
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.version = MSS_MSM8974,
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};
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@ -1716,6 +1912,7 @@ static const struct of_device_id q6v5_of_match[] = {
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{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
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{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
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{ .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
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{ .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
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{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
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{ },
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};
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