tg3: Convert u32 flag,flg2,flg3 uses to bitmap
Using a bitmap instead of separate u32 flags allows a consistent, simpler and more extensible mechanism to determine capabilities. Convert bitmasks to enum. Add tg3_flag, tg3_flag_clear and tg3_flag_set. Convert the flag & bitmask tests. Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Joe Perches
David S. Miller
parent
fa2bd7ff92
commit
63c3a66fe6
1299
drivers/net/tg3.c
1299
drivers/net/tg3.c
File diff suppressed because it is too large
Load Diff
@ -2816,6 +2816,86 @@ struct tg3_napi {
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unsigned int irq_vec;
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};
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enum TG3_FLAGS {
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TG3_FLAG_TAGGED_STATUS = 0,
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TG3_FLAG_TXD_MBOX_HWBUG,
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TG3_FLAG_USE_LINKCHG_REG,
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TG3_FLAG_ERROR_PROCESSED,
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TG3_FLAG_ENABLE_ASF,
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TG3_FLAG_ASPM_WORKAROUND,
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TG3_FLAG_POLL_SERDES,
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TG3_FLAG_MBOX_WRITE_REORDER,
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TG3_FLAG_PCIX_TARGET_HWBUG,
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TG3_FLAG_WOL_SPEED_100MB,
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TG3_FLAG_WOL_ENABLE,
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TG3_FLAG_EEPROM_WRITE_PROT,
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TG3_FLAG_NVRAM,
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TG3_FLAG_NVRAM_BUFFERED,
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TG3_FLAG_SUPPORT_MSI,
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TG3_FLAG_SUPPORT_MSIX,
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TG3_FLAG_PCIX_MODE,
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TG3_FLAG_PCI_HIGH_SPEED,
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TG3_FLAG_PCI_32BIT,
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TG3_FLAG_SRAM_USE_CONFIG,
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TG3_FLAG_TX_RECOVERY_PENDING,
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TG3_FLAG_WOL_CAP,
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TG3_FLAG_JUMBO_RING_ENABLE,
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TG3_FLAG_PAUSE_AUTONEG,
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TG3_FLAG_CPMU_PRESENT,
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TG3_FLAG_40BIT_DMA_BUG,
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TG3_FLAG_BROKEN_CHECKSUMS,
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TG3_FLAG_JUMBO_CAPABLE,
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TG3_FLAG_CHIP_RESETTING,
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TG3_FLAG_INIT_COMPLETE,
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TG3_FLAG_RESTART_TIMER,
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TG3_FLAG_TSO_BUG,
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TG3_FLAG_IS_5788,
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TG3_FLAG_MAX_RXPEND_64,
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TG3_FLAG_TSO_CAPABLE,
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TG3_FLAG_PCI_EXPRESS,
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TG3_FLAG_ASF_NEW_HANDSHAKE,
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TG3_FLAG_HW_AUTONEG,
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TG3_FLAG_IS_NIC,
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TG3_FLAG_FLASH,
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TG3_FLAG_HW_TSO_1,
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TG3_FLAG_5705_PLUS,
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TG3_FLAG_5750_PLUS,
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TG3_FLAG_HW_TSO_3,
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TG3_FLAG_USING_MSI,
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TG3_FLAG_USING_MSIX,
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TG3_FLAG_ICH_WORKAROUND,
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TG3_FLAG_5780_CLASS,
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TG3_FLAG_HW_TSO_2,
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TG3_FLAG_1SHOT_MSI,
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TG3_FLAG_NO_FWARE_REPORTED,
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TG3_FLAG_NO_NVRAM_ADDR_TRANS,
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TG3_FLAG_ENABLE_APE,
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TG3_FLAG_PROTECTED_NVRAM,
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TG3_FLAG_5701_DMA_BUG,
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TG3_FLAG_USE_PHYLIB,
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TG3_FLAG_MDIOBUS_INITED,
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TG3_FLAG_LRG_PROD_RING_CAP,
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TG3_FLAG_RGMII_INBAND_DISABLE,
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TG3_FLAG_RGMII_EXT_IBND_RX_EN,
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TG3_FLAG_RGMII_EXT_IBND_TX_EN,
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TG3_FLAG_CLKREQ_BUG,
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TG3_FLAG_5755_PLUS,
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TG3_FLAG_NO_NVRAM,
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TG3_FLAG_ENABLE_RSS,
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TG3_FLAG_ENABLE_TSS,
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TG3_FLAG_4G_DMA_BNDRY_BUG,
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TG3_FLAG_40BIT_DMA_LIMIT_BUG,
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TG3_FLAG_SHORT_DMA_BUG,
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TG3_FLAG_USE_JUMBO_BDFLAG,
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TG3_FLAG_L1PLLPD_EN,
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TG3_FLAG_57765_PLUS,
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TG3_FLAG_APE_HAS_NCSI,
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TG3_FLAG_5717_PLUS,
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/* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
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TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
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};
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struct tg3 {
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/* begin "general, frequently-used members" cacheline section */
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@ -2839,7 +2919,7 @@ struct tg3 {
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/* SMP locking strategy:
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*
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* lock: Held during reset, PHY access, timer, and when
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* updating tg3_flags and tg3_flags2.
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* updating tg3_flags.
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*
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* netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
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* netif_tx_lock when it needs to call
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@ -2896,95 +2976,13 @@ struct tg3 {
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struct tg3_ethtool_stats estats;
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struct tg3_ethtool_stats estats_prev;
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DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
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union {
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unsigned long phy_crc_errors;
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unsigned long last_event_jiffies;
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};
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u32 tg3_flags;
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#define TG3_FLAG_TAGGED_STATUS 0x00000001
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#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
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#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
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#define TG3_FLAG_ERROR_PROCESSED 0x00000010
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#define TG3_FLAG_ENABLE_ASF 0x00000020
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#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
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#define TG3_FLAG_POLL_SERDES 0x00000080
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#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
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#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
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#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
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#define TG3_FLAG_WOL_ENABLE 0x00000800
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#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
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#define TG3_FLAG_NVRAM 0x00002000
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#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
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#define TG3_FLAG_SUPPORT_MSI 0x00008000
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#define TG3_FLAG_SUPPORT_MSIX 0x00010000
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#define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
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TG3_FLAG_SUPPORT_MSIX)
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#define TG3_FLAG_PCIX_MODE 0x00020000
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#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
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#define TG3_FLAG_PCI_32BIT 0x00080000
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#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
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#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
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#define TG3_FLAG_WOL_CAP 0x00400000
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#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
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#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
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#define TG3_FLAG_CPMU_PRESENT 0x04000000
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#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
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#define TG3_FLAG_JUMBO_CAPABLE 0x20000000
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#define TG3_FLAG_CHIP_RESETTING 0x40000000
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#define TG3_FLAG_INIT_COMPLETE 0x80000000
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u32 tg3_flags2;
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#define TG3_FLG2_RESTART_TIMER 0x00000001
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#define TG3_FLG2_TSO_BUG 0x00000002
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#define TG3_FLG2_IS_5788 0x00000008
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#define TG3_FLG2_MAX_RXPEND_64 0x00000010
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#define TG3_FLG2_TSO_CAPABLE 0x00000020
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#define TG3_FLG2_PCI_EXPRESS 0x00000200
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#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
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#define TG3_FLG2_HW_AUTONEG 0x00000800
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#define TG3_FLG2_IS_NIC 0x00001000
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#define TG3_FLG2_FLASH 0x00008000
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#define TG3_FLG2_HW_TSO_1 0x00010000
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#define TG3_FLG2_5705_PLUS 0x00040000
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#define TG3_FLG2_5750_PLUS 0x00080000
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#define TG3_FLG2_HW_TSO_3 0x00100000
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#define TG3_FLG2_USING_MSI 0x00200000
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#define TG3_FLG2_USING_MSIX 0x00400000
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#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
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TG3_FLG2_USING_MSIX)
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#define TG3_FLG2_ICH_WORKAROUND 0x02000000
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#define TG3_FLG2_5780_CLASS 0x04000000
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#define TG3_FLG2_HW_TSO_2 0x08000000
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
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TG3_FLG2_HW_TSO_2 | \
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TG3_FLG2_HW_TSO_3)
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
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u32 tg3_flags3;
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#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
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#define TG3_FLG3_ENABLE_APE 0x00000002
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#define TG3_FLG3_PROTECTED_NVRAM 0x00000004
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#define TG3_FLG3_5701_DMA_BUG 0x00000008
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#define TG3_FLG3_USE_PHYLIB 0x00000010
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#define TG3_FLG3_MDIOBUS_INITED 0x00000020
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#define TG3_FLG3_LRG_PROD_RING_CAP 0x00000080
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#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
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#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
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#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
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#define TG3_FLG3_CLKREQ_BUG 0x00000800
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#define TG3_FLG3_5755_PLUS 0x00002000
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#define TG3_FLG3_NO_NVRAM 0x00004000
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#define TG3_FLG3_ENABLE_RSS 0x00020000
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#define TG3_FLG3_ENABLE_TSS 0x00040000
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#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
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#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
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#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
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#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
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#define TG3_FLG3_L1PLLPD_EN 0x00800000
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#define TG3_FLG3_57765_PLUS 0x01000000
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#define TG3_FLG3_APE_HAS_NCSI 0x02000000
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#define TG3_FLG3_5717_PLUS 0x04000000
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struct timer_list timer;
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u16 timer_counter;
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u16 timer_multiplier;
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