spi: spi-pxa2xx: remove legacy PXA DMA bits
Generic DMA support was already implemented by commit cd7bed0034
("spi/pxa2xx: break out the private DMA API usage into a separate file")
which moved all the legacy PXA DMA implementation code into its own
file.
With generic DMA available for PXA, we can now just trash this file.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Mark Brown <broonie@linaro.org>
[respin after pxa dmaengine support upstream]
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Daniel Mack
Mark Brown
parent
82ba2c2ab3
commit
6356437e65
@ -393,16 +393,9 @@ config SPI_PPC4xx
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help
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help
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This selects a driver for the PPC4xx SPI Controller.
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This selects a driver for the PPC4xx SPI Controller.
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config SPI_PXA2XX_PXADMA
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bool "PXA2xx SSP legacy PXA DMA API support"
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depends on SPI_PXA2XX && ARCH_PXA
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help
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Enable PXA private legacy DMA API support. Note that this is
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deprecated in favor of generic DMA engine API.
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config SPI_PXA2XX_DMA
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config SPI_PXA2XX_DMA
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def_bool y
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def_bool y
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depends on SPI_PXA2XX && !SPI_PXA2XX_PXADMA
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depends on SPI_PXA2XX
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config SPI_PXA2XX
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config SPI_PXA2XX
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tristate "PXA2xx SSP SPI master"
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tristate "PXA2xx SSP SPI master"
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@ -60,7 +60,6 @@ obj-$(CONFIG_SPI_ORION) += spi-orion.o
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obj-$(CONFIG_SPI_PL022) += spi-pl022.o
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obj-$(CONFIG_SPI_PL022) += spi-pl022.o
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obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
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obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o
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spi-pxa2xx-platform-objs := spi-pxa2xx.o
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spi-pxa2xx-platform-objs := spi-pxa2xx.o
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spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_PXADMA) += spi-pxa2xx-pxadma.o
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spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
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spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA) += spi-pxa2xx-dma.o
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obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
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@ -1,487 +0,0 @@
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/*
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* PXA2xx SPI private DMA support.
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*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <mach/dma.h>
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#include "spi-pxa2xx.h"
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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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#define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
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bool pxa2xx_spi_dma_is_possible(size_t len)
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{
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/* Try to map dma buffer and do a dma transfer if successful, but
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* only if the length is non-zero and less than MAX_DMA_LEN.
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*
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* Zero-length non-descriptor DMA is illegal on PXA2xx; force use
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* of PIO instead. Care is needed above because the transfer may
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* have have been passed with buffers that are already dma mapped.
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* A zero-length transfer in PIO mode will not try to write/read
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* to/from the buffers
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*
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* REVISIT large transfers are exactly where we most want to be
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* using DMA. If this happens much, split those transfers into
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* multiple DMA segments rather than forcing PIO.
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*/
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return len > 0 && len <= MAX_DMA_LEN;
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}
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int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
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{
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struct spi_message *msg = drv_data->cur_msg;
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struct device *dev = &msg->spi->dev;
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if (!drv_data->cur_chip->enable_dma)
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return 0;
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if (msg->is_dma_mapped)
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return drv_data->rx_dma && drv_data->tx_dma;
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if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
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return 0;
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/* Modify setup if rx buffer is null */
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if (drv_data->rx == NULL) {
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*drv_data->null_dma_buf = 0;
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drv_data->rx = drv_data->null_dma_buf;
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drv_data->rx_map_len = 4;
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} else
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drv_data->rx_map_len = drv_data->len;
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/* Modify setup if tx buffer is null */
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if (drv_data->tx == NULL) {
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*drv_data->null_dma_buf = 0;
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drv_data->tx = drv_data->null_dma_buf;
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drv_data->tx_map_len = 4;
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} else
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drv_data->tx_map_len = drv_data->len;
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/* Stream map the tx buffer. Always do DMA_TO_DEVICE first
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* so we flush the cache *before* invalidating it, in case
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* the tx and rx buffers overlap.
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*/
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drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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if (dma_mapping_error(dev, drv_data->tx_dma))
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return 0;
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/* Stream map the rx buffer */
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drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
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drv_data->rx_map_len, DMA_FROM_DEVICE);
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if (dma_mapping_error(dev, drv_data->rx_dma)) {
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dma_unmap_single(dev, drv_data->tx_dma,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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return 0;
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}
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return 1;
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}
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static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
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{
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struct device *dev;
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if (!drv_data->dma_mapped)
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return;
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if (!drv_data->cur_msg->is_dma_mapped) {
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dev = &drv_data->cur_msg->spi->dev;
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dma_unmap_single(dev, drv_data->rx_dma,
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drv_data->rx_map_len, DMA_FROM_DEVICE);
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dma_unmap_single(dev, drv_data->tx_dma,
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drv_data->tx_map_len, DMA_TO_DEVICE);
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}
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drv_data->dma_mapped = 0;
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}
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static int wait_ssp_rx_stall(struct driver_data *drv_data)
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{
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unsigned long limit = loops_per_jiffy << 1;
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while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
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cpu_relax();
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return limit;
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}
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static int wait_dma_channel_stop(int channel)
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{
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unsigned long limit = loops_per_jiffy << 1;
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while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
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cpu_relax();
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return limit;
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}
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static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
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const char *msg)
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{
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/* Stop and reset */
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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if (!pxa25x_ssp_comp(drv_data))
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pxa2xx_spi_write(drv_data, SSTO, 0);
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pxa2xx_spi_flush(drv_data);
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pxa2xx_spi_write(drv_data, SSCR0,
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pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
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pxa2xx_spi_unmap_dma_buffers(drv_data);
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dev_err(&drv_data->pdev->dev, "%s\n", msg);
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drv_data->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&drv_data->pump_transfers);
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}
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
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{
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struct spi_message *msg = drv_data->cur_msg;
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/* Clear and disable interrupts on SSP and DMA channels*/
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_handler: dma rx channel stop failed\n");
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if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_transfer: ssp rx stall failed\n");
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pxa2xx_spi_unmap_dma_buffers(drv_data);
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/* update the buffer pointer for the amount completed in dma */
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drv_data->rx += drv_data->len -
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(DCMD(drv_data->rx_channel) & DCMD_LENGTH);
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/* read trailing data from fifo, it does not matter how many
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* bytes are in the fifo just read until buffer is full
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* or fifo is empty, which ever occurs first */
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drv_data->read(drv_data);
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/* return count of what was actually read */
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msg->actual_length += drv_data->len -
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(drv_data->rx_end - drv_data->rx);
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/* Transfer delays and chip select release are
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* handled in pump_transfers or giveback
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*/
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/* Move to next transfer */
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msg->state = pxa2xx_spi_next_transfer(drv_data);
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/* Schedule transfer tasklet */
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tasklet_schedule(&drv_data->pump_transfers);
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}
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void pxa2xx_spi_dma_handler(int channel, void *data)
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{
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struct driver_data *drv_data = data;
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u32 irq_status = DCSR(channel) & DMA_INT_MASK;
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if (irq_status & DCSR_BUSERR) {
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if (channel == drv_data->tx_channel)
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pxa2xx_spi_dma_error_stop(drv_data,
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"dma_handler: bad bus address on tx channel");
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else
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pxa2xx_spi_dma_error_stop(drv_data,
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"dma_handler: bad bus address on rx channel");
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return;
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}
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/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
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if ((channel == drv_data->tx_channel)
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&& (irq_status & DCSR_ENDINTR)
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&& (drv_data->ssp_type == PXA25x_SSP)) {
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/* Wait for rx to stall */
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if (wait_ssp_rx_stall(drv_data) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_handler: ssp rx stall failed\n");
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/* finish this transfer, start the next */
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pxa2xx_spi_dma_transfer_complete(drv_data);
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}
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}
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irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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u32 irq_status;
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irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
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if (irq_status & SSSR_ROR) {
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pxa2xx_spi_dma_error_stop(drv_data,
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"dma_transfer: fifo overrun");
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return IRQ_HANDLED;
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}
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/* Check for false positive timeout */
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if ((irq_status & SSSR_TINT)
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&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
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pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
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return IRQ_HANDLED;
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}
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if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
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/* Clear and disable timeout interrupt, do the rest in
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* dma_transfer_complete */
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if (!pxa25x_ssp_comp(drv_data))
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pxa2xx_spi_write(drv_data, SSTO, 0);
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/* finish this transfer, start the next */
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pxa2xx_spi_dma_transfer_complete(drv_data);
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return IRQ_HANDLED;
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}
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/* Opps problem detected */
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return IRQ_NONE;
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}
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int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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{
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u32 dma_width;
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switch (drv_data->n_bytes) {
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case 1:
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dma_width = DCMD_WIDTH1;
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break;
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case 2:
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dma_width = DCMD_WIDTH2;
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break;
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default:
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dma_width = DCMD_WIDTH4;
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break;
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}
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/* Setup rx DMA Channel */
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
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DTADR(drv_data->rx_channel) = drv_data->rx_dma;
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if (drv_data->rx == drv_data->null_dma_buf)
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/* No target address increment */
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DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
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| dma_width
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| dma_burst
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| drv_data->len;
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else
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DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
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| DCMD_FLOWSRC
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| dma_width
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| dma_burst
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| drv_data->len;
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/* Setup tx DMA Channel */
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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DSADR(drv_data->tx_channel) = drv_data->tx_dma;
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DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
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if (drv_data->tx == drv_data->null_dma_buf)
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/* No source address increment */
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DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
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| dma_width
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| dma_burst
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| drv_data->len;
|
|
||||||
else
|
|
||||||
DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
|
|
||||||
| DCMD_FLOWTRG
|
|
||||||
| dma_width
|
|
||||||
| dma_burst
|
|
||||||
| drv_data->len;
|
|
||||||
|
|
||||||
/* Enable dma end irqs on SSP to detect end of transfer */
|
|
||||||
if (drv_data->ssp_type == PXA25x_SSP)
|
|
||||||
DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void pxa2xx_spi_dma_start(struct driver_data *drv_data)
|
|
||||||
{
|
|
||||||
DCSR(drv_data->rx_channel) |= DCSR_RUN;
|
|
||||||
DCSR(drv_data->tx_channel) |= DCSR_RUN;
|
|
||||||
}
|
|
||||||
|
|
||||||
int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
|
|
||||||
{
|
|
||||||
struct device *dev = &drv_data->pdev->dev;
|
|
||||||
struct ssp_device *ssp = drv_data->ssp;
|
|
||||||
|
|
||||||
/* Get two DMA channels (rx and tx) */
|
|
||||||
drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
|
|
||||||
DMA_PRIO_HIGH,
|
|
||||||
pxa2xx_spi_dma_handler,
|
|
||||||
drv_data);
|
|
||||||
if (drv_data->rx_channel < 0) {
|
|
||||||
dev_err(dev, "problem (%d) requesting rx channel\n",
|
|
||||||
drv_data->rx_channel);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
|
|
||||||
DMA_PRIO_MEDIUM,
|
|
||||||
pxa2xx_spi_dma_handler,
|
|
||||||
drv_data);
|
|
||||||
if (drv_data->tx_channel < 0) {
|
|
||||||
dev_err(dev, "problem (%d) requesting tx channel\n",
|
|
||||||
drv_data->tx_channel);
|
|
||||||
pxa_free_dma(drv_data->rx_channel);
|
|
||||||
return -ENODEV;
|
|
||||||
}
|
|
||||||
|
|
||||||
DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
|
|
||||||
DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void pxa2xx_spi_dma_release(struct driver_data *drv_data)
|
|
||||||
{
|
|
||||||
struct ssp_device *ssp = drv_data->ssp;
|
|
||||||
|
|
||||||
DRCMR(ssp->drcmr_rx) = 0;
|
|
||||||
DRCMR(ssp->drcmr_tx) = 0;
|
|
||||||
|
|
||||||
if (drv_data->tx_channel != 0)
|
|
||||||
pxa_free_dma(drv_data->tx_channel);
|
|
||||||
if (drv_data->rx_channel != 0)
|
|
||||||
pxa_free_dma(drv_data->rx_channel);
|
|
||||||
}
|
|
||||||
|
|
||||||
void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
|
|
||||||
{
|
|
||||||
if (drv_data->rx_channel != -1)
|
|
||||||
DRCMR(drv_data->ssp->drcmr_rx) =
|
|
||||||
DRCMR_MAPVLD | drv_data->rx_channel;
|
|
||||||
if (drv_data->tx_channel != -1)
|
|
||||||
DRCMR(drv_data->ssp->drcmr_tx) =
|
|
||||||
DRCMR_MAPVLD | drv_data->tx_channel;
|
|
||||||
}
|
|
||||||
|
|
||||||
int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
|
|
||||||
struct spi_device *spi,
|
|
||||||
u8 bits_per_word, u32 *burst_code,
|
|
||||||
u32 *threshold)
|
|
||||||
{
|
|
||||||
struct pxa2xx_spi_chip *chip_info =
|
|
||||||
(struct pxa2xx_spi_chip *)spi->controller_data;
|
|
||||||
int bytes_per_word;
|
|
||||||
int burst_bytes;
|
|
||||||
int thresh_words;
|
|
||||||
int req_burst_size;
|
|
||||||
int retval = 0;
|
|
||||||
|
|
||||||
/* Set the threshold (in registers) to equal the same amount of data
|
|
||||||
* as represented by burst size (in bytes). The computation below
|
|
||||||
* is (burst_size rounded up to nearest 8 byte, word or long word)
|
|
||||||
* divided by (bytes/register); the tx threshold is the inverse of
|
|
||||||
* the rx, so that there will always be enough data in the rx fifo
|
|
||||||
* to satisfy a burst, and there will always be enough space in the
|
|
||||||
* tx fifo to accept a burst (a tx burst will overwrite the fifo if
|
|
||||||
* there is not enough space), there must always remain enough empty
|
|
||||||
* space in the rx fifo for any data loaded to the tx fifo.
|
|
||||||
* Whenever burst_size (in bytes) equals bits/word, the fifo threshold
|
|
||||||
* will be 8, or half the fifo;
|
|
||||||
* The threshold can only be set to 2, 4 or 8, but not 16, because
|
|
||||||
* to burst 16 to the tx fifo, the fifo would have to be empty;
|
|
||||||
* however, the minimum fifo trigger level is 1, and the tx will
|
|
||||||
* request service when the fifo is at this level, with only 15 spaces.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* find bytes/word */
|
|
||||||
if (bits_per_word <= 8)
|
|
||||||
bytes_per_word = 1;
|
|
||||||
else if (bits_per_word <= 16)
|
|
||||||
bytes_per_word = 2;
|
|
||||||
else
|
|
||||||
bytes_per_word = 4;
|
|
||||||
|
|
||||||
/* use struct pxa2xx_spi_chip->dma_burst_size if available */
|
|
||||||
if (chip_info)
|
|
||||||
req_burst_size = chip_info->dma_burst_size;
|
|
||||||
else {
|
|
||||||
switch (chip->dma_burst_size) {
|
|
||||||
default:
|
|
||||||
/* if the default burst size is not set,
|
|
||||||
* do it now */
|
|
||||||
chip->dma_burst_size = DCMD_BURST8;
|
|
||||||
case DCMD_BURST8:
|
|
||||||
req_burst_size = 8;
|
|
||||||
break;
|
|
||||||
case DCMD_BURST16:
|
|
||||||
req_burst_size = 16;
|
|
||||||
break;
|
|
||||||
case DCMD_BURST32:
|
|
||||||
req_burst_size = 32;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (req_burst_size <= 8) {
|
|
||||||
*burst_code = DCMD_BURST8;
|
|
||||||
burst_bytes = 8;
|
|
||||||
} else if (req_burst_size <= 16) {
|
|
||||||
if (bytes_per_word == 1) {
|
|
||||||
/* don't burst more than 1/2 the fifo */
|
|
||||||
*burst_code = DCMD_BURST8;
|
|
||||||
burst_bytes = 8;
|
|
||||||
retval = 1;
|
|
||||||
} else {
|
|
||||||
*burst_code = DCMD_BURST16;
|
|
||||||
burst_bytes = 16;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (bytes_per_word == 1) {
|
|
||||||
/* don't burst more than 1/2 the fifo */
|
|
||||||
*burst_code = DCMD_BURST8;
|
|
||||||
burst_bytes = 8;
|
|
||||||
retval = 1;
|
|
||||||
} else if (bytes_per_word == 2) {
|
|
||||||
/* don't burst more than 1/2 the fifo */
|
|
||||||
*burst_code = DCMD_BURST16;
|
|
||||||
burst_bytes = 16;
|
|
||||||
retval = 1;
|
|
||||||
} else {
|
|
||||||
*burst_code = DCMD_BURST32;
|
|
||||||
burst_bytes = 32;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
thresh_words = burst_bytes / bytes_per_word;
|
|
||||||
|
|
||||||
/* thresh_words will be between 2 and 8 */
|
|
||||||
*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
|
|
||||||
| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
|
|
||||||
|
|
||||||
return retval;
|
|
||||||
}
|
|
||||||
@ -162,11 +162,7 @@ extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data);
|
|||||||
/*
|
/*
|
||||||
* Select the right DMA implementation.
|
* Select the right DMA implementation.
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_SPI_PXA2XX_PXADMA)
|
#if defined(CONFIG_SPI_PXA2XX_DMA)
|
||||||
#define SPI_PXA2XX_USE_DMA 1
|
|
||||||
#define MAX_DMA_LEN 8191
|
|
||||||
#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE)
|
|
||||||
#elif defined(CONFIG_SPI_PXA2XX_DMA)
|
|
||||||
#define SPI_PXA2XX_USE_DMA 1
|
#define SPI_PXA2XX_USE_DMA 1
|
||||||
#define MAX_DMA_LEN SZ_64K
|
#define MAX_DMA_LEN SZ_64K
|
||||||
#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
|
#define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user