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drm/amd/amdgpu: Correct whitespace in GFX v8

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Fix various whitespace issues in gfx v8 driver.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom St Denis
2016-08-09 10:07:36 -04:00
committed by Alex Deucher
parent 9accf2fd33
commit 62d2ce4b09
1 changed files with 16 additions and 25 deletions
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41
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
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@@ -1232,10 +1232,9 @@ static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
if (adev->gfx.rlc.clear_state_obj) { if (adev->gfx.rlc.clear_state_obj) {
r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
if (unlikely(r != 0)) if (unlikely(r != 0))
dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r); dev_warn(adev->dev, "(%d) reserve RLC cbs bo failed\n", r);
amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
adev->gfx.rlc.clear_state_obj = NULL; adev->gfx.rlc.clear_state_obj = NULL;
} }
@@ -1247,7 +1246,6 @@ static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r); dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
adev->gfx.rlc.cp_table_obj = NULL; adev->gfx.rlc.cp_table_obj = NULL;
} }
@@ -1289,14 +1287,14 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
&adev->gfx.rlc.clear_state_gpu_addr); &adev->gfx.rlc.clear_state_gpu_addr);
if (r) { if (r) {
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r); dev_warn(adev->dev, "(%d) pin RLC cbs bo failed\n", r);
gfx_v8_0_rlc_fini(adev); gfx_v8_0_rlc_fini(adev);
return r; return r;
} }
r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
if (r) { if (r) {
dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r); dev_warn(adev->dev, "(%d) map RLC cbs bo failed\n", r);
gfx_v8_0_rlc_fini(adev); gfx_v8_0_rlc_fini(adev);
return r; return r;
} }
@@ -1331,7 +1329,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
&adev->gfx.rlc.cp_table_gpu_addr); &adev->gfx.rlc.cp_table_gpu_addr);
if (r) { if (r) {
amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r); dev_warn(adev->dev, "(%d) pin RLC cp table bo failed\n", r);
return r; return r;
} }
r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
@@ -1344,7 +1342,6 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
} }
return 0; return 0;
@@ -1360,7 +1357,6 @@ static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r); dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
adev->gfx.mec.hpd_eop_obj = NULL; adev->gfx.mec.hpd_eop_obj = NULL;
} }
@@ -2123,9 +2119,7 @@ static int gfx_v8_0_sw_fini(void *handle)
amdgpu_ring_fini(&adev->gfx.compute_ring[i]); amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
gfx_v8_0_mec_fini(adev); gfx_v8_0_mec_fini(adev);
gfx_v8_0_rlc_fini(adev); gfx_v8_0_rlc_fini(adev);
gfx_v8_0_free_microcode(adev); gfx_v8_0_free_microcode(adev);
return 0; return 0;
@@ -3581,7 +3575,6 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
gfx_v8_0_tiling_mode_table_init(adev); gfx_v8_0_tiling_mode_table_init(adev);
gfx_v8_0_setup_rb(adev); gfx_v8_0_setup_rb(adev);
gfx_v8_0_get_cu_info(adev); gfx_v8_0_get_cu_info(adev);
@@ -3994,14 +3987,13 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
/* disable CG */ /* disable CG */
WREG32(mmRLC_CGCG_CGLS_CTRL, 0); WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
if (adev->asic_type == CHIP_POLARIS11 || if (adev->asic_type == CHIP_POLARIS11 ||
adev->asic_type == CHIP_POLARIS10) adev->asic_type == CHIP_POLARIS10)
WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0);
/* disable PG */ /* disable PG */
WREG32(mmRLC_PG_CNTL, 0); WREG32(mmRLC_PG_CNTL, 0);
gfx_v8_0_rlc_reset(adev); gfx_v8_0_rlc_reset(adev);
gfx_v8_0_init_pg(adev); gfx_v8_0_init_pg(adev);
if (!adev->pp_enabled) { if (!adev->pp_enabled) {
@@ -4976,7 +4968,6 @@ static int gfx_v8_0_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
gfx_v8_0_init_golden_registers(adev); gfx_v8_0_init_golden_registers(adev);
gfx_v8_0_gpu_init(adev); gfx_v8_0_gpu_init(adev);
r = gfx_v8_0_rlc_resume(adev); r = gfx_v8_0_rlc_resume(adev);
@@ -5548,15 +5539,15 @@ static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
data = RREG32(mmRLC_SERDES_WR_CTRL); data = RREG32(mmRLC_SERDES_WR_CTRL);
if (adev->asic_type == CHIP_STONEY) if (adev->asic_type == CHIP_STONEY)
data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
RLC_SERDES_WR_CTRL__P1_SELECT_MASK | RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
RLC_SERDES_WR_CTRL__P2_SELECT_MASK | RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK | RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
RLC_SERDES_WR_CTRL__POWER_DOWN_MASK | RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
RLC_SERDES_WR_CTRL__POWER_UP_MASK | RLC_SERDES_WR_CTRL__POWER_UP_MASK |
RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK | RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK); RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
else else
data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK | data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
RLC_SERDES_WR_CTRL__READ_COMMAND_MASK | RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
@@ -6089,9 +6080,9 @@ static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
amdgpu_ring_write(ring, amdgpu_ring_write(ring,
#ifdef __BIG_ENDIAN #ifdef __BIG_ENDIAN
(2 << 0) | (2 << 0) |
#endif #endif
(ib->gpu_addr & 0xFFFFFFFC)); (ib->gpu_addr & 0xFFFFFFFC));
amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
amdgpu_ring_write(ring, control); amdgpu_ring_write(ring, control);
} }