forked from Minki/linux
ARM: dts: uniphier: factor out common nodes to uniphier-common32.dtsi
UniPhier SoCs (except PH1-sLD3) have several nodes in common. Factor out them into uniphier-common32.dtsi. This improves the code maintainability. PH1-sLD3 is so old that it has more or less different register maps than the others. So, it cannot be included in this refactoring. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Masahiro Yamada
Arnd Bergmann
parent
618a43eaea
commit
629b557ab4
135
arch/arm/boot/dts/uniphier-common32.dtsi
Normal file
135
arch/arm/boot/dts/uniphier-common32.dtsi
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@ -0,0 +1,135 @@
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/*
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* Device Tree Source commonly used by UniPhier ARM SoCs
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "skeleton.dtsi"
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/ {
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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extbus: extbus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&uart_clk>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&uart_clk>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&uart_clk>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&uart_clk>;
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};
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system-bus-controller@58c00000 {
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compatible = "socionext,uniphier-system-bus-controller";
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reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <1 11 0x104>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <1 13 0x104>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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pinctrl: pinctrl@5f801000 {
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/* specify compatible in each SoC DTSI */
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reg = <0x5f801000 0xe00>;
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};
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};
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};
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/include/ "uniphier-pinctrl.dtsi"
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@ -42,7 +42,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "skeleton.dtsi"
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/include/ "uniphier-common32.dtsi"
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/ {
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compatible = "socionext,ph1-ld4";
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@ -78,188 +78,105 @@
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clock-frequency = <100000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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extbus: extbus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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};
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(512 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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interrupts = <0 33 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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interrupts = <0 35 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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interrupts = <0 37 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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interrupts = <0 29 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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interrupts = <0 41 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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interrupts = <0 42 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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interrupts = <0 43 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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interrupts = <0 44 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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system-bus-controller@58c00000 {
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compatible = "socionext,uniphier-system-bus-controller";
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reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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interrupts = <0 80 4>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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interrupts = <0 81 4>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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interrupts = <0 82 4>;
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};
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pinctrl: pinctrl@5f801000 {
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compatible = "socionext,ph1-ld4-pinctrl",
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"syscon";
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reg = <0x5f801000 0xe00>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <1 11 0x104>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <1 13 0x104>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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};
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};
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};
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/include/ "uniphier-pinctrl.dtsi"
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&soc {
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(512 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 82 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb2>;
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};
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};
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&serial3 {
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interrupts = <0 29 4>;
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};
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&pinctrl {
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compatible = "socionext,ph1-ld4-pinctrl", "syscon";
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};
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@ -42,7 +42,7 @@
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* OTHER DEALINGS IN THE SOFTWARE.
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||||
*/
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/include/ "skeleton.dtsi"
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/include/ "uniphier-common32.dtsi"
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/ {
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compatible = "socionext,ph1-pro4";
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@ -86,203 +86,115 @@
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clock-frequency = <50000000>;
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};
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};
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};
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soc {
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compatible = "simple-bus";
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&soc {
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(768 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
extbus: extbus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(768 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
interrupts = <0 33 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
interrupts = <0 35 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
/* i2c4 does not exist */
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
interrupts = <0 37 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
/* chip-internal connection for DMD */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
interrupts = <0 177 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58780000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
interrupts = <0 41 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
usb2: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
interrupts = <0 42 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* i2c4 does not exist */
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system-bus-controller@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus-controller";
|
||||
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
|
||||
};
|
||||
|
||||
usb2: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
interrupts = <0 80 4>;
|
||||
};
|
||||
|
||||
usb3: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb3>;
|
||||
interrupts = <0 81 4>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@5f801000 {
|
||||
compatible = "socionext,ph1-pro4-pinctrl",
|
||||
"syscon";
|
||||
reg = <0x5f801000 0xe00>;
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
usb3: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb3>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-pro4-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "uniphier-common32.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "socionext,ph1-pro5";
|
||||
@ -86,193 +86,109 @@
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
&soc {
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
|
||||
interrupts = <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
|
||||
l3: l3-cache@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58780000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
extbus: extbus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3>;
|
||||
};
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
l3: l3-cache@500c8000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
|
||||
<0x506c8000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(2 * 1024 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <256>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
interrupts = <0 33 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
/* i2c4 does not exist */
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
interrupts = <0 35 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
/* chip-internal connection for DMD */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
interrupts = <0 37 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
interrupts = <0 177 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58780000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
interrupts = <0 41 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
interrupts = <0 42 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* i2c4 does not exist */
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system-bus-controller@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus-controller";
|
||||
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@5f801000 {
|
||||
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
|
||||
reg = <0x5f801000 0xe00>;
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x304>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x304>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-pro5-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "uniphier-common32.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "socionext,ph1-sld8";
|
||||
@ -78,188 +78,104 @@
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
&soc {
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(256 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
extbus: extbus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>;
|
||||
cache-unified;
|
||||
cache-size = <(256 * 1024)>;
|
||||
cache-sets = <256>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 43 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
interrupts = <0 33 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
interrupts = <0 35 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
interrupts = <0 80 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
interrupts = <0 37 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
interrupts = <0 81 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
interrupts = <0 29 4>;
|
||||
clocks = <&uart_clk>;
|
||||
fifo-size = <64>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58400000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58400000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
interrupts = <0 41 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58480000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58480000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
interrupts = <0 42 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c2: i2c@58500000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
reg = <0x58500000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
interrupts = <0 43 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58580000 {
|
||||
compatible = "socionext,uniphier-i2c";
|
||||
status = "disabled";
|
||||
reg = <0x58580000 0x40>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
interrupts = <0 44 1>;
|
||||
clocks = <&iobus_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
system-bus-controller@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus-controller";
|
||||
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
|
||||
};
|
||||
|
||||
usb0: usb@5a800100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a800100 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
interrupts = <0 80 4>;
|
||||
};
|
||||
|
||||
usb1: usb@5a810100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a810100 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
interrupts = <0 81 4>;
|
||||
};
|
||||
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
interrupts = <0 82 4>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@5f801000 {
|
||||
compatible = "socionext,ph1-sld8-pinctrl",
|
||||
"syscon";
|
||||
reg = <0x5f801000 0xe00>;
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0x104>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
usb2: usb@5a820100 {
|
||||
compatible = "socionext,uniphier-ehci", "generic-ehci";
|
||||
status = "disabled";
|
||||
reg = <0x5a820100 0x100>;
|
||||
interrupts = <0 82 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
&serial3 {
|
||||
interrupts = <0 29 4>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "socionext,ph1-sld8-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/include/ "uniphier-common32.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "socionext,proxstream2";
|
||||
@ -100,189 +100,106 @@
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
&soc {
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <(1280 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58780000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
interrupt-parent = <&intc>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 41 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
extbus: extbus {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 42 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
l2: l2-cache@500c0000 {
|
||||
compatible = "socionext,uniphier-system-cache";
|
||||
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
|
||||
<0x506c0000 0x400>;
|
||||
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
|
||||
cache-unified;
|
||||
cache-size = <(1280 * 1024)>;
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <128>;
|
||||
cache-level = <2>;
|
||||
};
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial0: serial@54006800 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006800 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0>;
|
||||
interrupts = <0 33 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 44 4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial1: serial@54006900 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006900 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
interrupts = <0 35 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
/* chip-internal connection for DMD */
|
||||
i2c4: i2c@58784000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
serial2: serial@54006a00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006a00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
interrupts = <0 37 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
/* chip-internal connection for STM */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
serial3: serial@54006b00 {
|
||||
compatible = "socionext,uniphier-uart";
|
||||
status = "disabled";
|
||||
reg = <0x54006b00 0x40>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
interrupts = <0 177 4>;
|
||||
clocks = <&uart_clk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@58780000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58780000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0>;
|
||||
interrupts = <0 41 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c1: i2c@58781000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58781000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
interrupts = <0 42 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c2: i2c@58782000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58782000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
interrupts = <0 43 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c3: i2c@58783000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
status = "disabled";
|
||||
reg = <0x58783000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
interrupts = <0 44 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for DMD */
|
||||
i2c4: i2c@58784000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58784000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 45 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for STM */
|
||||
i2c5: i2c@58785000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58785000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 25 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
system-bus-controller@58c00000 {
|
||||
compatible = "socionext,uniphier-system-bus-controller";
|
||||
reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@5f801000 {
|
||||
compatible = "socionext,proxstream2-pinctrl", "syscon";
|
||||
reg = <0x5f801000 0xe00>;
|
||||
};
|
||||
|
||||
timer@60000200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x60000200 0x20>;
|
||||
interrupts = <1 11 0xf04>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
timer@60000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x60000600 0x20>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
clocks = <&arm_timer_clk>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@60001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x60001000 0x1000>,
|
||||
<0x60000100 0x100>;
|
||||
};
|
||||
/* chip-internal connection for HDMI */
|
||||
i2c6: i2c@58786000 {
|
||||
compatible = "socionext,uniphier-fi2c";
|
||||
reg = <0x58786000 0x80>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <0 26 4>;
|
||||
clocks = <&i2c_clk>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "uniphier-pinctrl.dtsi"
|
||||
&pinctrl {
|
||||
compatible = "socionext,proxstream2-pinctrl", "syscon";
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user