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dt/bindings: drm/komeda: Unify mclk/pclk/pipeline->aclk to one ACLK

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Current komeda driver uses three dedicated clks for a specific purpose:
- mclk: main engine clock
- pclk: APB clock
- pipeline->aclk: AXI clock.

But per spec the komeda HW only has three input clks:
- ACLK: used for AXI masters, APB slave and most pipeline processing
- PXCLK for pipeline 0: output pixel clock for pipeline 0
- PXCLK for pipeline 1: output pixel clock for pipeline 1

So one ACLK is enough, no need to split it to three mclk/pclk/axiclk.

Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@arm.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
This commit is contained in:
james qian wang (Arm Technology China) 2019-06-05 11:35:45 +01:00 committed by Liviu Dudau
parent 6f84da0c74
commit 619053220a
1 changed files with 7 additions and 9 deletions
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16
Documentation/devicetree/bindings/display/arm,komeda.txt
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@ -7,8 +7,7 @@ Required properties:
- clocks: A list of phandle + clock-specifier pairs, one for each entry
in 'clock-names'
- clock-names: A list of clock names. It should contain:
- "mclk": for the main processor clock
- "pclk": for the APB interface clock
- "aclk": for the main processor clock
- #address-cells: Must be 1
- #size-cells: Must be 0
- iommus: configure the stream id to IOMMU, Must be configured if want to
@ -24,7 +23,6 @@ pipeline node should provide properties:
in 'clock-names'
- clock-names: should contain:
- "pxclk": pixel clock
- "aclk": AXI interface clock
- port: each pipeline connect to an encoder input port. The connection is
modeled using the OF graph bindings specified in
@ -46,15 +44,15 @@ Example:
compatible = "arm,mali-d71";
reg = <0xc00000 0x20000>;
interrupts = <0 168 4>;
clocks = <&dpu_mclk>, <&dpu_aclk>;
clock-names = "mclk", "pclk";
clocks = <&dpu_aclk>;
clock-names = "aclk";
iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
<&smmu 8>, <&smmu 9>;
dp0_pipe0: pipeline@0 {
clocks = <&fpgaosc2>, <&dpu_aclk>;
clock-names = "pxclk", "aclk";
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <0>;
port {
@ -65,8 +63,8 @@ Example:
};
dp0_pipe1: pipeline@1 {
clocks = <&fpgaosc2>, <&dpu_aclk>;
clock-names = "pxclk", "aclk";
clocks = <&fpgaosc2>;
clock-names = "pxclk";
reg = <1>;
port {